{ "pips": { "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_FIFO18_ADDRATIEHIGH0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL0" }, "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_FIFO36_ADDRARDADDRL0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL0" }, "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_UTURN_ADDRARDADDRL0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL0" }, "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_FIFO18_ADDRARDADDR0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL1" }, "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_FIFO36_ADDRARDADDRL1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL1" }, "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_UTURN_ADDRARDADDRL1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL1" }, "BRAM_L.BRAM_ADDRARDADDRL2->>BRAM_FIFO18_ADDRARDADDR1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL2" }, "BRAM_L.BRAM_ADDRARDADDRL2->>BRAM_FIFO36_ADDRARDADDRL2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL2" }, "BRAM_L.BRAM_ADDRARDADDRL2->>BRAM_UTURN_ADDRARDADDRL2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL2" }, "BRAM_L.BRAM_ADDRARDADDRL3->>BRAM_FIFO18_ADDRARDADDR2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL3" }, "BRAM_L.BRAM_ADDRARDADDRL3->>BRAM_FIFO36_ADDRARDADDRL3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL3" }, "BRAM_L.BRAM_ADDRARDADDRL3->>BRAM_UTURN_ADDRARDADDRL3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL3" }, "BRAM_L.BRAM_ADDRARDADDRL4->>BRAM_FIFO18_ADDRARDADDR3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL4" }, "BRAM_L.BRAM_ADDRARDADDRL4->>BRAM_FIFO36_ADDRARDADDRL4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL4" }, "BRAM_L.BRAM_ADDRARDADDRL4->>BRAM_UTURN_ADDRARDADDRL4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL4" }, "BRAM_L.BRAM_ADDRARDADDRL5->>BRAM_FIFO18_ADDRARDADDR4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL5" }, "BRAM_L.BRAM_ADDRARDADDRL5->>BRAM_FIFO36_ADDRARDADDRL5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL5" }, "BRAM_L.BRAM_ADDRARDADDRL5->>BRAM_UTURN_ADDRARDADDRL5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL5" }, "BRAM_L.BRAM_ADDRARDADDRL6->>BRAM_FIFO18_ADDRARDADDR5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL6" }, "BRAM_L.BRAM_ADDRARDADDRL6->>BRAM_FIFO36_ADDRARDADDRL6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL6" }, "BRAM_L.BRAM_ADDRARDADDRL6->>BRAM_UTURN_ADDRARDADDRL6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL6" }, "BRAM_L.BRAM_ADDRARDADDRL7->>BRAM_FIFO18_ADDRARDADDR6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL7" }, "BRAM_L.BRAM_ADDRARDADDRL7->>BRAM_FIFO36_ADDRARDADDRL7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL7" }, "BRAM_L.BRAM_ADDRARDADDRL7->>BRAM_UTURN_ADDRARDADDRL7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL7" }, "BRAM_L.BRAM_ADDRARDADDRL8->>BRAM_FIFO18_ADDRARDADDR7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL8" }, "BRAM_L.BRAM_ADDRARDADDRL8->>BRAM_FIFO36_ADDRARDADDRL8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL8" }, "BRAM_L.BRAM_ADDRARDADDRL8->>BRAM_UTURN_ADDRARDADDRL8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL8" }, "BRAM_L.BRAM_ADDRARDADDRL9->>BRAM_FIFO18_ADDRARDADDR8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL9" }, "BRAM_L.BRAM_ADDRARDADDRL9->>BRAM_FIFO36_ADDRARDADDRL9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL9" }, "BRAM_L.BRAM_ADDRARDADDRL9->>BRAM_UTURN_ADDRARDADDRL9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL9" }, "BRAM_L.BRAM_ADDRARDADDRL10->>BRAM_FIFO18_ADDRARDADDR9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL10" }, "BRAM_L.BRAM_ADDRARDADDRL10->>BRAM_FIFO36_ADDRARDADDRL10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL10" }, "BRAM_L.BRAM_ADDRARDADDRL10->>BRAM_UTURN_ADDRARDADDRL10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL10" }, "BRAM_L.BRAM_ADDRARDADDRL11->>BRAM_FIFO18_ADDRARDADDR10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL11" }, "BRAM_L.BRAM_ADDRARDADDRL11->>BRAM_FIFO36_ADDRARDADDRL11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL11" }, "BRAM_L.BRAM_ADDRARDADDRL11->>BRAM_UTURN_ADDRARDADDRL11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL11" }, "BRAM_L.BRAM_ADDRARDADDRL12->>BRAM_FIFO18_ADDRARDADDR11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL12" }, "BRAM_L.BRAM_ADDRARDADDRL12->>BRAM_FIFO36_ADDRARDADDRL12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL12" }, "BRAM_L.BRAM_ADDRARDADDRL12->>BRAM_UTURN_ADDRARDADDRL12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL12" }, "BRAM_L.BRAM_ADDRARDADDRL13->>BRAM_FIFO18_ADDRARDADDR12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL13" }, "BRAM_L.BRAM_ADDRARDADDRL13->>BRAM_FIFO36_ADDRARDADDRL13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL13" }, "BRAM_L.BRAM_ADDRARDADDRL13->>BRAM_UTURN_ADDRARDADDRL13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL13" }, "BRAM_L.BRAM_ADDRARDADDRL14->>BRAM_FIFO18_ADDRARDADDR13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL14" }, "BRAM_L.BRAM_ADDRARDADDRL14->>BRAM_FIFO36_ADDRARDADDRL14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRL14" }, "BRAM_L.BRAM_ADDRARDADDRL14->>BRAM_UTURN_ADDRARDADDRL14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRL14" }, "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_CASCOUT_ADDRARDADDRU0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU0" }, "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_FIFO36_ADDRARDADDRU0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU0" }, "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_RAMB18_ADDRATIEHIGH0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU0" }, "BRAM_L.BRAM_ADDRARDADDRU0->>BRAM_UTURN_ADDRARDADDRU0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU0" }, "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_CASCOUT_ADDRARDADDRU1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU1" }, "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_FIFO36_ADDRARDADDRU1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU1" }, "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_RAMB18_ADDRARDADDR0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU1" }, "BRAM_L.BRAM_ADDRARDADDRU1->>BRAM_UTURN_ADDRARDADDRU1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU1" }, "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_CASCOUT_ADDRARDADDRU2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU2" }, "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_FIFO36_ADDRARDADDRU2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU2" }, "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_RAMB18_ADDRARDADDR1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU2" }, "BRAM_L.BRAM_ADDRARDADDRU2->>BRAM_UTURN_ADDRARDADDRU2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU2" }, "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_CASCOUT_ADDRARDADDRU3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU3" }, "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_FIFO36_ADDRARDADDRU3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU3" }, "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_RAMB18_ADDRARDADDR2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU3" }, "BRAM_L.BRAM_ADDRARDADDRU3->>BRAM_UTURN_ADDRARDADDRU3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU3" }, "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_CASCOUT_ADDRARDADDRU4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU4" }, "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_FIFO36_ADDRARDADDRU4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU4" }, "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_RAMB18_ADDRARDADDR3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU4" }, "BRAM_L.BRAM_ADDRARDADDRU4->>BRAM_UTURN_ADDRARDADDRU4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU4" }, "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_CASCOUT_ADDRARDADDRU5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU5" }, "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_FIFO36_ADDRARDADDRU5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU5" }, "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_RAMB18_ADDRARDADDR4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU5" }, "BRAM_L.BRAM_ADDRARDADDRU5->>BRAM_UTURN_ADDRARDADDRU5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU5" }, "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_CASCOUT_ADDRARDADDRU6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU6" }, "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_FIFO36_ADDRARDADDRU6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU6" }, "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_RAMB18_ADDRARDADDR5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU6" }, "BRAM_L.BRAM_ADDRARDADDRU6->>BRAM_UTURN_ADDRARDADDRU6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU6" }, "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_CASCOUT_ADDRARDADDRU7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU7" }, "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_FIFO36_ADDRARDADDRU7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU7" }, "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_RAMB18_ADDRARDADDR6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU7" }, "BRAM_L.BRAM_ADDRARDADDRU7->>BRAM_UTURN_ADDRARDADDRU7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU7" }, "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_CASCOUT_ADDRARDADDRU8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU8" }, "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_FIFO36_ADDRARDADDRU8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU8" }, "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_RAMB18_ADDRARDADDR7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU8" }, "BRAM_L.BRAM_ADDRARDADDRU8->>BRAM_UTURN_ADDRARDADDRU8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU8" }, "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_CASCOUT_ADDRARDADDRU9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU9" }, "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_FIFO36_ADDRARDADDRU9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU9" }, "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_RAMB18_ADDRARDADDR8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU9" }, "BRAM_L.BRAM_ADDRARDADDRU9->>BRAM_UTURN_ADDRARDADDRU9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU9" }, "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_CASCOUT_ADDRARDADDRU10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU10" }, "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_FIFO36_ADDRARDADDRU10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU10" }, "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_RAMB18_ADDRARDADDR9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU10" }, "BRAM_L.BRAM_ADDRARDADDRU10->>BRAM_UTURN_ADDRARDADDRU10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU10" }, "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_CASCOUT_ADDRARDADDRU11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU11" }, "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_FIFO36_ADDRARDADDRU11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU11" }, "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_RAMB18_ADDRARDADDR10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU11" }, "BRAM_L.BRAM_ADDRARDADDRU11->>BRAM_UTURN_ADDRARDADDRU11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU11" }, "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_CASCOUT_ADDRARDADDRU12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU12" }, "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_FIFO36_ADDRARDADDRU12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU12" }, "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_RAMB18_ADDRARDADDR11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU12" }, "BRAM_L.BRAM_ADDRARDADDRU12->>BRAM_UTURN_ADDRARDADDRU12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU12" }, "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_CASCOUT_ADDRARDADDRU13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU13" }, "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_FIFO36_ADDRARDADDRU13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU13" }, "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_RAMB18_ADDRARDADDR12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU13" }, "BRAM_L.BRAM_ADDRARDADDRU13->>BRAM_UTURN_ADDRARDADDRU13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU13" }, "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_CASCOUT_ADDRARDADDRU14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRARDADDRU14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU14" }, "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_FIFO36_ADDRARDADDRU14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRU14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU14" }, "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_RAMB18_ADDRARDADDR13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRARDADDR13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRARDADDRU14" }, "BRAM_L.BRAM_ADDRARDADDRU14->>BRAM_UTURN_ADDRARDADDRU14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRU14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRARDADDRU14" }, "BRAM_L.BRAM_ADDRBWRADDRL0->>BRAM_FIFO18_ADDRBTIEHIGH0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL0" }, "BRAM_L.BRAM_ADDRBWRADDRL0->>BRAM_FIFO36_ADDRBWRADDRL0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL0" }, "BRAM_L.BRAM_ADDRBWRADDRL0->>BRAM_UTURN_ADDRBWRADDRL0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL0" }, "BRAM_L.BRAM_ADDRBWRADDRL1->>BRAM_FIFO18_ADDRBWRADDR0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL1" }, "BRAM_L.BRAM_ADDRBWRADDRL1->>BRAM_FIFO36_ADDRBWRADDRL1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL1" }, "BRAM_L.BRAM_ADDRBWRADDRL1->>BRAM_UTURN_ADDRBWRADDRL1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL1" }, "BRAM_L.BRAM_ADDRBWRADDRL2->>BRAM_FIFO18_ADDRBWRADDR1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL2" }, "BRAM_L.BRAM_ADDRBWRADDRL2->>BRAM_FIFO36_ADDRBWRADDRL2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL2" }, "BRAM_L.BRAM_ADDRBWRADDRL2->>BRAM_UTURN_ADDRBWRADDRL2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL2" }, "BRAM_L.BRAM_ADDRBWRADDRL3->>BRAM_FIFO18_ADDRBWRADDR2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL3" }, "BRAM_L.BRAM_ADDRBWRADDRL3->>BRAM_FIFO36_ADDRBWRADDRL3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL3" }, "BRAM_L.BRAM_ADDRBWRADDRL3->>BRAM_UTURN_ADDRBWRADDRL3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL3" }, "BRAM_L.BRAM_ADDRBWRADDRL4->>BRAM_FIFO18_ADDRBWRADDR3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL4" }, "BRAM_L.BRAM_ADDRBWRADDRL4->>BRAM_FIFO36_ADDRBWRADDRL4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL4" }, "BRAM_L.BRAM_ADDRBWRADDRL4->>BRAM_UTURN_ADDRBWRADDRL4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL4" }, "BRAM_L.BRAM_ADDRBWRADDRL5->>BRAM_FIFO18_ADDRBWRADDR4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL5" }, "BRAM_L.BRAM_ADDRBWRADDRL5->>BRAM_FIFO36_ADDRBWRADDRL5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL5" }, "BRAM_L.BRAM_ADDRBWRADDRL5->>BRAM_UTURN_ADDRBWRADDRL5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL5" }, "BRAM_L.BRAM_ADDRBWRADDRL6->>BRAM_FIFO18_ADDRBWRADDR5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL6" }, "BRAM_L.BRAM_ADDRBWRADDRL6->>BRAM_FIFO36_ADDRBWRADDRL6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL6" }, "BRAM_L.BRAM_ADDRBWRADDRL6->>BRAM_UTURN_ADDRBWRADDRL6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL6" }, "BRAM_L.BRAM_ADDRBWRADDRL7->>BRAM_FIFO18_ADDRBWRADDR6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL7" }, "BRAM_L.BRAM_ADDRBWRADDRL7->>BRAM_FIFO36_ADDRBWRADDRL7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL7" }, "BRAM_L.BRAM_ADDRBWRADDRL7->>BRAM_UTURN_ADDRBWRADDRL7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL7" }, "BRAM_L.BRAM_ADDRBWRADDRL8->>BRAM_FIFO18_ADDRBWRADDR7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL8" }, "BRAM_L.BRAM_ADDRBWRADDRL8->>BRAM_FIFO36_ADDRBWRADDRL8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL8" }, "BRAM_L.BRAM_ADDRBWRADDRL8->>BRAM_UTURN_ADDRBWRADDRL8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL8" }, "BRAM_L.BRAM_ADDRBWRADDRL9->>BRAM_FIFO18_ADDRBWRADDR8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL9" }, "BRAM_L.BRAM_ADDRBWRADDRL9->>BRAM_FIFO36_ADDRBWRADDRL9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL9" }, "BRAM_L.BRAM_ADDRBWRADDRL9->>BRAM_UTURN_ADDRBWRADDRL9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL9" }, "BRAM_L.BRAM_ADDRBWRADDRL10->>BRAM_FIFO18_ADDRBWRADDR9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL10" }, "BRAM_L.BRAM_ADDRBWRADDRL10->>BRAM_FIFO36_ADDRBWRADDRL10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL10" }, "BRAM_L.BRAM_ADDRBWRADDRL10->>BRAM_UTURN_ADDRBWRADDRL10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL10" }, "BRAM_L.BRAM_ADDRBWRADDRL11->>BRAM_FIFO18_ADDRBWRADDR10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL11" }, "BRAM_L.BRAM_ADDRBWRADDRL11->>BRAM_FIFO36_ADDRBWRADDRL11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL11" }, "BRAM_L.BRAM_ADDRBWRADDRL11->>BRAM_UTURN_ADDRBWRADDRL11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL11" }, "BRAM_L.BRAM_ADDRBWRADDRL12->>BRAM_FIFO18_ADDRBWRADDR11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL12" }, "BRAM_L.BRAM_ADDRBWRADDRL12->>BRAM_FIFO36_ADDRBWRADDRL12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL12" }, "BRAM_L.BRAM_ADDRBWRADDRL12->>BRAM_UTURN_ADDRBWRADDRL12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL12" }, "BRAM_L.BRAM_ADDRBWRADDRL13->>BRAM_FIFO18_ADDRBWRADDR12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL13" }, "BRAM_L.BRAM_ADDRBWRADDRL13->>BRAM_FIFO36_ADDRBWRADDRL13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL13" }, "BRAM_L.BRAM_ADDRBWRADDRL13->>BRAM_UTURN_ADDRBWRADDRL13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL13" }, "BRAM_L.BRAM_ADDRBWRADDRL14->>BRAM_FIFO18_ADDRBWRADDR13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBWRADDR13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL14" }, "BRAM_L.BRAM_ADDRBWRADDRL14->>BRAM_FIFO36_ADDRBWRADDRL14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRL14" }, "BRAM_L.BRAM_ADDRBWRADDRL14->>BRAM_UTURN_ADDRBWRADDRL14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRL14" }, "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_CASCOUT_ADDRBWRADDRU0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU0" }, "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_FIFO36_ADDRBWRADDRU0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU0" }, "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_RAMB18_ADDRBTIEHIGH0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU0" }, "BRAM_L.BRAM_ADDRBWRADDRU0->>BRAM_UTURN_ADDRBWRADDRU0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU0" }, "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_CASCOUT_ADDRBWRADDRU1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU1" }, "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_FIFO36_ADDRBWRADDRU1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU1" }, "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_RAMB18_ADDRBWRADDR0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU1" }, "BRAM_L.BRAM_ADDRBWRADDRU1->>BRAM_UTURN_ADDRBWRADDRU1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU1" }, "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_CASCOUT_ADDRBWRADDRU2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU2" }, "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_FIFO36_ADDRBWRADDRU2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU2" }, "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_RAMB18_ADDRBWRADDR1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU2" }, "BRAM_L.BRAM_ADDRBWRADDRU2->>BRAM_UTURN_ADDRBWRADDRU2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU2" }, "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_CASCOUT_ADDRBWRADDRU3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU3" }, "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_FIFO36_ADDRBWRADDRU3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU3" }, "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_RAMB18_ADDRBWRADDR2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU3" }, "BRAM_L.BRAM_ADDRBWRADDRU3->>BRAM_UTURN_ADDRBWRADDRU3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU3" }, "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_CASCOUT_ADDRBWRADDRU4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU4" }, "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_FIFO36_ADDRBWRADDRU4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU4" }, "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_RAMB18_ADDRBWRADDR3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU4" }, "BRAM_L.BRAM_ADDRBWRADDRU4->>BRAM_UTURN_ADDRBWRADDRU4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU4" }, "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_CASCOUT_ADDRBWRADDRU5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU5" }, "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_FIFO36_ADDRBWRADDRU5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU5" }, "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_RAMB18_ADDRBWRADDR4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU5" }, "BRAM_L.BRAM_ADDRBWRADDRU5->>BRAM_UTURN_ADDRBWRADDRU5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU5" }, "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_CASCOUT_ADDRBWRADDRU6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU6" }, "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_FIFO36_ADDRBWRADDRU6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU6" }, "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_RAMB18_ADDRBWRADDR5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU6" }, "BRAM_L.BRAM_ADDRBWRADDRU6->>BRAM_UTURN_ADDRBWRADDRU6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU6" }, "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_CASCOUT_ADDRBWRADDRU7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU7" }, "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_FIFO36_ADDRBWRADDRU7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU7" }, "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_RAMB18_ADDRBWRADDR6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU7" }, "BRAM_L.BRAM_ADDRBWRADDRU7->>BRAM_UTURN_ADDRBWRADDRU7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU7" }, "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_CASCOUT_ADDRBWRADDRU8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU8" }, "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_FIFO36_ADDRBWRADDRU8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU8" }, "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_RAMB18_ADDRBWRADDR7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU8" }, "BRAM_L.BRAM_ADDRBWRADDRU8->>BRAM_UTURN_ADDRBWRADDRU8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU8" }, "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_CASCOUT_ADDRBWRADDRU9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU9" }, "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_FIFO36_ADDRBWRADDRU9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU9" }, "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_RAMB18_ADDRBWRADDR8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU9" }, "BRAM_L.BRAM_ADDRBWRADDRU9->>BRAM_UTURN_ADDRBWRADDRU9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU9" }, "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_CASCOUT_ADDRBWRADDRU10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU10" }, "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_FIFO36_ADDRBWRADDRU10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU10" }, "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_RAMB18_ADDRBWRADDR9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU10" }, "BRAM_L.BRAM_ADDRBWRADDRU10->>BRAM_UTURN_ADDRBWRADDRU10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU10" }, "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_CASCOUT_ADDRBWRADDRU11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU11" }, "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_FIFO36_ADDRBWRADDRU11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU11" }, "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_RAMB18_ADDRBWRADDR10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU11" }, "BRAM_L.BRAM_ADDRBWRADDRU11->>BRAM_UTURN_ADDRBWRADDRU11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU11" }, "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_CASCOUT_ADDRBWRADDRU12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU12" }, "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_FIFO36_ADDRBWRADDRU12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU12" }, "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_RAMB18_ADDRBWRADDR11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU12" }, "BRAM_L.BRAM_ADDRBWRADDRU12->>BRAM_UTURN_ADDRBWRADDRU12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU12" }, "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_CASCOUT_ADDRBWRADDRU13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU13" }, "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_FIFO36_ADDRBWRADDRU13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU13" }, "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_RAMB18_ADDRBWRADDR12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU13" }, "BRAM_L.BRAM_ADDRBWRADDRU13->>BRAM_UTURN_ADDRBWRADDRU13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU13" }, "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_CASCOUT_ADDRBWRADDRU14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.106", "0.129", "0.280", "0.338" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU14" }, "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_FIFO36_ADDRBWRADDRU14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU14" }, "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_RAMB18_ADDRBWRADDR13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_ADDRBWRADDRU14" }, "BRAM_L.BRAM_ADDRBWRADDRU14->>BRAM_UTURN_ADDRBWRADDRU14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_ADDRBWRADDRU14" }, "BRAM_L.BRAM_BYP3_2->BRAM_FIFO18_WEBWE3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_WEBWE3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_BYP3_2" }, "BRAM_L.BRAM_BYP3_2->BRAM_FIFO36_WEBWEL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_BYP3_2" }, "BRAM_L.BRAM_BYP6_2->BRAM_FIFO18_WEBWE7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_WEBWE7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_BYP6_2" }, "BRAM_L.BRAM_BYP6_2->BRAM_FIFO36_WEBWEL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_BYP6_2" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14" }, "BRAM_L.BRAM_CLK0_0->BRAM_FIFO18_REGCLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_REGCLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK0_0" }, "BRAM_L.BRAM_CLK0_0->BRAM_FIFO36_REGCLKBL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_REGCLKBL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK0_0" }, "BRAM_L.BRAM_CLK0_1->BRAM_FIFO18_CLKBWRCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_CLKBWRCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK0_1" }, "BRAM_L.BRAM_CLK0_1->BRAM_FIFO36_CLKBWRCLKL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_CLKBWRCLKL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK0_1" }, "BRAM_L.BRAM_CLK0_3->BRAM_FIFO18_CLKARDCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_CLKARDCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK0_3" }, "BRAM_L.BRAM_CLK0_3->BRAM_FIFO36_CLKARDCLKL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_CLKARDCLKL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK0_3" }, "BRAM_L.BRAM_CLK0_4->BRAM_FIFO18_REGCLKARDRCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_REGCLKARDRCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK0_4" }, "BRAM_L.BRAM_CLK0_4->BRAM_FIFO36_REGCLKARDRCLKL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK0_4" }, "BRAM_L.BRAM_CLK1_0->BRAM_FIFO36_REGCLKBU": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_REGCLKBU", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK1_0" }, "BRAM_L.BRAM_CLK1_0->BRAM_RAMB18_REGCLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_REGCLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK1_0" }, "BRAM_L.BRAM_CLK1_1->BRAM_FIFO36_CLKBWRCLKU": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_CLKBWRCLKU", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK1_1" }, "BRAM_L.BRAM_CLK1_1->BRAM_RAMB18_CLKBWRCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_CLKBWRCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK1_1" }, "BRAM_L.BRAM_CLK1_3->BRAM_FIFO36_CLKARDCLKU": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_CLKARDCLKU", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK1_3" }, "BRAM_L.BRAM_CLK1_3->BRAM_RAMB18_CLKARDCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_CLKARDCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK1_3" }, "BRAM_L.BRAM_CLK1_4->BRAM_FIFO36_REGCLKARDRCLKU": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKU", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK1_4" }, "BRAM_L.BRAM_CLK1_4->BRAM_RAMB18_REGCLKARDRCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_REGCLKARDRCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CLK1_4" }, "BRAM_L.BRAM_CTRL0_0->BRAM_FIFO18_RSTREGB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_RSTREGB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL0_0" }, "BRAM_L.BRAM_CTRL0_0->BRAM_FIFO36_RSTREGBL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_RSTREGBL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL0_0" }, "BRAM_L.BRAM_CTRL0_1->BRAM_FIFO18_RSTRAMB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_RSTRAMB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL0_1" }, "BRAM_L.BRAM_CTRL0_1->BRAM_FIFO36_RSTRAMBL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_RSTRAMBL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL0_1" }, "BRAM_L.BRAM_CTRL0_3->BRAM_FIFO18_RSTRAMARSTRAM": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_RSTRAMARSTRAM", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL0_3" }, "BRAM_L.BRAM_CTRL0_3->BRAM_FIFO36_RSTRAMARSTRAMLRST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMLRST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL0_3" }, "BRAM_L.BRAM_CTRL0_4->BRAM_FIFO18_RSTREGARSTREG": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_RSTREGARSTREG", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL0_4" }, "BRAM_L.BRAM_CTRL0_4->BRAM_FIFO36_RSTREGARSTREGL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_RSTREGARSTREGL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL0_4" }, "BRAM_L.BRAM_CTRL1_0->BRAM_FIFO36_RSTREGBU": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_RSTREGBU", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL1_0" }, "BRAM_L.BRAM_CTRL1_0->BRAM_RAMB18_RSTREGB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_RSTREGB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL1_0" }, "BRAM_L.BRAM_CTRL1_1->BRAM_FIFO36_RSTRAMBU": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_RSTRAMBU", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL1_1" }, "BRAM_L.BRAM_CTRL1_1->BRAM_RAMB18_RSTRAMB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_RSTRAMB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL1_1" }, "BRAM_L.BRAM_CTRL1_3->BRAM_FIFO36_RSTRAMARSTRAMU": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMU", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL1_3" }, "BRAM_L.BRAM_CTRL1_3->BRAM_RAMB18_RSTRAMARSTRAM": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_RSTRAMARSTRAM", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL1_3" }, "BRAM_L.BRAM_CTRL1_4->BRAM_FIFO36_RSTREGARSTREGU": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_RSTREGARSTREGU", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL1_4" }, "BRAM_L.BRAM_CTRL1_4->BRAM_RAMB18_RSTREGARSTREG": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_RSTREGARSTREG", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_CTRL1_4" }, "BRAM_L.BRAM_FAN1_2->BRAM_FIFO36_WEBWEU4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEU4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FAN1_2" }, "BRAM_L.BRAM_FAN1_2->BRAM_RAMB18_WEBWE4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_WEBWE4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FAN1_2" }, "BRAM_L.BRAM_FAN5_2->BRAM_FIFO36_WEBWEU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FAN5_2" }, "BRAM_L.BRAM_FAN5_2->BRAM_RAMB18_WEBWE0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_WEBWE0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FAN5_2" }, "BRAM_L.BRAM_FIFO18_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B2_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_ALMOSTEMPTY" }, "BRAM_L.BRAM_FIFO18_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B1_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_ALMOSTFULL" }, "BRAM_L.BRAM_FIFO18_DOADO0->BRAM_LOGIC_OUTS_B8_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B8_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO0" }, "BRAM_L.BRAM_FIFO18_DOADO1->BRAM_LOGIC_OUTS_B13_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B13_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO1" }, "BRAM_L.BRAM_FIFO18_DOADO2->BRAM_LOGIC_OUTS_B10_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B10_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO2" }, "BRAM_L.BRAM_FIFO18_DOADO3->BRAM_LOGIC_OUTS_B15_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B15_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO3" }, "BRAM_L.BRAM_FIFO18_DOADO4->BRAM_LOGIC_OUTS_B13_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B13_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO4" }, "BRAM_L.BRAM_FIFO18_DOADO5->BRAM_LOGIC_OUTS_B10_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B10_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO5" }, "BRAM_L.BRAM_FIFO18_DOADO6->BRAM_LOGIC_OUTS_B15_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B15_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO6" }, "BRAM_L.BRAM_FIFO18_DOADO7->BRAM_LOGIC_OUTS_B8_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B8_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO7" }, "BRAM_L.BRAM_FIFO18_DOADO8->BRAM_LOGIC_OUTS_B0_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B0_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO8" }, "BRAM_L.BRAM_FIFO18_DOADO9->BRAM_LOGIC_OUTS_B5_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B5_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO9" }, "BRAM_L.BRAM_FIFO18_DOADO10->BRAM_LOGIC_OUTS_B2_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B2_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO10" }, "BRAM_L.BRAM_FIFO18_DOADO11->BRAM_LOGIC_OUTS_B7_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B7_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO11" }, "BRAM_L.BRAM_FIFO18_DOADO12->BRAM_LOGIC_OUTS_B5_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B5_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO12" }, "BRAM_L.BRAM_FIFO18_DOADO13->BRAM_LOGIC_OUTS_B2_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B2_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO13" }, "BRAM_L.BRAM_FIFO18_DOADO14->BRAM_LOGIC_OUTS_B7_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B7_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO14" }, "BRAM_L.BRAM_FIFO18_DOADO15->BRAM_LOGIC_OUTS_B0_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B0_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOADO15" }, "BRAM_L.BRAM_FIFO18_DOBDO0->BRAM_LOGIC_OUTS_B4_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B4_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO0" }, "BRAM_L.BRAM_FIFO18_DOBDO1->BRAM_LOGIC_OUTS_B1_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B1_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO1" }, "BRAM_L.BRAM_FIFO18_DOBDO2->BRAM_LOGIC_OUTS_B6_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B6_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO2" }, "BRAM_L.BRAM_FIFO18_DOBDO3->BRAM_LOGIC_OUTS_B3_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B3_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO3" }, "BRAM_L.BRAM_FIFO18_DOBDO4->BRAM_LOGIC_OUTS_B1_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B1_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO4" }, "BRAM_L.BRAM_FIFO18_DOBDO5->BRAM_LOGIC_OUTS_B6_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B6_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO5" }, "BRAM_L.BRAM_FIFO18_DOBDO6->BRAM_LOGIC_OUTS_B3_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B3_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO6" }, "BRAM_L.BRAM_FIFO18_DOBDO7->BRAM_LOGIC_OUTS_B4_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B4_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO7" }, "BRAM_L.BRAM_FIFO18_DOBDO8->BRAM_LOGIC_OUTS_B22_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B22_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO8" }, "BRAM_L.BRAM_FIFO18_DOBDO9->BRAM_LOGIC_OUTS_B19_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B19_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO9" }, "BRAM_L.BRAM_FIFO18_DOBDO10->BRAM_LOGIC_OUTS_B20_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B20_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO10" }, "BRAM_L.BRAM_FIFO18_DOBDO11->BRAM_LOGIC_OUTS_B17_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B17_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO11" }, "BRAM_L.BRAM_FIFO18_DOBDO12->BRAM_LOGIC_OUTS_B19_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B19_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO12" }, "BRAM_L.BRAM_FIFO18_DOBDO13->BRAM_LOGIC_OUTS_B20_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B20_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO13" }, "BRAM_L.BRAM_FIFO18_DOBDO14->BRAM_LOGIC_OUTS_B17_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B17_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO14" }, "BRAM_L.BRAM_FIFO18_DOBDO15->BRAM_LOGIC_OUTS_B22_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B22_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOBDO15" }, "BRAM_L.BRAM_FIFO18_DOPADOP0->BRAM_LOGIC_OUTS_B8_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B8_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOPADOP0" }, "BRAM_L.BRAM_FIFO18_DOPADOP1->BRAM_LOGIC_OUTS_B0_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B0_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOPADOP1" }, "BRAM_L.BRAM_FIFO18_DOPBDOP0->BRAM_LOGIC_OUTS_B4_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B4_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOPBDOP0" }, "BRAM_L.BRAM_FIFO18_DOPBDOP1->BRAM_LOGIC_OUTS_B22_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B22_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_DOPBDOP1" }, "BRAM_L.BRAM_FIFO18_EMPTY->BRAM_LOGIC_OUTS_B6_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B6_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_EMPTY" }, "BRAM_L.BRAM_FIFO18_FULL->BRAM_LOGIC_OUTS_B5_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B5_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_FULL" }, "BRAM_L.BRAM_FIFO18_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B12_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDCOUNT0" }, "BRAM_L.BRAM_FIFO18_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B23_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDCOUNT1" }, "BRAM_L.BRAM_FIFO18_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B9_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDCOUNT2" }, "BRAM_L.BRAM_FIFO18_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B12_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDCOUNT3" }, "BRAM_L.BRAM_FIFO18_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B23_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDCOUNT4" }, "BRAM_L.BRAM_FIFO18_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B9_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDCOUNT5" }, "BRAM_L.BRAM_FIFO18_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B16_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDCOUNT6" }, "BRAM_L.BRAM_FIFO18_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B14_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDCOUNT7" }, "BRAM_L.BRAM_FIFO18_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B21_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDCOUNT8" }, "BRAM_L.BRAM_FIFO18_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B11_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDCOUNT9" }, "BRAM_L.BRAM_FIFO18_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B16_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDCOUNT10" }, "BRAM_L.BRAM_FIFO18_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B14_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDCOUNT11" }, "BRAM_L.BRAM_FIFO18_RDERR->BRAM_LOGIC_OUTS_B14_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B14_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_RDERR" }, "BRAM_L.BRAM_FIFO18_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B16_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRCOUNT0" }, "BRAM_L.BRAM_FIFO18_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B14_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRCOUNT1" }, "BRAM_L.BRAM_FIFO18_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B21_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRCOUNT2" }, "BRAM_L.BRAM_FIFO18_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B16_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRCOUNT3" }, "BRAM_L.BRAM_FIFO18_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B14_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRCOUNT4" }, "BRAM_L.BRAM_FIFO18_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B21_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRCOUNT5" }, "BRAM_L.BRAM_FIFO18_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B18_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRCOUNT6" }, "BRAM_L.BRAM_FIFO18_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B12_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRCOUNT7" }, "BRAM_L.BRAM_FIFO18_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B23_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRCOUNT8" }, "BRAM_L.BRAM_FIFO18_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B9_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRCOUNT9" }, "BRAM_L.BRAM_FIFO18_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B18_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRCOUNT10" }, "BRAM_L.BRAM_FIFO18_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B12_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRCOUNT11" }, "BRAM_L.BRAM_FIFO18_WRERR->BRAM_LOGIC_OUTS_B23_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B23_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO18_WRERR" }, "BRAM_L.BRAM_FIFO36_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B2_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_ALMOSTEMPTY" }, "BRAM_L.BRAM_FIFO36_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B1_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_ALMOSTFULL" }, "BRAM_L.BRAM_FIFO36_CASCADEOUTA->BRAM_FIFO36_CASCADEOUTA_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_CASCADEOUTA_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_CASCADEOUTA" }, "BRAM_L.BRAM_FIFO36_CASCADEOUTB->BRAM_FIFO36_CASCADEOUTB_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_CASCADEOUTB_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_CASCADEOUTB" }, "BRAM_L.BRAM_FIFO36_DBITERR->BRAM_LOGIC_OUTS_B16_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B16_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DBITERR" }, "BRAM_L.BRAM_FIFO36_DOADOL0->BRAM_LOGIC_OUTS_B8_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B8_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL0" }, "BRAM_L.BRAM_FIFO36_DOADOL1->BRAM_LOGIC_OUTS_B13_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B13_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL1" }, "BRAM_L.BRAM_FIFO36_DOADOL2->BRAM_LOGIC_OUTS_B10_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B10_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL2" }, "BRAM_L.BRAM_FIFO36_DOADOL3->BRAM_LOGIC_OUTS_B15_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B15_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL3" }, "BRAM_L.BRAM_FIFO36_DOADOL4->BRAM_LOGIC_OUTS_B13_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B13_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL4" }, "BRAM_L.BRAM_FIFO36_DOADOL5->BRAM_LOGIC_OUTS_B10_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B10_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL5" }, "BRAM_L.BRAM_FIFO36_DOADOL6->BRAM_LOGIC_OUTS_B15_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B15_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL6" }, "BRAM_L.BRAM_FIFO36_DOADOL7->BRAM_LOGIC_OUTS_B8_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B8_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL7" }, "BRAM_L.BRAM_FIFO36_DOADOL8->BRAM_LOGIC_OUTS_B0_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B0_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL8" }, "BRAM_L.BRAM_FIFO36_DOADOL9->BRAM_LOGIC_OUTS_B5_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B5_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL9" }, "BRAM_L.BRAM_FIFO36_DOADOL10->BRAM_LOGIC_OUTS_B2_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B2_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL10" }, "BRAM_L.BRAM_FIFO36_DOADOL11->BRAM_LOGIC_OUTS_B7_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B7_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL11" }, "BRAM_L.BRAM_FIFO36_DOADOL12->BRAM_LOGIC_OUTS_B5_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B5_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL12" }, "BRAM_L.BRAM_FIFO36_DOADOL13->BRAM_LOGIC_OUTS_B2_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B2_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL13" }, "BRAM_L.BRAM_FIFO36_DOADOL14->BRAM_LOGIC_OUTS_B7_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B7_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL14" }, "BRAM_L.BRAM_FIFO36_DOADOL15->BRAM_LOGIC_OUTS_B0_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B0_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOL15" }, "BRAM_L.BRAM_FIFO36_DOADOU0->BRAM_LOGIC_OUTS_B15_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B15_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU0" }, "BRAM_L.BRAM_FIFO36_DOADOU1->BRAM_LOGIC_OUTS_B8_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B8_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU1" }, "BRAM_L.BRAM_FIFO36_DOADOU2->BRAM_LOGIC_OUTS_B13_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B13_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU2" }, "BRAM_L.BRAM_FIFO36_DOADOU3->BRAM_LOGIC_OUTS_B10_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B10_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU3" }, "BRAM_L.BRAM_FIFO36_DOADOU4->BRAM_LOGIC_OUTS_B8_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B8_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU4" }, "BRAM_L.BRAM_FIFO36_DOADOU5->BRAM_LOGIC_OUTS_B13_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B13_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU5" }, "BRAM_L.BRAM_FIFO36_DOADOU6->BRAM_LOGIC_OUTS_B10_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B10_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU6" }, "BRAM_L.BRAM_FIFO36_DOADOU7->BRAM_LOGIC_OUTS_B15_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B15_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU7" }, "BRAM_L.BRAM_FIFO36_DOADOU8->BRAM_LOGIC_OUTS_B7_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B7_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU8" }, "BRAM_L.BRAM_FIFO36_DOADOU9->BRAM_LOGIC_OUTS_B0_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B0_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU9" }, "BRAM_L.BRAM_FIFO36_DOADOU10->BRAM_LOGIC_OUTS_B5_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B5_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU10" }, "BRAM_L.BRAM_FIFO36_DOADOU11->BRAM_LOGIC_OUTS_B2_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B2_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU11" }, "BRAM_L.BRAM_FIFO36_DOADOU12->BRAM_LOGIC_OUTS_B0_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B0_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU12" }, "BRAM_L.BRAM_FIFO36_DOADOU13->BRAM_LOGIC_OUTS_B5_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B5_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU13" }, "BRAM_L.BRAM_FIFO36_DOADOU14->BRAM_LOGIC_OUTS_B2_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B2_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU14" }, "BRAM_L.BRAM_FIFO36_DOADOU15->BRAM_LOGIC_OUTS_B7_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B7_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOADOU15" }, "BRAM_L.BRAM_FIFO36_DOBDOL0->BRAM_LOGIC_OUTS_B4_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B4_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL0" }, "BRAM_L.BRAM_FIFO36_DOBDOL1->BRAM_LOGIC_OUTS_B1_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B1_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL1" }, "BRAM_L.BRAM_FIFO36_DOBDOL2->BRAM_LOGIC_OUTS_B6_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B6_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL2" }, "BRAM_L.BRAM_FIFO36_DOBDOL3->BRAM_LOGIC_OUTS_B3_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B3_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL3" }, "BRAM_L.BRAM_FIFO36_DOBDOL4->BRAM_LOGIC_OUTS_B1_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B1_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL4" }, "BRAM_L.BRAM_FIFO36_DOBDOL5->BRAM_LOGIC_OUTS_B6_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B6_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL5" }, "BRAM_L.BRAM_FIFO36_DOBDOL6->BRAM_LOGIC_OUTS_B3_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B3_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL6" }, "BRAM_L.BRAM_FIFO36_DOBDOL7->BRAM_LOGIC_OUTS_B4_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B4_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL7" }, "BRAM_L.BRAM_FIFO36_DOBDOL8->BRAM_LOGIC_OUTS_B22_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B22_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL8" }, "BRAM_L.BRAM_FIFO36_DOBDOL9->BRAM_LOGIC_OUTS_B19_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B19_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL9" }, "BRAM_L.BRAM_FIFO36_DOBDOL10->BRAM_LOGIC_OUTS_B20_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B20_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL10" }, "BRAM_L.BRAM_FIFO36_DOBDOL11->BRAM_LOGIC_OUTS_B17_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B17_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL11" }, "BRAM_L.BRAM_FIFO36_DOBDOL12->BRAM_LOGIC_OUTS_B19_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B19_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL12" }, "BRAM_L.BRAM_FIFO36_DOBDOL13->BRAM_LOGIC_OUTS_B20_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B20_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL13" }, "BRAM_L.BRAM_FIFO36_DOBDOL14->BRAM_LOGIC_OUTS_B17_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B17_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL14" }, "BRAM_L.BRAM_FIFO36_DOBDOL15->BRAM_LOGIC_OUTS_B22_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B22_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOL15" }, "BRAM_L.BRAM_FIFO36_DOBDOU0->BRAM_LOGIC_OUTS_B3_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B3_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU0" }, "BRAM_L.BRAM_FIFO36_DOBDOU1->BRAM_LOGIC_OUTS_B4_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B4_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU1" }, "BRAM_L.BRAM_FIFO36_DOBDOU2->BRAM_LOGIC_OUTS_B1_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B1_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU2" }, "BRAM_L.BRAM_FIFO36_DOBDOU3->BRAM_LOGIC_OUTS_B6_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B6_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU3" }, "BRAM_L.BRAM_FIFO36_DOBDOU4->BRAM_LOGIC_OUTS_B4_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B4_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU4" }, "BRAM_L.BRAM_FIFO36_DOBDOU5->BRAM_LOGIC_OUTS_B1_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B1_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU5" }, "BRAM_L.BRAM_FIFO36_DOBDOU6->BRAM_LOGIC_OUTS_B6_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B6_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU6" }, "BRAM_L.BRAM_FIFO36_DOBDOU7->BRAM_LOGIC_OUTS_B3_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B3_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU7" }, "BRAM_L.BRAM_FIFO36_DOBDOU8->BRAM_LOGIC_OUTS_B17_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B17_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU8" }, "BRAM_L.BRAM_FIFO36_DOBDOU9->BRAM_LOGIC_OUTS_B22_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B22_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU9" }, "BRAM_L.BRAM_FIFO36_DOBDOU10->BRAM_LOGIC_OUTS_B19_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B19_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU10" }, "BRAM_L.BRAM_FIFO36_DOBDOU11->BRAM_LOGIC_OUTS_B20_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B20_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU11" }, "BRAM_L.BRAM_FIFO36_DOBDOU12->BRAM_LOGIC_OUTS_B22_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B22_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU12" }, "BRAM_L.BRAM_FIFO36_DOBDOU13->BRAM_LOGIC_OUTS_B19_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B19_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU13" }, "BRAM_L.BRAM_FIFO36_DOBDOU14->BRAM_LOGIC_OUTS_B20_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B20_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU14" }, "BRAM_L.BRAM_FIFO36_DOBDOU15->BRAM_LOGIC_OUTS_B17_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B17_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOBDOU15" }, "BRAM_L.BRAM_FIFO36_DOPADOPL0->BRAM_LOGIC_OUTS_B8_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B8_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOPADOPL0" }, "BRAM_L.BRAM_FIFO36_DOPADOPL1->BRAM_LOGIC_OUTS_B0_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B0_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOPADOPL1" }, "BRAM_L.BRAM_FIFO36_DOPADOPU0->BRAM_LOGIC_OUTS_B15_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B15_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOPADOPU0" }, "BRAM_L.BRAM_FIFO36_DOPADOPU1->BRAM_LOGIC_OUTS_B7_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B7_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOPADOPU1" }, "BRAM_L.BRAM_FIFO36_DOPBDOPL0->BRAM_LOGIC_OUTS_B4_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B4_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOPBDOPL0" }, "BRAM_L.BRAM_FIFO36_DOPBDOPL1->BRAM_LOGIC_OUTS_B22_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B22_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOPBDOPL1" }, "BRAM_L.BRAM_FIFO36_DOPBDOPU0->BRAM_LOGIC_OUTS_B3_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B3_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOPBDOPU0" }, "BRAM_L.BRAM_FIFO36_DOPBDOPU1->BRAM_LOGIC_OUTS_B17_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B17_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_DOPBDOPU1" }, "BRAM_L.BRAM_FIFO36_ECCPARITY0->BRAM_LOGIC_OUTS_B18_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B18_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_ECCPARITY0" }, "BRAM_L.BRAM_FIFO36_ECCPARITY1->BRAM_LOGIC_OUTS_B12_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B12_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_ECCPARITY1" }, "BRAM_L.BRAM_FIFO36_ECCPARITY2->BRAM_LOGIC_OUTS_B13_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B13_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_ECCPARITY2" }, "BRAM_L.BRAM_FIFO36_ECCPARITY3->BRAM_LOGIC_OUTS_B19_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B19_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_ECCPARITY3" }, "BRAM_L.BRAM_FIFO36_ECCPARITY4->BRAM_LOGIC_OUTS_B10_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B10_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_ECCPARITY4" }, "BRAM_L.BRAM_FIFO36_ECCPARITY5->BRAM_LOGIC_OUTS_B20_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B20_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_ECCPARITY5" }, "BRAM_L.BRAM_FIFO36_ECCPARITY6->BRAM_LOGIC_OUTS_B21_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B21_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_ECCPARITY6" }, "BRAM_L.BRAM_FIFO36_ECCPARITY7->BRAM_LOGIC_OUTS_B11_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B11_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_ECCPARITY7" }, "BRAM_L.BRAM_FIFO36_EMPTY->BRAM_LOGIC_OUTS_B6_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B6_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_EMPTY" }, "BRAM_L.BRAM_FIFO36_FULL->BRAM_LOGIC_OUTS_B5_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B5_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_FULL" }, "BRAM_L.BRAM_FIFO36_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B12_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT0" }, "BRAM_L.BRAM_FIFO36_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B23_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT1" }, "BRAM_L.BRAM_FIFO36_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B9_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT2" }, "BRAM_L.BRAM_FIFO36_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B12_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT3" }, "BRAM_L.BRAM_FIFO36_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B23_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT4" }, "BRAM_L.BRAM_FIFO36_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B9_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT5" }, "BRAM_L.BRAM_FIFO36_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B16_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT6" }, "BRAM_L.BRAM_FIFO36_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B14_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT7" }, "BRAM_L.BRAM_FIFO36_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B21_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT8" }, "BRAM_L.BRAM_FIFO36_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B11_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT9" }, "BRAM_L.BRAM_FIFO36_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B16_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT10" }, "BRAM_L.BRAM_FIFO36_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B14_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT11" }, "BRAM_L.BRAM_FIFO36_RDCOUNT12->BRAM_LOGIC_OUTS_B21_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B21_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDCOUNT12" }, "BRAM_L.BRAM_FIFO36_RDERR->BRAM_LOGIC_OUTS_B14_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B14_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_RDERR" }, "BRAM_L.BRAM_FIFO36_SBITERR->BRAM_LOGIC_OUTS_B9_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B9_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_SBITERR" }, "BRAM_L.BRAM_FIFO36_TSTOUT0->BRAM_LOGIC_OUTS_B18_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B18_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_TSTOUT0" }, "BRAM_L.BRAM_FIFO36_TSTOUT1->BRAM_LOGIC_OUTS_B18_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B18_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_TSTOUT1" }, "BRAM_L.BRAM_FIFO36_TSTOUT2->BRAM_LOGIC_OUTS_B11_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B11_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_TSTOUT2" }, "BRAM_L.BRAM_FIFO36_TSTOUT3->BRAM_LOGIC_OUTS_B11_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B11_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_TSTOUT3" }, "BRAM_L.BRAM_FIFO36_TSTOUT4->BRAM_LOGIC_OUTS_B11_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B11_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_TSTOUT4" }, "BRAM_L.BRAM_FIFO36_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B16_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT0" }, "BRAM_L.BRAM_FIFO36_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B14_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT1" }, "BRAM_L.BRAM_FIFO36_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B21_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT2" }, "BRAM_L.BRAM_FIFO36_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B16_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT3" }, "BRAM_L.BRAM_FIFO36_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B14_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT4" }, "BRAM_L.BRAM_FIFO36_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B21_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT5" }, "BRAM_L.BRAM_FIFO36_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B18_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT6" }, "BRAM_L.BRAM_FIFO36_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B12_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT7" }, "BRAM_L.BRAM_FIFO36_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B23_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT8" }, "BRAM_L.BRAM_FIFO36_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B9_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT9" }, "BRAM_L.BRAM_FIFO36_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B18_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT10" }, "BRAM_L.BRAM_FIFO36_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B12_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT11" }, "BRAM_L.BRAM_FIFO36_WRCOUNT12->BRAM_LOGIC_OUTS_B23_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B23_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRCOUNT12" }, "BRAM_L.BRAM_FIFO36_WRERR->BRAM_LOGIC_OUTS_B23_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B23_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_FIFO36_WRERR" }, "BRAM_L.BRAM_IMUX0_0->BRAM_FIFO36_TSTBRAMRST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTBRAMRST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX0_0" }, "BRAM_L.BRAM_IMUX1_1->BRAM_FIFO18_DIPBDIP1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIPBDIP1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX1_1" }, "BRAM_L.BRAM_IMUX1_1->BRAM_FIFO36_DIPBDIPL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIPBDIPL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX1_1" }, "BRAM_L.BRAM_IMUX1_2->BRAM_FIFO18_DIBDI7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX1_2" }, "BRAM_L.BRAM_IMUX1_2->BRAM_FIFO36_DIBDIL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX1_2" }, "BRAM_L.BRAM_IMUX1_3->BRAM_FIFO36_DIBDIU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX1_3" }, "BRAM_L.BRAM_IMUX1_3->BRAM_RAMB18_DIBDI1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX1_3" }, "BRAM_L.BRAM_IMUX2_0->BRAM_FIFO36_TSTRDCNTOFF": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDCNTOFF", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX2_0" }, "BRAM_L.BRAM_IMUX2_1->BRAM_FIFO18_DIBDI4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX2_1" }, "BRAM_L.BRAM_IMUX2_1->BRAM_FIFO36_DIBDIL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX2_1" }, "BRAM_L.BRAM_IMUX2_2->BRAM_FIFO18_DIBDI15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX2_2" }, "BRAM_L.BRAM_IMUX2_2->BRAM_FIFO36_DIBDIL15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX2_2" }, "BRAM_L.BRAM_IMUX2_3->BRAM_FIFO36_DIBDIU9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX2_3" }, "BRAM_L.BRAM_IMUX2_3->BRAM_RAMB18_DIBDI9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX2_3" }, "BRAM_L.BRAM_IMUX3_0->BRAM_FIFO36_TSTWRCNTOFF": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWRCNTOFF", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX3_0" }, "BRAM_L.BRAM_IMUX3_1->BRAM_FIFO18_DIBDI12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX3_1" }, "BRAM_L.BRAM_IMUX3_1->BRAM_FIFO36_DIBDIL12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX3_1" }, "BRAM_L.BRAM_IMUX3_2->BRAM_FIFO18_DIPADIP0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIPADIP0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX3_2" }, "BRAM_L.BRAM_IMUX3_2->BRAM_FIFO36_DIPADIPL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIPADIPL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX3_2" }, "BRAM_L.BRAM_IMUX3_3->BRAM_FIFO36_DIBDIU2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX3_3" }, "BRAM_L.BRAM_IMUX3_3->BRAM_RAMB18_DIBDI2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX3_3" }, "BRAM_L.BRAM_IMUX4_0->BRAM_FIFO36_TSTOFF": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTOFF", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX4_0" }, "BRAM_L.BRAM_IMUX4_1->BRAM_FIFO18_DIBDI5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX4_1" }, "BRAM_L.BRAM_IMUX4_1->BRAM_FIFO36_DIBDIL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX4_1" }, "BRAM_L.BRAM_IMUX4_2->BRAM_FIFO18_DIPBDIP0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIPBDIP0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX4_2" }, "BRAM_L.BRAM_IMUX4_2->BRAM_FIFO36_DIPBDIPL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIPBDIPL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX4_2" }, "BRAM_L.BRAM_IMUX4_3->BRAM_FIFO36_DIBDIU10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX4_3" }, "BRAM_L.BRAM_IMUX4_3->BRAM_RAMB18_DIBDI10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX4_3" }, "BRAM_L.BRAM_IMUX4_4->BRAM_FIFO36_TSTIN2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTIN2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX4_4" }, "BRAM_L.BRAM_IMUX5_0->BRAM_FIFO36_TSTFLAGIN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTFLAGIN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX5_0" }, "BRAM_L.BRAM_IMUX5_1->BRAM_FIFO18_DIBDI13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX5_1" }, "BRAM_L.BRAM_IMUX5_1->BRAM_FIFO36_DIBDIL13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX5_1" }, "BRAM_L.BRAM_IMUX5_2->BRAM_FIFO18_WEBWE0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_WEBWE0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX5_2" }, "BRAM_L.BRAM_IMUX5_2->BRAM_FIFO36_WEBWEL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX5_2" }, "BRAM_L.BRAM_IMUX5_3->BRAM_FIFO36_DIBDIU3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX5_3" }, "BRAM_L.BRAM_IMUX5_3->BRAM_RAMB18_DIBDI3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX5_3" }, "BRAM_L.BRAM_IMUX5_4->BRAM_FIFO36_TSTIN0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTIN0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX5_4" }, "BRAM_L.BRAM_IMUX6_1->BRAM_FIFO18_DIBDI6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX6_1" }, "BRAM_L.BRAM_IMUX6_1->BRAM_FIFO36_DIBDIL6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX6_1" }, "BRAM_L.BRAM_IMUX6_2->BRAM_FIFO18_WEBWE4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_WEBWE4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX6_2" }, "BRAM_L.BRAM_IMUX6_2->BRAM_FIFO36_WEBWEL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX6_2" }, "BRAM_L.BRAM_IMUX6_3->BRAM_FIFO36_DIBDIU11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX6_3" }, "BRAM_L.BRAM_IMUX6_3->BRAM_RAMB18_DIBDI11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX6_3" }, "BRAM_L.BRAM_IMUX7_1->BRAM_FIFO18_DIBDI14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX7_1" }, "BRAM_L.BRAM_IMUX7_1->BRAM_FIFO36_DIBDIL14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX7_1" }, "BRAM_L.BRAM_IMUX8_0->BRAM_FIFO36_TSTIN3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTIN3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX8_0" }, "BRAM_L.BRAM_IMUX8_1->BRAM_FIFO36_DIADIU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX8_1" }, "BRAM_L.BRAM_IMUX8_1->BRAM_RAMB18_DIADI0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX8_1" }, "BRAM_L.BRAM_IMUX8_2->BRAM_FIFO36_WEAU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEAU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX8_2" }, "BRAM_L.BRAM_IMUX8_2->BRAM_RAMB18_WEA0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_WEA0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX8_2" }, "BRAM_L.BRAM_IMUX8_3->BRAM_IMUX_ADDRARDADDRU6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX8_3" }, "BRAM_L.BRAM_IMUX8_4->BRAM_FIFO36_DIADIU4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX8_4" }, "BRAM_L.BRAM_IMUX8_4->BRAM_RAMB18_DIADI4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX8_4" }, "BRAM_L.BRAM_IMUX9_1->BRAM_IMUX_ADDRARDADDRU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX9_1" }, "BRAM_L.BRAM_IMUX9_2->BRAM_FIFO36_WEAU2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEAU2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX9_2" }, "BRAM_L.BRAM_IMUX9_2->BRAM_RAMB18_WEA2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_WEA2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX9_2" }, "BRAM_L.BRAM_IMUX9_3->BRAM_IMUX_ADDRARDADDRU7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX9_3" }, "BRAM_L.BRAM_IMUX9_4->BRAM_FIFO36_DIADIU12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX9_4" }, "BRAM_L.BRAM_IMUX9_4->BRAM_RAMB18_DIADI12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX9_4" }, "BRAM_L.BRAM_IMUX10_0->BRAM_FIFO36_TSTCNT0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX10_0" }, "BRAM_L.BRAM_IMUX10_1->BRAM_IMUX_ADDRARDADDRU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX10_1" }, "BRAM_L.BRAM_IMUX10_2->BRAM_FIFO36_ENARDENU": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_ENARDENU", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX10_2" }, "BRAM_L.BRAM_IMUX10_2->BRAM_RAMB18_ENARDEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_ENARDEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX10_2" }, "BRAM_L.BRAM_IMUX10_3->BRAM_IMUX_ADDRARDADDRU3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX10_3" }, "BRAM_L.BRAM_IMUX10_4->BRAM_FIFO36_DIADIU5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX10_4" }, "BRAM_L.BRAM_IMUX10_4->BRAM_RAMB18_DIADI5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX10_4" }, "BRAM_L.BRAM_IMUX11_0->BRAM_FIFO36_TSTCNT1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX11_0" }, "BRAM_L.BRAM_IMUX11_1->BRAM_IMUX_ADDRARDADDRU2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX11_1" }, "BRAM_L.BRAM_IMUX11_2->BRAM_FIFO36_REGCEAREGCEU": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_REGCEAREGCEU", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX11_2" }, "BRAM_L.BRAM_IMUX11_2->BRAM_RAMB18_REGCEAREGCE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_REGCEAREGCE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX11_2" }, "BRAM_L.BRAM_IMUX11_3->BRAM_IMUX_ADDRARDADDRU9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX11_3" }, "BRAM_L.BRAM_IMUX11_4->BRAM_FIFO36_DIADIU13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX11_4" }, "BRAM_L.BRAM_IMUX11_4->BRAM_RAMB18_DIADI13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX11_4" }, "BRAM_L.BRAM_IMUX12_0->BRAM_FIFO36_TSTCNT2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX12_0" }, "BRAM_L.BRAM_IMUX12_1->BRAM_IMUX_ADDRARDADDRU8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX12_1" }, "BRAM_L.BRAM_IMUX12_2->BRAM_IMUX_ADDRARDADDRU10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX12_2" }, "BRAM_L.BRAM_IMUX12_3->BRAM_IMUX_ADDRARDADDRU5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX12_3" }, "BRAM_L.BRAM_IMUX12_4->BRAM_FIFO36_DIADIU6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX12_4" }, "BRAM_L.BRAM_IMUX12_4->BRAM_RAMB18_DIADI6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX12_4" }, "BRAM_L.BRAM_IMUX13_0->BRAM_FIFO36_TSTCNT3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX13_0" }, "BRAM_L.BRAM_IMUX13_1->BRAM_IMUX_ADDRARDADDRU4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX13_1" }, "BRAM_L.BRAM_IMUX13_2->BRAM_FIFO36_WEBWEU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX13_2" }, "BRAM_L.BRAM_IMUX13_2->BRAM_RAMB18_WEBWE1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_WEBWE1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX13_2" }, "BRAM_L.BRAM_IMUX13_3->BRAM_IMUX_ADDRARDADDRU12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX13_3" }, "BRAM_L.BRAM_IMUX13_4->BRAM_FIFO36_DIADIU14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX13_4" }, "BRAM_L.BRAM_IMUX13_4->BRAM_RAMB18_DIADI14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX13_4" }, "BRAM_L.BRAM_IMUX14_0->BRAM_FIFO36_TSTCNT4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX14_0" }, "BRAM_L.BRAM_IMUX14_1->BRAM_IMUX_ADDRARDADDRU11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX14_1" }, "BRAM_L.BRAM_IMUX14_2->BRAM_FIFO36_WEBWEU5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEU5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX14_2" }, "BRAM_L.BRAM_IMUX14_2->BRAM_RAMB18_WEBWE5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_WEBWE5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX14_2" }, "BRAM_L.BRAM_IMUX14_3->BRAM_IMUX_ADDRARDADDRU14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX14_3" }, "BRAM_L.BRAM_IMUX14_4->BRAM_FIFO36_DIADIU7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX14_4" }, "BRAM_L.BRAM_IMUX14_4->BRAM_RAMB18_DIADI7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX14_4" }, "BRAM_L.BRAM_IMUX15_0->BRAM_FIFO36_TSTCNT5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX15_0" }, "BRAM_L.BRAM_IMUX15_1->BRAM_IMUX_ADDRARDADDRU13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX15_1" }, "BRAM_L.BRAM_IMUX15_2->BRAM_FIFO36_DIADIU8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX15_2" }, "BRAM_L.BRAM_IMUX15_2->BRAM_RAMB18_DIADI8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX15_2" }, "BRAM_L.BRAM_IMUX15_3->BRAM_FIFO36_DIPADIPU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIPADIPU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX15_3" }, "BRAM_L.BRAM_IMUX15_3->BRAM_RAMB18_DIPADIP1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIPADIP1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX15_3" }, "BRAM_L.BRAM_IMUX15_4->BRAM_FIFO36_DIADIU15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX15_4" }, "BRAM_L.BRAM_IMUX15_4->BRAM_RAMB18_DIADI15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX15_4" }, "BRAM_L.BRAM_IMUX16_0->BRAM_FIFO36_TSTIN1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTIN1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX16_0" }, "BRAM_L.BRAM_IMUX16_1->BRAM_FIFO18_DIADI0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX16_1" }, "BRAM_L.BRAM_IMUX16_1->BRAM_FIFO36_DIADIL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX16_1" }, "BRAM_L.BRAM_IMUX16_2->BRAM_FIFO18_WEA0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_WEA0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX16_2" }, "BRAM_L.BRAM_IMUX16_2->BRAM_FIFO36_WEAL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEAL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX16_2" }, "BRAM_L.BRAM_IMUX16_3->BRAM_IMUX_ADDRARDADDRL6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX16_3" }, "BRAM_L.BRAM_IMUX16_4->BRAM_FIFO36_DIBDIU4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX16_4" }, "BRAM_L.BRAM_IMUX16_4->BRAM_RAMB18_DIBDI4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX16_4" }, "BRAM_L.BRAM_IMUX17_1->BRAM_IMUX_ADDRARDADDRL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX17_1" }, "BRAM_L.BRAM_IMUX17_2->BRAM_FIFO18_WEA2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_WEA2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX17_2" }, "BRAM_L.BRAM_IMUX17_2->BRAM_FIFO36_WEAL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEAL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX17_2" }, "BRAM_L.BRAM_IMUX17_3->BRAM_IMUX_ADDRARDADDRL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX17_3" }, "BRAM_L.BRAM_IMUX17_4->BRAM_FIFO36_DIBDIU12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX17_4" }, "BRAM_L.BRAM_IMUX17_4->BRAM_RAMB18_DIBDI12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX17_4" }, "BRAM_L.BRAM_IMUX18_0->BRAM_FIFO36_TSTRDOS0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX18_0" }, "BRAM_L.BRAM_IMUX18_1->BRAM_IMUX_ADDRARDADDRL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX18_1" }, "BRAM_L.BRAM_IMUX18_2->BRAM_FIFO18_ENARDEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_ENARDEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX18_2" }, "BRAM_L.BRAM_IMUX18_2->BRAM_FIFO36_ENARDENL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_ENARDENL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX18_2" }, "BRAM_L.BRAM_IMUX18_3->BRAM_IMUX_ADDRARDADDRL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX18_3" }, "BRAM_L.BRAM_IMUX18_4->BRAM_FIFO36_DIBDIU5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX18_4" }, "BRAM_L.BRAM_IMUX18_4->BRAM_RAMB18_DIBDI5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX18_4" }, "BRAM_L.BRAM_IMUX19_0->BRAM_FIFO36_TSTRDOS1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX19_0" }, "BRAM_L.BRAM_IMUX19_1->BRAM_IMUX_ADDRARDADDRL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX19_1" }, "BRAM_L.BRAM_IMUX19_2->BRAM_FIFO18_REGCEAREGCE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_REGCEAREGCE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX19_2" }, "BRAM_L.BRAM_IMUX19_2->BRAM_FIFO36_REGCEAREGCEL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_REGCEAREGCEL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX19_2" }, "BRAM_L.BRAM_IMUX19_3->BRAM_IMUX_ADDRARDADDRL9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX19_3" }, "BRAM_L.BRAM_IMUX19_4->BRAM_FIFO36_DIBDIU13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX19_4" }, "BRAM_L.BRAM_IMUX19_4->BRAM_RAMB18_DIBDI13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX19_4" }, "BRAM_L.BRAM_IMUX20_0->BRAM_FIFO36_TSTRDOS2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX20_0" }, "BRAM_L.BRAM_IMUX20_1->BRAM_IMUX_ADDRARDADDRL8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX20_1" }, "BRAM_L.BRAM_IMUX20_2->BRAM_IMUX_ADDRARDADDRL10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX20_2" }, "BRAM_L.BRAM_IMUX20_3->BRAM_IMUX_ADDRARDADDRL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX20_3" }, "BRAM_L.BRAM_IMUX20_4->BRAM_FIFO36_DIBDIU6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX20_4" }, "BRAM_L.BRAM_IMUX20_4->BRAM_RAMB18_DIBDI6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX20_4" }, "BRAM_L.BRAM_IMUX21_0->BRAM_FIFO36_TSTRDOS3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX21_0" }, "BRAM_L.BRAM_IMUX21_1->BRAM_IMUX_ADDRARDADDRL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX21_1" }, "BRAM_L.BRAM_IMUX21_2->BRAM_FIFO18_WEBWE1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_WEBWE1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX21_2" }, "BRAM_L.BRAM_IMUX21_2->BRAM_FIFO36_WEBWEL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX21_2" }, "BRAM_L.BRAM_IMUX21_3->BRAM_IMUX_ADDRARDADDRL12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX21_3" }, "BRAM_L.BRAM_IMUX21_4->BRAM_FIFO36_DIBDIU14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX21_4" }, "BRAM_L.BRAM_IMUX21_4->BRAM_RAMB18_DIBDI14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX21_4" }, "BRAM_L.BRAM_IMUX22_0->BRAM_FIFO36_TSTRDOS4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX22_0" }, "BRAM_L.BRAM_IMUX22_1->BRAM_IMUX_ADDRARDADDRL11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX22_1" }, "BRAM_L.BRAM_IMUX22_2->BRAM_FIFO18_WEBWE5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_WEBWE5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX22_2" }, "BRAM_L.BRAM_IMUX22_2->BRAM_FIFO36_WEBWEL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX22_2" }, "BRAM_L.BRAM_IMUX22_3->BRAM_IMUX_ADDRARDADDRL14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX22_3" }, "BRAM_L.BRAM_IMUX22_4->BRAM_FIFO36_DIBDIU7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX22_4" }, "BRAM_L.BRAM_IMUX22_4->BRAM_RAMB18_DIBDI7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX22_4" }, "BRAM_L.BRAM_IMUX23_0->BRAM_FIFO36_TSTRDOS5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX23_0" }, "BRAM_L.BRAM_IMUX23_1->BRAM_IMUX_ADDRARDADDRL13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX23_1" }, "BRAM_L.BRAM_IMUX23_2->BRAM_FIFO36_DIBDIU8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX23_2" }, "BRAM_L.BRAM_IMUX23_2->BRAM_RAMB18_DIBDI8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX23_2" }, "BRAM_L.BRAM_IMUX23_3->BRAM_FIFO36_DIPBDIPU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIPBDIPU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX23_3" }, "BRAM_L.BRAM_IMUX23_3->BRAM_RAMB18_DIPBDIP1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIPBDIP1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX23_3" }, "BRAM_L.BRAM_IMUX23_4->BRAM_FIFO36_DIBDIU15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX23_4" }, "BRAM_L.BRAM_IMUX23_4->BRAM_RAMB18_DIBDI15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX23_4" }, "BRAM_L.BRAM_IMUX24_1->BRAM_FIFO36_DIBDIU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX24_1" }, "BRAM_L.BRAM_IMUX24_1->BRAM_RAMB18_DIBDI0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIBDI0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX24_1" }, "BRAM_L.BRAM_IMUX24_2->BRAM_FIFO36_WEAU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEAU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX24_2" }, "BRAM_L.BRAM_IMUX24_2->BRAM_RAMB18_WEA1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_WEA1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX24_2" }, "BRAM_L.BRAM_IMUX24_3->BRAM_IMUX_ADDRBWRADDRU6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX24_3" }, "BRAM_L.BRAM_IMUX24_4->BRAM_FIFO36_TSTCNT6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX24_4" }, "BRAM_L.BRAM_IMUX25_0->BRAM_FIFO18_DIADI8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX25_0" }, "BRAM_L.BRAM_IMUX25_0->BRAM_FIFO36_DIADIL8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX25_0" }, "BRAM_L.BRAM_IMUX25_1->BRAM_IMUX_ADDRBWRADDRU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX25_1" }, "BRAM_L.BRAM_IMUX25_2->BRAM_FIFO36_WEAU3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEAU3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX25_2" }, "BRAM_L.BRAM_IMUX25_2->BRAM_RAMB18_WEA3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_WEA3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX25_2" }, "BRAM_L.BRAM_IMUX25_3->BRAM_IMUX_ADDRBWRADDRU7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX25_3" }, "BRAM_L.BRAM_IMUX25_4->BRAM_FIFO36_TSTCNT7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX25_4" }, "BRAM_L.BRAM_IMUX26_0->BRAM_FIFO18_DIADI1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX26_0" }, "BRAM_L.BRAM_IMUX26_0->BRAM_FIFO36_DIADIL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX26_0" }, "BRAM_L.BRAM_IMUX26_1->BRAM_IMUX_ADDRBWRADDRU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX26_1" }, "BRAM_L.BRAM_IMUX26_2->BRAM_FIFO36_ENBWRENU": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_ENBWRENU", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX26_2" }, "BRAM_L.BRAM_IMUX26_2->BRAM_RAMB18_ENBWREN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_ENBWREN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX26_2" }, "BRAM_L.BRAM_IMUX26_3->BRAM_IMUX_ADDRBWRADDRU3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX26_3" }, "BRAM_L.BRAM_IMUX26_4->BRAM_FIFO36_TSTCNT8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX26_4" }, "BRAM_L.BRAM_IMUX27_0->BRAM_FIFO18_DIADI9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX27_0" }, "BRAM_L.BRAM_IMUX27_0->BRAM_FIFO36_DIADIL9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX27_0" }, "BRAM_L.BRAM_IMUX27_1->BRAM_IMUX_ADDRBWRADDRU2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX27_1" }, "BRAM_L.BRAM_IMUX27_2->BRAM_FIFO36_REGCEBU": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_REGCEBU", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX27_2" }, "BRAM_L.BRAM_IMUX27_2->BRAM_RAMB18_REGCEB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_REGCEB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX27_2" }, "BRAM_L.BRAM_IMUX27_3->BRAM_IMUX_ADDRBWRADDRU9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX27_3" }, "BRAM_L.BRAM_IMUX27_4->BRAM_FIFO36_TSTCNT9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX27_4" }, "BRAM_L.BRAM_IMUX28_0->BRAM_FIFO18_DIADI2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX28_0" }, "BRAM_L.BRAM_IMUX28_0->BRAM_FIFO36_DIADIL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX28_0" }, "BRAM_L.BRAM_IMUX28_1->BRAM_IMUX_ADDRBWRADDRU8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX28_1" }, "BRAM_L.BRAM_IMUX28_2->BRAM_IMUX_ADDRBWRADDRU10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX28_2" }, "BRAM_L.BRAM_IMUX28_3->BRAM_IMUX_ADDRBWRADDRU5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX28_3" }, "BRAM_L.BRAM_IMUX28_4->BRAM_FIFO36_TSTCNT10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX28_4" }, "BRAM_L.BRAM_IMUX29_0->BRAM_FIFO18_DIADI10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX29_0" }, "BRAM_L.BRAM_IMUX29_0->BRAM_FIFO36_DIADIL10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX29_0" }, "BRAM_L.BRAM_IMUX29_1->BRAM_IMUX_ADDRBWRADDRU4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX29_1" }, "BRAM_L.BRAM_IMUX29_2->BRAM_FIFO36_WEBWEU2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEU2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX29_2" }, "BRAM_L.BRAM_IMUX29_2->BRAM_RAMB18_WEBWE2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_WEBWE2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX29_2" }, "BRAM_L.BRAM_IMUX29_3->BRAM_IMUX_ADDRBWRADDRU12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX29_3" }, "BRAM_L.BRAM_IMUX29_4->BRAM_FIFO36_TSTCNT11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX29_4" }, "BRAM_L.BRAM_IMUX30_0->BRAM_FIFO18_DIADI3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX30_0" }, "BRAM_L.BRAM_IMUX30_0->BRAM_FIFO36_DIADIL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX30_0" }, "BRAM_L.BRAM_IMUX30_1->BRAM_IMUX_ADDRBWRADDRU11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX30_1" }, "BRAM_L.BRAM_IMUX30_2->BRAM_FIFO36_WEBWEU6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEU6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX30_2" }, "BRAM_L.BRAM_IMUX30_2->BRAM_RAMB18_WEBWE6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_WEBWE6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX30_2" }, "BRAM_L.BRAM_IMUX30_3->BRAM_IMUX_ADDRBWRADDRU14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX30_3" }, "BRAM_L.BRAM_IMUX30_4->BRAM_FIFO36_TSTCNT12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTCNT12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX30_4" }, "BRAM_L.BRAM_IMUX31_0->BRAM_FIFO18_DIADI11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX31_0" }, "BRAM_L.BRAM_IMUX31_0->BRAM_FIFO36_DIADIL11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX31_0" }, "BRAM_L.BRAM_IMUX31_1->BRAM_IMUX_ADDRBWRADDRU13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX31_1" }, "BRAM_L.BRAM_IMUX31_2->BRAM_FIFO36_INJECTDBITERR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_INJECTDBITERR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX31_2" }, "BRAM_L.BRAM_IMUX31_3->BRAM_IMUX_ADDRARDADDRL15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX31_3" }, "BRAM_L.BRAM_IMUX32_1->BRAM_FIFO18_DIBDI0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX32_1" }, "BRAM_L.BRAM_IMUX32_1->BRAM_FIFO36_DIBDIL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX32_1" }, "BRAM_L.BRAM_IMUX32_2->BRAM_FIFO18_WEA1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_WEA1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX32_2" }, "BRAM_L.BRAM_IMUX32_2->BRAM_FIFO36_WEAL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEAL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX32_2" }, "BRAM_L.BRAM_IMUX32_3->BRAM_IMUX_ADDRBWRADDRL6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX32_3" }, "BRAM_L.BRAM_IMUX32_4->BRAM_FIFO36_TSTRDOS6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX32_4" }, "BRAM_L.BRAM_IMUX33_0->BRAM_FIFO18_DIBDI8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX33_0" }, "BRAM_L.BRAM_IMUX33_0->BRAM_FIFO36_DIBDIL8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX33_0" }, "BRAM_L.BRAM_IMUX33_1->BRAM_IMUX_ADDRBWRADDRL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX33_1" }, "BRAM_L.BRAM_IMUX33_2->BRAM_FIFO18_WEA3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_WEA3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX33_2" }, "BRAM_L.BRAM_IMUX33_2->BRAM_FIFO36_WEAL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEAL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX33_2" }, "BRAM_L.BRAM_IMUX33_3->BRAM_IMUX_ADDRBWRADDRL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX33_3" }, "BRAM_L.BRAM_IMUX33_4->BRAM_FIFO36_TSTRDOS7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX33_4" }, "BRAM_L.BRAM_IMUX34_0->BRAM_FIFO18_DIBDI1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX34_0" }, "BRAM_L.BRAM_IMUX34_0->BRAM_FIFO36_DIBDIL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX34_0" }, "BRAM_L.BRAM_IMUX34_1->BRAM_IMUX_ADDRBWRADDRL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX34_1" }, "BRAM_L.BRAM_IMUX34_2->BRAM_FIFO18_ENBWREN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_ENBWREN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX34_2" }, "BRAM_L.BRAM_IMUX34_2->BRAM_FIFO36_ENBWRENL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_ENBWRENL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX34_2" }, "BRAM_L.BRAM_IMUX34_3->BRAM_IMUX_ADDRBWRADDRL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX34_3" }, "BRAM_L.BRAM_IMUX34_4->BRAM_FIFO36_TSTRDOS8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX34_4" }, "BRAM_L.BRAM_IMUX35_0->BRAM_FIFO18_DIBDI9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX35_0" }, "BRAM_L.BRAM_IMUX35_0->BRAM_FIFO36_DIBDIL9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX35_0" }, "BRAM_L.BRAM_IMUX35_1->BRAM_IMUX_ADDRBWRADDRL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX35_1" }, "BRAM_L.BRAM_IMUX35_2->BRAM_FIFO18_REGCEB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_REGCEB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX35_2" }, "BRAM_L.BRAM_IMUX35_2->BRAM_FIFO36_REGCEBL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_REGCEBL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX35_2" }, "BRAM_L.BRAM_IMUX35_3->BRAM_IMUX_ADDRBWRADDRL9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX35_3" }, "BRAM_L.BRAM_IMUX35_4->BRAM_FIFO36_TSTRDOS9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX35_4" }, "BRAM_L.BRAM_IMUX36_0->BRAM_FIFO18_DIBDI2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX36_0" }, "BRAM_L.BRAM_IMUX36_0->BRAM_FIFO36_DIBDIL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX36_0" }, "BRAM_L.BRAM_IMUX36_1->BRAM_IMUX_ADDRBWRADDRL8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX36_1" }, "BRAM_L.BRAM_IMUX36_2->BRAM_IMUX_ADDRBWRADDRL10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX36_2" }, "BRAM_L.BRAM_IMUX36_3->BRAM_IMUX_ADDRBWRADDRL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX36_3" }, "BRAM_L.BRAM_IMUX36_4->BRAM_FIFO36_TSTRDOS10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX36_4" }, "BRAM_L.BRAM_IMUX37_0->BRAM_FIFO18_DIBDI10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX37_0" }, "BRAM_L.BRAM_IMUX37_0->BRAM_FIFO36_DIBDIL10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX37_0" }, "BRAM_L.BRAM_IMUX37_1->BRAM_IMUX_ADDRBWRADDRL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX37_1" }, "BRAM_L.BRAM_IMUX37_2->BRAM_FIFO18_WEBWE2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_WEBWE2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX37_2" }, "BRAM_L.BRAM_IMUX37_2->BRAM_FIFO36_WEBWEL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX37_2" }, "BRAM_L.BRAM_IMUX37_3->BRAM_IMUX_ADDRBWRADDRL12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX37_3" }, "BRAM_L.BRAM_IMUX37_4->BRAM_FIFO36_TSTRDOS11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX37_4" }, "BRAM_L.BRAM_IMUX38_0->BRAM_FIFO18_DIBDI3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX38_0" }, "BRAM_L.BRAM_IMUX38_0->BRAM_FIFO36_DIBDIL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX38_0" }, "BRAM_L.BRAM_IMUX38_1->BRAM_IMUX_ADDRBWRADDRL11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX38_1" }, "BRAM_L.BRAM_IMUX38_2->BRAM_FIFO18_WEBWE6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_WEBWE6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX38_2" }, "BRAM_L.BRAM_IMUX38_2->BRAM_FIFO36_WEBWEL6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEL6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX38_2" }, "BRAM_L.BRAM_IMUX38_3->BRAM_IMUX_ADDRBWRADDRL14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX38_3" }, "BRAM_L.BRAM_IMUX38_4->BRAM_FIFO36_TSTRDOS12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTRDOS12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX38_4" }, "BRAM_L.BRAM_IMUX39_0->BRAM_FIFO18_DIBDI11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIBDI11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX39_0" }, "BRAM_L.BRAM_IMUX39_0->BRAM_FIFO36_DIBDIL11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIBDIL11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX39_0" }, "BRAM_L.BRAM_IMUX39_1->BRAM_IMUX_ADDRBWRADDRL13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX39_1" }, "BRAM_L.BRAM_IMUX39_2->BRAM_FIFO36_INJECTSBITERR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_INJECTSBITERR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX39_2" }, "BRAM_L.BRAM_IMUX39_3->BRAM_IMUX_ADDRBWRADDRL15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX39_3" }, "BRAM_L.BRAM_IMUX40_1->BRAM_FIFO18_DIPADIP1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIPADIP1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX40_1" }, "BRAM_L.BRAM_IMUX40_1->BRAM_FIFO36_DIPADIPL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIPADIPL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX40_1" }, "BRAM_L.BRAM_IMUX40_2->BRAM_FIFO18_DIADI7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX40_2" }, "BRAM_L.BRAM_IMUX40_2->BRAM_FIFO36_DIADIL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX40_2" }, "BRAM_L.BRAM_IMUX40_3->BRAM_FIFO36_DIADIU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX40_3" }, "BRAM_L.BRAM_IMUX40_3->BRAM_RAMB18_DIADI1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX40_3" }, "BRAM_L.BRAM_IMUX40_4->BRAM_FIFO36_TSTWROS6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX40_4" }, "BRAM_L.BRAM_IMUX41_0->BRAM_FIFO36_TSTIN4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTIN4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX41_0" }, "BRAM_L.BRAM_IMUX41_1->BRAM_FIFO18_DIADI4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX41_1" }, "BRAM_L.BRAM_IMUX41_1->BRAM_FIFO36_DIADIL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX41_1" }, "BRAM_L.BRAM_IMUX41_2->BRAM_FIFO18_DIADI15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX41_2" }, "BRAM_L.BRAM_IMUX41_2->BRAM_FIFO36_DIADIL15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX41_2" }, "BRAM_L.BRAM_IMUX41_3->BRAM_FIFO36_DIADIU9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX41_3" }, "BRAM_L.BRAM_IMUX41_3->BRAM_RAMB18_DIADI9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX41_3" }, "BRAM_L.BRAM_IMUX41_4->BRAM_FIFO36_TSTWROS7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX41_4" }, "BRAM_L.BRAM_IMUX42_0->BRAM_FIFO36_TSTWROS0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX42_0" }, "BRAM_L.BRAM_IMUX42_1->BRAM_FIFO18_DIADI12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX42_1" }, "BRAM_L.BRAM_IMUX42_1->BRAM_FIFO36_DIADIL12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX42_1" }, "BRAM_L.BRAM_IMUX42_2->BRAM_FIFO36_DIPADIPU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIPADIPU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX42_2" }, "BRAM_L.BRAM_IMUX42_2->BRAM_RAMB18_DIPADIP0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIPADIP0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX42_2" }, "BRAM_L.BRAM_IMUX42_3->BRAM_FIFO36_DIADIU2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX42_3" }, "BRAM_L.BRAM_IMUX42_3->BRAM_RAMB18_DIADI2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX42_3" }, "BRAM_L.BRAM_IMUX42_4->BRAM_FIFO36_TSTWROS8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX42_4" }, "BRAM_L.BRAM_IMUX43_0->BRAM_FIFO36_TSTWROS1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX43_0" }, "BRAM_L.BRAM_IMUX43_1->BRAM_FIFO18_DIADI5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX43_1" }, "BRAM_L.BRAM_IMUX43_1->BRAM_FIFO36_DIADIL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX43_1" }, "BRAM_L.BRAM_IMUX43_2->BRAM_FIFO36_DIPBDIPU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIPBDIPU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX43_2" }, "BRAM_L.BRAM_IMUX43_2->BRAM_RAMB18_DIPBDIP0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIPBDIP0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX43_2" }, "BRAM_L.BRAM_IMUX43_3->BRAM_FIFO36_DIADIU10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX43_3" }, "BRAM_L.BRAM_IMUX43_3->BRAM_RAMB18_DIADI10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX43_3" }, "BRAM_L.BRAM_IMUX43_4->BRAM_FIFO36_TSTWROS9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX43_4" }, "BRAM_L.BRAM_IMUX44_0->BRAM_FIFO36_TSTWROS2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX44_0" }, "BRAM_L.BRAM_IMUX44_1->BRAM_FIFO18_DIADI13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX44_1" }, "BRAM_L.BRAM_IMUX44_1->BRAM_FIFO36_DIADIL13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX44_1" }, "BRAM_L.BRAM_IMUX44_3->BRAM_FIFO36_DIADIU3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX44_3" }, "BRAM_L.BRAM_IMUX44_3->BRAM_RAMB18_DIADI3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX44_3" }, "BRAM_L.BRAM_IMUX44_4->BRAM_FIFO36_TSTWROS10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX44_4" }, "BRAM_L.BRAM_IMUX45_0->BRAM_FIFO36_TSTWROS3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX45_0" }, "BRAM_L.BRAM_IMUX45_1->BRAM_FIFO18_DIADI6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX45_1" }, "BRAM_L.BRAM_IMUX45_1->BRAM_FIFO36_DIADIL6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX45_1" }, "BRAM_L.BRAM_IMUX45_2->BRAM_FIFO36_WEBWEU3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEU3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX45_2" }, "BRAM_L.BRAM_IMUX45_2->BRAM_RAMB18_WEBWE3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_WEBWE3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX45_2" }, "BRAM_L.BRAM_IMUX45_3->BRAM_FIFO36_DIADIU11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIU11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX45_3" }, "BRAM_L.BRAM_IMUX45_3->BRAM_RAMB18_DIADI11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_DIADI11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX45_3" }, "BRAM_L.BRAM_IMUX45_4->BRAM_FIFO36_TSTWROS11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX45_4" }, "BRAM_L.BRAM_IMUX46_0->BRAM_FIFO36_TSTWROS4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX46_0" }, "BRAM_L.BRAM_IMUX46_1->BRAM_FIFO18_DIADI14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO18_DIADI14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX46_1" }, "BRAM_L.BRAM_IMUX46_1->BRAM_FIFO36_DIADIL14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_DIADIL14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX46_1" }, "BRAM_L.BRAM_IMUX46_2->BRAM_FIFO36_WEBWEU7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_WEBWEU7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX46_2" }, "BRAM_L.BRAM_IMUX46_2->BRAM_RAMB18_WEBWE7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_RAMB18_WEBWE7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX46_2" }, "BRAM_L.BRAM_IMUX46_4->BRAM_FIFO36_TSTWROS12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX46_4" }, "BRAM_L.BRAM_IMUX47_0->BRAM_FIFO36_TSTWROS5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_FIFO36_TSTWROS5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX47_0" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL0->BRAM_ADDRARDADDRL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL0" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL1->BRAM_ADDRARDADDRL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL1" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL2->BRAM_ADDRARDADDRL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL2" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL3->BRAM_ADDRARDADDRL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL3" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL4->BRAM_ADDRARDADDRL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL4" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL5->BRAM_ADDRARDADDRL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL5" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL6->BRAM_ADDRARDADDRL6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL6" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL7->BRAM_ADDRARDADDRL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL7" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL8->BRAM_ADDRARDADDRL8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL8" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL9->BRAM_ADDRARDADDRL9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL9" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL10->BRAM_ADDRARDADDRL10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL10" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL11->BRAM_ADDRARDADDRL11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL11" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL12->BRAM_ADDRARDADDRL12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL12" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL13->BRAM_ADDRARDADDRL13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL13" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL14->BRAM_ADDRARDADDRL14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL14" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_FIFO18_ADDRATIEHIGH1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_FIFO36_ADDRARDADDRL15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_RAMB18_ADDRATIEHIGH1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_UTURN_ADDRARDADDRL15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_IMUX_ADDRARDADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU0" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU1" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU2" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU3" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU4" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU5" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU6" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU7" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU8" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU9" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU10" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU11" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU12" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU13" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRARDADDRU14" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL0" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL1" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL2" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL3" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL4" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL5" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL6" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL7" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL8" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL9" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL10" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL11" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL12" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL13" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL14" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_FIFO18_ADDRBTIEHIGH1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_FIFO36_ADDRBWRADDRL15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_RAMB18_ADDRBTIEHIGH1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.046", "0.111", "0.134" ], "in_cap": "0.000", "res": "737.319" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_UTURN_ADDRBWRADDRL15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU0" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU1" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU2" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU3" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU4" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU5" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU6" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU7" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU8" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU9" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU10" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU11" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU12" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU13" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU14" }, "BRAM_L.BRAM_RAMB18_DOADO0->BRAM_LOGIC_OUTS_B15_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B15_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO0" }, "BRAM_L.BRAM_RAMB18_DOADO1->BRAM_LOGIC_OUTS_B8_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B8_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO1" }, "BRAM_L.BRAM_RAMB18_DOADO2->BRAM_LOGIC_OUTS_B13_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B13_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO2" }, "BRAM_L.BRAM_RAMB18_DOADO3->BRAM_LOGIC_OUTS_B10_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B10_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO3" }, "BRAM_L.BRAM_RAMB18_DOADO4->BRAM_LOGIC_OUTS_B8_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B8_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO4" }, "BRAM_L.BRAM_RAMB18_DOADO5->BRAM_LOGIC_OUTS_B13_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B13_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO5" }, "BRAM_L.BRAM_RAMB18_DOADO6->BRAM_LOGIC_OUTS_B10_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B10_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO6" }, "BRAM_L.BRAM_RAMB18_DOADO7->BRAM_LOGIC_OUTS_B15_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B15_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO7" }, "BRAM_L.BRAM_RAMB18_DOADO8->BRAM_LOGIC_OUTS_B7_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B7_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO8" }, "BRAM_L.BRAM_RAMB18_DOADO9->BRAM_LOGIC_OUTS_B0_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B0_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO9" }, "BRAM_L.BRAM_RAMB18_DOADO10->BRAM_LOGIC_OUTS_B5_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B5_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO10" }, "BRAM_L.BRAM_RAMB18_DOADO11->BRAM_LOGIC_OUTS_B2_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B2_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO11" }, "BRAM_L.BRAM_RAMB18_DOADO12->BRAM_LOGIC_OUTS_B0_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B0_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO12" }, "BRAM_L.BRAM_RAMB18_DOADO13->BRAM_LOGIC_OUTS_B5_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B5_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO13" }, "BRAM_L.BRAM_RAMB18_DOADO14->BRAM_LOGIC_OUTS_B2_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B2_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO14" }, "BRAM_L.BRAM_RAMB18_DOADO15->BRAM_LOGIC_OUTS_B7_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B7_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOADO15" }, "BRAM_L.BRAM_RAMB18_DOBDO0->BRAM_LOGIC_OUTS_B3_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B3_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO0" }, "BRAM_L.BRAM_RAMB18_DOBDO1->BRAM_LOGIC_OUTS_B4_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B4_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO1" }, "BRAM_L.BRAM_RAMB18_DOBDO2->BRAM_LOGIC_OUTS_B1_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B1_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO2" }, "BRAM_L.BRAM_RAMB18_DOBDO3->BRAM_LOGIC_OUTS_B6_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B6_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO3" }, "BRAM_L.BRAM_RAMB18_DOBDO4->BRAM_LOGIC_OUTS_B4_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B4_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO4" }, "BRAM_L.BRAM_RAMB18_DOBDO5->BRAM_LOGIC_OUTS_B1_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B1_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO5" }, "BRAM_L.BRAM_RAMB18_DOBDO6->BRAM_LOGIC_OUTS_B6_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B6_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO6" }, "BRAM_L.BRAM_RAMB18_DOBDO7->BRAM_LOGIC_OUTS_B3_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B3_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO7" }, "BRAM_L.BRAM_RAMB18_DOBDO8->BRAM_LOGIC_OUTS_B17_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B17_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO8" }, "BRAM_L.BRAM_RAMB18_DOBDO9->BRAM_LOGIC_OUTS_B22_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B22_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO9" }, "BRAM_L.BRAM_RAMB18_DOBDO10->BRAM_LOGIC_OUTS_B19_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B19_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO10" }, "BRAM_L.BRAM_RAMB18_DOBDO11->BRAM_LOGIC_OUTS_B20_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B20_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO11" }, "BRAM_L.BRAM_RAMB18_DOBDO12->BRAM_LOGIC_OUTS_B22_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B22_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO12" }, "BRAM_L.BRAM_RAMB18_DOBDO13->BRAM_LOGIC_OUTS_B19_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B19_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO13" }, "BRAM_L.BRAM_RAMB18_DOBDO14->BRAM_LOGIC_OUTS_B20_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B20_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO14" }, "BRAM_L.BRAM_RAMB18_DOBDO15->BRAM_LOGIC_OUTS_B17_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B17_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOBDO15" }, "BRAM_L.BRAM_RAMB18_DOPADOP0->BRAM_LOGIC_OUTS_B15_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B15_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOPADOP0" }, "BRAM_L.BRAM_RAMB18_DOPADOP1->BRAM_LOGIC_OUTS_B7_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B7_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOPADOP1" }, "BRAM_L.BRAM_RAMB18_DOPBDOP0->BRAM_LOGIC_OUTS_B3_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B3_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOPBDOP0" }, "BRAM_L.BRAM_RAMB18_DOPBDOP1->BRAM_LOGIC_OUTS_B17_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "BRAM_LOGIC_OUTS_B17_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "BRAM_RAMB18_DOPBDOP1" } }, "sites": [ { "name": "X0Y0", "prefix": "RAMB18", "site_pins": { "ADDRARDADDR0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR0" }, "ADDRARDADDR1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR1" }, "ADDRARDADDR2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR2" }, "ADDRARDADDR3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR3" }, "ADDRARDADDR4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR4" }, "ADDRARDADDR5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR5" }, "ADDRARDADDR6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR6" }, "ADDRARDADDR7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR7" }, "ADDRARDADDR8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR8" }, "ADDRARDADDR9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR9" }, "ADDRARDADDR10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR10" }, "ADDRARDADDR11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR11" }, "ADDRARDADDR12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR12" }, "ADDRARDADDR13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRARDADDR13" }, "ADDRATIEHIGH0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRATIEHIGH0" }, "ADDRATIEHIGH1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRATIEHIGH1" }, "ADDRBTIEHIGH0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBTIEHIGH0" }, "ADDRBTIEHIGH1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBTIEHIGH1" }, "ADDRBWRADDR0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR0" }, "ADDRBWRADDR1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR1" }, "ADDRBWRADDR2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR2" }, "ADDRBWRADDR3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR3" }, "ADDRBWRADDR4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR4" }, "ADDRBWRADDR5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR5" }, "ADDRBWRADDR6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR6" }, "ADDRBWRADDR7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR7" }, "ADDRBWRADDR8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR8" }, "ADDRBWRADDR9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR9" }, "ADDRBWRADDR10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR10" }, "ADDRBWRADDR11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR11" }, "ADDRBWRADDR12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR12" }, "ADDRBWRADDR13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ADDRBWRADDR13" }, "ALMOSTEMPTY": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_ALMOSTEMPTY" }, "ALMOSTFULL": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_ALMOSTFULL" }, "DIADI0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI0" }, "DIADI1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI1" }, "DIADI2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI2" }, "DIADI3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI3" }, "DIADI4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI4" }, "DIADI5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI5" }, "DIADI6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI6" }, "DIADI7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI7" }, "DIADI8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI8" }, "DIADI9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI9" }, "DIADI10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI10" }, "DIADI11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI11" }, "DIADI12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI12" }, "DIADI13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI13" }, "DIADI14": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI14" }, "DIADI15": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIADI15" }, "DIBDI0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI0" }, "DIBDI1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI1" }, "DIBDI2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI2" }, "DIBDI3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI3" }, "DIBDI4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI4" }, "DIBDI5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI5" }, "DIBDI6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI6" }, "DIBDI7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI7" }, "DIBDI8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI8" }, "DIBDI9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI9" }, "DIBDI10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI10" }, "DIBDI11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI11" }, "DIBDI12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI12" }, "DIBDI13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI13" }, "DIBDI14": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI14" }, "DIBDI15": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIBDI15" }, "DIPADIP0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIPADIP0" }, "DIPADIP1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIPADIP1" }, "DIPBDIP0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIPBDIP0" }, "DIPBDIP1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_DIPBDIP1" }, "DO0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO0" }, "DO1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO1" }, "DO2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO2" }, "DO3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO3" }, "DO4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO4" }, "DO5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO5" }, "DO6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO6" }, "DO7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO7" }, "DO8": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO8" }, "DO9": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO9" }, "DO10": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO10" }, "DO11": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO11" }, "DO12": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO12" }, "DO13": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO13" }, "DO14": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO14" }, "DO15": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOADO15" }, "DO16": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO0" }, "DO17": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO1" }, "DO18": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO2" }, "DO19": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO3" }, "DO20": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO4" }, "DO21": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO5" }, "DO22": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO6" }, "DO23": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO7" }, "DO24": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO8" }, "DO25": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO9" }, "DO26": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO10" }, "DO27": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO11" }, "DO28": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO12" }, "DO29": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO13" }, "DO30": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO14" }, "DO31": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOBDO15" }, "DOP0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOPADOP0" }, "DOP1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOPADOP1" }, "DOP2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOPBDOP0" }, "DOP3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_DOPBDOP1" }, "EMPTY": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_EMPTY" }, "FULL": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_FULL" }, "RDCLK": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_CLKARDCLK" }, "RDCOUNT0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDCOUNT0" }, "RDCOUNT1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDCOUNT1" }, "RDCOUNT2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDCOUNT2" }, "RDCOUNT3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDCOUNT3" }, "RDCOUNT4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDCOUNT4" }, "RDCOUNT5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDCOUNT5" }, "RDCOUNT6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDCOUNT6" }, "RDCOUNT7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDCOUNT7" }, "RDCOUNT8": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDCOUNT8" }, "RDCOUNT9": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDCOUNT9" }, "RDCOUNT10": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDCOUNT10" }, "RDCOUNT11": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDCOUNT11" }, "RDEN": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ENARDEN" }, "RDERR": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_RDERR" }, "RDRCLK": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_REGCLKARDRCLK" }, "REGCE": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_REGCEAREGCE" }, "REGCEB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_REGCEB" }, "REGCLKB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_REGCLKB" }, "RST": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_RSTRAMARSTRAM" }, "RSTRAMB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_RSTRAMB" }, "RSTREG": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_RSTREGARSTREG" }, "RSTREGB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_RSTREGB" }, "WEA0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_WEA0" }, "WEA1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_WEA1" }, "WEA2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_WEA2" }, "WEA3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_WEA3" }, "WEBWE0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_WEBWE0" }, "WEBWE1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_WEBWE1" }, "WEBWE2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_WEBWE2" }, "WEBWE3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_WEBWE3" }, "WEBWE4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_WEBWE4" }, "WEBWE5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_WEBWE5" }, "WEBWE6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_WEBWE6" }, "WEBWE7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_WEBWE7" }, "WRCLK": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_CLKBWRCLK" }, "WRCOUNT0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRCOUNT0" }, "WRCOUNT1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRCOUNT1" }, "WRCOUNT2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRCOUNT2" }, "WRCOUNT3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRCOUNT3" }, "WRCOUNT4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRCOUNT4" }, "WRCOUNT5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRCOUNT5" }, "WRCOUNT6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRCOUNT6" }, "WRCOUNT7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRCOUNT7" }, "WRCOUNT8": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRCOUNT8" }, "WRCOUNT9": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRCOUNT9" }, "WRCOUNT10": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRCOUNT10" }, "WRCOUNT11": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRCOUNT11" }, "WREN": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO18_ENBWREN" }, "WRERR": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "855.9375", "wire": "BRAM_FIFO18_WRERR" } }, "type": "FIFO18E1", "x_coord": 0, "y_coord": 0 }, { "name": "X0Y0", "prefix": "RAMB36", "site_pins": { "ADDRARDADDRL0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL0" }, "ADDRARDADDRL1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL1" }, "ADDRARDADDRL2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL2" }, "ADDRARDADDRL3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL3" }, "ADDRARDADDRL4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL4" }, "ADDRARDADDRL5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL5" }, "ADDRARDADDRL6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL6" }, "ADDRARDADDRL7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL7" }, "ADDRARDADDRL8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL8" }, "ADDRARDADDRL9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL9" }, "ADDRARDADDRL10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL10" }, "ADDRARDADDRL11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL11" }, "ADDRARDADDRL12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL12" }, "ADDRARDADDRL13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL13" }, "ADDRARDADDRL14": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL14" }, "ADDRARDADDRL15": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRL15" }, "ADDRARDADDRU0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU0" }, "ADDRARDADDRU1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU1" }, "ADDRARDADDRU2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU2" }, "ADDRARDADDRU3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU3" }, "ADDRARDADDRU4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU4" }, "ADDRARDADDRU5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU5" }, "ADDRARDADDRU6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU6" }, "ADDRARDADDRU7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU7" }, "ADDRARDADDRU8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU8" }, "ADDRARDADDRU9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU9" }, "ADDRARDADDRU10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU10" }, "ADDRARDADDRU11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU11" }, "ADDRARDADDRU12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU12" }, "ADDRARDADDRU13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU13" }, "ADDRARDADDRU14": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRARDADDRU14" }, "ADDRBWRADDRL0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL0" }, "ADDRBWRADDRL1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL1" }, "ADDRBWRADDRL2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL2" }, "ADDRBWRADDRL3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL3" }, "ADDRBWRADDRL4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL4" }, "ADDRBWRADDRL5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL5" }, "ADDRBWRADDRL6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL6" }, "ADDRBWRADDRL7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL7" }, "ADDRBWRADDRL8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL8" }, "ADDRBWRADDRL9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL9" }, "ADDRBWRADDRL10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL10" }, "ADDRBWRADDRL11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL11" }, "ADDRBWRADDRL12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL12" }, "ADDRBWRADDRL13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL13" }, "ADDRBWRADDRL14": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL14" }, "ADDRBWRADDRL15": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRL15" }, "ADDRBWRADDRU0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU0" }, "ADDRBWRADDRU1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU1" }, "ADDRBWRADDRU2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU2" }, "ADDRBWRADDRU3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU3" }, "ADDRBWRADDRU4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU4" }, "ADDRBWRADDRU5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU5" }, "ADDRBWRADDRU6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU6" }, "ADDRBWRADDRU7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU7" }, "ADDRBWRADDRU8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU8" }, "ADDRBWRADDRU9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU9" }, "ADDRBWRADDRU10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU10" }, "ADDRBWRADDRU11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU11" }, "ADDRBWRADDRU12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU12" }, "ADDRBWRADDRU13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU13" }, "ADDRBWRADDRU14": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ADDRBWRADDRU14" }, "ALMOSTEMPTY": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_ALMOSTEMPTY" }, "ALMOSTFULL": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_ALMOSTFULL" }, "CASCADEINA": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_CASCADEINA" }, "CASCADEINB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_CASCADEINB" }, "CASCADEOUTA": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_CASCADEOUTA" }, "CASCADEOUTB": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_CASCADEOUTB" }, "CLKARDCLKL": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_CLKARDCLKL" }, "CLKARDCLKU": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_CLKARDCLKU" }, "CLKBWRCLKL": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_CLKBWRCLKL" }, "CLKBWRCLKU": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_CLKBWRCLKU" }, "DBITERR": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DBITERR" }, "DIADI0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL0" }, "DIADI1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU0" }, "DIADI2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL1" }, "DIADI3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU1" }, "DIADI4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL2" }, "DIADI5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU2" }, "DIADI6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL3" }, "DIADI7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU3" }, "DIADI8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL4" }, "DIADI9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU4" }, "DIADI10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL5" }, "DIADI11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU5" }, "DIADI12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL6" }, "DIADI13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU6" }, "DIADI14": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL7" }, "DIADI15": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU7" }, "DIADI16": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL8" }, "DIADI17": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU8" }, "DIADI18": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL9" }, "DIADI19": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU9" }, "DIADI20": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL10" }, "DIADI21": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU10" }, "DIADI22": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL11" }, "DIADI23": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU11" }, "DIADI24": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL12" }, "DIADI25": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU12" }, "DIADI26": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL13" }, "DIADI27": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU13" }, "DIADI28": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL14" }, "DIADI29": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU14" }, "DIADI30": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIL15" }, "DIADI31": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIADIU15" }, "DIBDI0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL0" }, "DIBDI1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU0" }, "DIBDI2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL1" }, "DIBDI3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU1" }, "DIBDI4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL2" }, "DIBDI5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU2" }, "DIBDI6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL3" }, "DIBDI7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU3" }, "DIBDI8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL4" }, "DIBDI9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU4" }, "DIBDI10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL5" }, "DIBDI11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU5" }, "DIBDI12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL6" }, "DIBDI13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU6" }, "DIBDI14": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL7" }, "DIBDI15": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU7" }, "DIBDI16": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL8" }, "DIBDI17": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU8" }, "DIBDI18": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL9" }, "DIBDI19": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU9" }, "DIBDI20": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL10" }, "DIBDI21": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU10" }, "DIBDI22": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL11" }, "DIBDI23": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU11" }, "DIBDI24": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL12" }, "DIBDI25": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU12" }, "DIBDI26": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL13" }, "DIBDI27": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU13" }, "DIBDI28": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL14" }, "DIBDI29": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU14" }, "DIBDI30": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIL15" }, "DIBDI31": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIBDIU15" }, "DIPADIP0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIPADIPL0" }, "DIPADIP1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIPADIPU0" }, "DIPADIP2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIPADIPL1" }, "DIPADIP3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIPADIPU1" }, "DIPBDIP0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIPBDIPL0" }, "DIPBDIP1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIPBDIPU0" }, "DIPBDIP2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIPBDIPL1" }, "DIPBDIP3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_DIPBDIPU1" }, "DOADO0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL0" }, "DOADO1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU0" }, "DOADO2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL1" }, "DOADO3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU1" }, "DOADO4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL2" }, "DOADO5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU2" }, "DOADO6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL3" }, "DOADO7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU3" }, "DOADO8": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL4" }, "DOADO9": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU4" }, "DOADO10": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL5" }, "DOADO11": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU5" }, "DOADO12": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL6" }, "DOADO13": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU6" }, "DOADO14": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL7" }, "DOADO15": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU7" }, "DOADO16": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL8" }, "DOADO17": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU8" }, "DOADO18": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL9" }, "DOADO19": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU9" }, "DOADO20": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL10" }, "DOADO21": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU10" }, "DOADO22": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL11" }, "DOADO23": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU11" }, "DOADO24": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL12" }, "DOADO25": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU12" }, "DOADO26": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL13" }, "DOADO27": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU13" }, "DOADO28": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL14" }, "DOADO29": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU14" }, "DOADO30": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOL15" }, "DOADO31": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOADOU15" }, "DOBDO0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL0" }, "DOBDO1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU0" }, "DOBDO2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL1" }, "DOBDO3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU1" }, "DOBDO4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL2" }, "DOBDO5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU2" }, "DOBDO6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL3" }, "DOBDO7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU3" }, "DOBDO8": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL4" }, "DOBDO9": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU4" }, "DOBDO10": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL5" }, "DOBDO11": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU5" }, "DOBDO12": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL6" }, "DOBDO13": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU6" }, "DOBDO14": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL7" }, "DOBDO15": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU7" }, "DOBDO16": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL8" }, "DOBDO17": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU8" }, "DOBDO18": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL9" }, "DOBDO19": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU9" }, "DOBDO20": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL10" }, "DOBDO21": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU10" }, "DOBDO22": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL11" }, "DOBDO23": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU11" }, "DOBDO24": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL12" }, "DOBDO25": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU12" }, "DOBDO26": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL13" }, "DOBDO27": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU13" }, "DOBDO28": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL14" }, "DOBDO29": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU14" }, "DOBDO30": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOL15" }, "DOBDO31": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOBDOU15" }, "DOPADOP0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOPADOPL0" }, "DOPADOP1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOPADOPU0" }, "DOPADOP2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOPADOPL1" }, "DOPADOP3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOPADOPU1" }, "DOPBDOP0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOPBDOPL0" }, "DOPBDOP1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOPBDOPU0" }, "DOPBDOP2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOPBDOPL1" }, "DOPBDOP3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_DOPBDOPU1" }, "ECCPARITY0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_ECCPARITY0" }, "ECCPARITY1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_ECCPARITY1" }, "ECCPARITY2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_ECCPARITY2" }, "ECCPARITY3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_ECCPARITY3" }, "ECCPARITY4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_ECCPARITY4" }, "ECCPARITY5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_ECCPARITY5" }, "ECCPARITY6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_ECCPARITY6" }, "ECCPARITY7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_ECCPARITY7" }, "EMPTY": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_EMPTY" }, "ENARDENL": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ENARDENL" }, "ENARDENU": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ENARDENU" }, "ENBWRENL": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ENBWRENL" }, "ENBWRENU": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_ENBWRENU" }, "FULL": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_FULL" }, "INJECTDBITERR": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_INJECTDBITERR" }, "INJECTSBITERR": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_INJECTSBITERR" }, "RDCOUNT0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT0" }, "RDCOUNT1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT1" }, "RDCOUNT2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT2" }, "RDCOUNT3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT3" }, "RDCOUNT4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT4" }, "RDCOUNT5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT5" }, "RDCOUNT6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT6" }, "RDCOUNT7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT7" }, "RDCOUNT8": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT8" }, "RDCOUNT9": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT9" }, "RDCOUNT10": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT10" }, "RDCOUNT11": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT11" }, "RDCOUNT12": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDCOUNT12" }, "RDERR": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_RDERR" }, "REGCEAREGCEL": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_REGCEAREGCEL" }, "REGCEAREGCEU": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_REGCEAREGCEU" }, "REGCEBL": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_REGCEBL" }, "REGCEBU": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_REGCEBU" }, "REGCLKARDRCLKL": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_REGCLKARDRCLKL" }, "REGCLKARDRCLKU": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_REGCLKARDRCLKU" }, "REGCLKBL": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_REGCLKBL" }, "REGCLKBU": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_REGCLKBU" }, "RSTRAMARSTRAMLRST": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_RSTRAMARSTRAMLRST" }, "RSTRAMARSTRAMU": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_RSTRAMARSTRAMU" }, "RSTRAMBL": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_RSTRAMBL" }, "RSTRAMBU": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_RSTRAMBU" }, "RSTREGARSTREGL": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_RSTREGARSTREGL" }, "RSTREGARSTREGU": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_RSTREGARSTREGU" }, "RSTREGBL": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_RSTREGBL" }, "RSTREGBU": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_RSTREGBU" }, "SBITERR": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_SBITERR" }, "TSTBRAMRST": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTBRAMRST" }, "TSTCNT0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT0" }, "TSTCNT1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT1" }, "TSTCNT2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT2" }, "TSTCNT3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT3" }, "TSTCNT4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT4" }, "TSTCNT5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT5" }, "TSTCNT6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT6" }, "TSTCNT7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT7" }, "TSTCNT8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT8" }, "TSTCNT9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT9" }, "TSTCNT10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT10" }, "TSTCNT11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT11" }, "TSTCNT12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTCNT12" }, "TSTFLAGIN": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTFLAGIN" }, "TSTIN0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTIN0" }, "TSTIN1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTIN1" }, "TSTIN2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTIN2" }, "TSTIN3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTIN3" }, "TSTIN4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTIN4" }, "TSTOFF": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTOFF" }, "TSTOUT0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_TSTOUT0" }, "TSTOUT1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_TSTOUT1" }, "TSTOUT2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_TSTOUT2" }, "TSTOUT3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_TSTOUT3" }, "TSTOUT4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_TSTOUT4" }, "TSTRDCNTOFF": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDCNTOFF" }, "TSTRDOS0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS0" }, "TSTRDOS1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS1" }, "TSTRDOS2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS2" }, "TSTRDOS3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS3" }, "TSTRDOS4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS4" }, "TSTRDOS5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS5" }, "TSTRDOS6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS6" }, "TSTRDOS7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS7" }, "TSTRDOS8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS8" }, "TSTRDOS9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS9" }, "TSTRDOS10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS10" }, "TSTRDOS11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS11" }, "TSTRDOS12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTRDOS12" }, "TSTWRCNTOFF": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWRCNTOFF" }, "TSTWROS0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS0" }, "TSTWROS1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS1" }, "TSTWROS2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS2" }, "TSTWROS3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS3" }, "TSTWROS4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS4" }, "TSTWROS5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS5" }, "TSTWROS6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS6" }, "TSTWROS7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS7" }, "TSTWROS8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS8" }, "TSTWROS9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS9" }, "TSTWROS10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS10" }, "TSTWROS11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS11" }, "TSTWROS12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_TSTWROS12" }, "WEAL0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEAL0" }, "WEAL1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEAL1" }, "WEAL2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEAL2" }, "WEAL3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEAL3" }, "WEAU0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEAU0" }, "WEAU1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEAU1" }, "WEAU2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEAU2" }, "WEAU3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEAU3" }, "WEBWEL0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEL0" }, "WEBWEL1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEL1" }, "WEBWEL2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEL2" }, "WEBWEL3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEL3" }, "WEBWEL4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEL4" }, "WEBWEL5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEL5" }, "WEBWEL6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEL6" }, "WEBWEL7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEL7" }, "WEBWEU0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEU0" }, "WEBWEU1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEU1" }, "WEBWEU2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEU2" }, "WEBWEU3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEU3" }, "WEBWEU4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEU4" }, "WEBWEU5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEU5" }, "WEBWEU6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEU6" }, "WEBWEU7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_FIFO36_WEBWEU7" }, "WRCOUNT0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT0" }, "WRCOUNT1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT1" }, "WRCOUNT2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT2" }, "WRCOUNT3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT3" }, "WRCOUNT4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT4" }, "WRCOUNT5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT5" }, "WRCOUNT6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT6" }, "WRCOUNT7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT7" }, "WRCOUNT8": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT8" }, "WRCOUNT9": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT9" }, "WRCOUNT10": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT10" }, "WRCOUNT11": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT11" }, "WRCOUNT12": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRCOUNT12" }, "WRERR": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_FIFO36_WRERR" } }, "type": "RAMBFIFO36E1", "x_coord": 0, "y_coord": 0 }, { "name": "X0Y1", "prefix": "RAMB18", "site_pins": { "ADDRARDADDR0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR0" }, "ADDRARDADDR1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR1" }, "ADDRARDADDR2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR2" }, "ADDRARDADDR3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR3" }, "ADDRARDADDR4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR4" }, "ADDRARDADDR5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR5" }, "ADDRARDADDR6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR6" }, "ADDRARDADDR7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR7" }, "ADDRARDADDR8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR8" }, "ADDRARDADDR9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR9" }, "ADDRARDADDR10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR10" }, "ADDRARDADDR11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR11" }, "ADDRARDADDR12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR12" }, "ADDRARDADDR13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRARDADDR13" }, "ADDRATIEHIGH0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRATIEHIGH0" }, "ADDRATIEHIGH1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRATIEHIGH1" }, "ADDRBTIEHIGH0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBTIEHIGH0" }, "ADDRBTIEHIGH1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBTIEHIGH1" }, "ADDRBWRADDR0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR0" }, "ADDRBWRADDR1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR1" }, "ADDRBWRADDR2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR2" }, "ADDRBWRADDR3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR3" }, "ADDRBWRADDR4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR4" }, "ADDRBWRADDR5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR5" }, "ADDRBWRADDR6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR6" }, "ADDRBWRADDR7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR7" }, "ADDRBWRADDR8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR8" }, "ADDRBWRADDR9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR9" }, "ADDRBWRADDR10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR10" }, "ADDRBWRADDR11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR11" }, "ADDRBWRADDR12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR12" }, "ADDRBWRADDR13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ADDRBWRADDR13" }, "ALMOSTEMPTY": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_ALMOSTEMPTY" }, "ALMOSTFULL": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_ALMOSTFULL" }, "CLKARDCLK": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_CLKARDCLK" }, "CLKBWRCLK": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_CLKBWRCLK" }, "DIADI0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI0" }, "DIADI1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI1" }, "DIADI2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI2" }, "DIADI3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI3" }, "DIADI4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI4" }, "DIADI5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI5" }, "DIADI6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI6" }, "DIADI7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI7" }, "DIADI8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI8" }, "DIADI9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI9" }, "DIADI10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI10" }, "DIADI11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI11" }, "DIADI12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI12" }, "DIADI13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI13" }, "DIADI14": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI14" }, "DIADI15": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIADI15" }, "DIBDI0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI0" }, "DIBDI1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI1" }, "DIBDI2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI2" }, "DIBDI3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI3" }, "DIBDI4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI4" }, "DIBDI5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI5" }, "DIBDI6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI6" }, "DIBDI7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI7" }, "DIBDI8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI8" }, "DIBDI9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI9" }, "DIBDI10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI10" }, "DIBDI11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI11" }, "DIBDI12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI12" }, "DIBDI13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI13" }, "DIBDI14": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI14" }, "DIBDI15": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIBDI15" }, "DIPADIP0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIPADIP0" }, "DIPADIP1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIPADIP1" }, "DIPBDIP0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIPBDIP0" }, "DIPBDIP1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_DIPBDIP1" }, "DOADO0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO0" }, "DOADO1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO1" }, "DOADO2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO2" }, "DOADO3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO3" }, "DOADO4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO4" }, "DOADO5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO5" }, "DOADO6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO6" }, "DOADO7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO7" }, "DOADO8": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO8" }, "DOADO9": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO9" }, "DOADO10": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO10" }, "DOADO11": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO11" }, "DOADO12": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO12" }, "DOADO13": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO13" }, "DOADO14": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO14" }, "DOADO15": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOADO15" }, "DOBDO0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO0" }, "DOBDO1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO1" }, "DOBDO2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO2" }, "DOBDO3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO3" }, "DOBDO4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO4" }, "DOBDO5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO5" }, "DOBDO6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO6" }, "DOBDO7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO7" }, "DOBDO8": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO8" }, "DOBDO9": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO9" }, "DOBDO10": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO10" }, "DOBDO11": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO11" }, "DOBDO12": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO12" }, "DOBDO13": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO13" }, "DOBDO14": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO14" }, "DOBDO15": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOBDO15" }, "DOPADOP0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOPADOP0" }, "DOPADOP1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOPADOP1" }, "DOPBDOP0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOPBDOP0" }, "DOPBDOP1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_DOPBDOP1" }, "EMPTY": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_EMPTY" }, "ENARDEN": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ENARDEN" }, "ENBWREN": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_ENBWREN" }, "FULL": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_FULL" }, "RDCOUNT0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDCOUNT0" }, "RDCOUNT1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDCOUNT1" }, "RDCOUNT2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDCOUNT2" }, "RDCOUNT3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDCOUNT3" }, "RDCOUNT4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDCOUNT4" }, "RDCOUNT5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDCOUNT5" }, "RDCOUNT6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDCOUNT6" }, "RDCOUNT7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDCOUNT7" }, "RDCOUNT8": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDCOUNT8" }, "RDCOUNT9": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDCOUNT9" }, "RDCOUNT10": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDCOUNT10" }, "RDCOUNT11": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDCOUNT11" }, "RDERR": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_RDERR" }, "REGCEAREGCE": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_REGCEAREGCE" }, "REGCEB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_REGCEB" }, "REGCLKARDRCLK": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_REGCLKARDRCLK" }, "REGCLKB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_REGCLKB" }, "RSTRAMARSTRAM": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_RSTRAMARSTRAM" }, "RSTRAMB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_RSTRAMB" }, "RSTREGARSTREG": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_RSTREGARSTREG" }, "RSTREGB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_RSTREGB" }, "WEA0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_WEA0" }, "WEA1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_WEA1" }, "WEA2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_WEA2" }, "WEA3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_WEA3" }, "WEBWE0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_WEBWE0" }, "WEBWE1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_WEBWE1" }, "WEBWE2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_WEBWE2" }, "WEBWE3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_WEBWE3" }, "WEBWE4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_WEBWE4" }, "WEBWE5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_WEBWE5" }, "WEBWE6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_WEBWE6" }, "WEBWE7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "BRAM_RAMB18_WEBWE7" }, "WRCOUNT0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRCOUNT0" }, "WRCOUNT1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRCOUNT1" }, "WRCOUNT2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRCOUNT2" }, "WRCOUNT3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRCOUNT3" }, "WRCOUNT4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRCOUNT4" }, "WRCOUNT5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRCOUNT5" }, "WRCOUNT6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRCOUNT6" }, "WRCOUNT7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRCOUNT7" }, "WRCOUNT8": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRCOUNT8" }, "WRCOUNT9": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRCOUNT9" }, "WRCOUNT10": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRCOUNT10" }, "WRCOUNT11": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRCOUNT11" }, "WRERR": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "860.0625", "wire": "BRAM_RAMB18_WRERR" } }, "type": "RAMB18E1", "x_coord": 0, "y_coord": 1 } ], "tile_type": "BRAM_L", "wires": { "BRAM_ADDRARDADDRL0": null, "BRAM_ADDRARDADDRL1": null, "BRAM_ADDRARDADDRL2": null, "BRAM_ADDRARDADDRL3": null, "BRAM_ADDRARDADDRL4": null, "BRAM_ADDRARDADDRL5": null, "BRAM_ADDRARDADDRL6": null, "BRAM_ADDRARDADDRL7": null, "BRAM_ADDRARDADDRL8": null, "BRAM_ADDRARDADDRL9": null, "BRAM_ADDRARDADDRL10": null, "BRAM_ADDRARDADDRL11": null, "BRAM_ADDRARDADDRL12": null, "BRAM_ADDRARDADDRL13": null, "BRAM_ADDRARDADDRL14": null, "BRAM_ADDRARDADDRU0": null, "BRAM_ADDRARDADDRU1": null, "BRAM_ADDRARDADDRU2": null, "BRAM_ADDRARDADDRU3": null, "BRAM_ADDRARDADDRU4": null, "BRAM_ADDRARDADDRU5": null, "BRAM_ADDRARDADDRU6": null, "BRAM_ADDRARDADDRU7": null, "BRAM_ADDRARDADDRU8": null, "BRAM_ADDRARDADDRU9": null, "BRAM_ADDRARDADDRU10": null, "BRAM_ADDRARDADDRU11": null, "BRAM_ADDRARDADDRU12": null, "BRAM_ADDRARDADDRU13": null, "BRAM_ADDRARDADDRU14": null, "BRAM_ADDRBWRADDRL0": null, "BRAM_ADDRBWRADDRL1": null, "BRAM_ADDRBWRADDRL2": null, "BRAM_ADDRBWRADDRL3": null, "BRAM_ADDRBWRADDRL4": null, "BRAM_ADDRBWRADDRL5": null, "BRAM_ADDRBWRADDRL6": null, "BRAM_ADDRBWRADDRL7": null, "BRAM_ADDRBWRADDRL8": null, "BRAM_ADDRBWRADDRL9": null, "BRAM_ADDRBWRADDRL10": null, "BRAM_ADDRBWRADDRL11": null, "BRAM_ADDRBWRADDRL12": null, "BRAM_ADDRBWRADDRL13": null, "BRAM_ADDRBWRADDRL14": null, "BRAM_ADDRBWRADDRU0": null, "BRAM_ADDRBWRADDRU1": null, "BRAM_ADDRBWRADDRU2": null, "BRAM_ADDRBWRADDRU3": null, "BRAM_ADDRBWRADDRU4": null, "BRAM_ADDRBWRADDRU5": null, "BRAM_ADDRBWRADDRU6": null, "BRAM_ADDRBWRADDRU7": null, "BRAM_ADDRBWRADDRU8": null, "BRAM_ADDRBWRADDRU9": null, "BRAM_ADDRBWRADDRU10": null, "BRAM_ADDRBWRADDRU11": null, "BRAM_ADDRBWRADDRU12": null, "BRAM_ADDRBWRADDRU13": null, "BRAM_ADDRBWRADDRU14": null, "BRAM_BLOCK_OUTS_L_B0_0": null, "BRAM_BLOCK_OUTS_L_B0_1": null, "BRAM_BLOCK_OUTS_L_B0_2": null, "BRAM_BLOCK_OUTS_L_B0_3": null, "BRAM_BLOCK_OUTS_L_B0_4": null, "BRAM_BLOCK_OUTS_L_B1_0": null, "BRAM_BLOCK_OUTS_L_B1_1": null, "BRAM_BLOCK_OUTS_L_B1_2": null, "BRAM_BLOCK_OUTS_L_B1_3": null, "BRAM_BLOCK_OUTS_L_B1_4": null, "BRAM_BLOCK_OUTS_L_B2_0": null, "BRAM_BLOCK_OUTS_L_B2_1": null, "BRAM_BLOCK_OUTS_L_B2_2": null, "BRAM_BLOCK_OUTS_L_B2_3": null, "BRAM_BLOCK_OUTS_L_B2_4": null, "BRAM_BLOCK_OUTS_L_B3_0": null, "BRAM_BLOCK_OUTS_L_B3_1": null, "BRAM_BLOCK_OUTS_L_B3_2": null, "BRAM_BLOCK_OUTS_L_B3_3": null, "BRAM_BLOCK_OUTS_L_B3_4": null, "BRAM_BYP0_0": null, "BRAM_BYP0_1": null, "BRAM_BYP0_2": null, "BRAM_BYP0_3": null, "BRAM_BYP0_4": null, "BRAM_BYP1_0": null, "BRAM_BYP1_1": null, "BRAM_BYP1_2": null, "BRAM_BYP1_3": null, "BRAM_BYP1_4": null, "BRAM_BYP2_0": null, "BRAM_BYP2_1": null, "BRAM_BYP2_2": null, "BRAM_BYP2_3": null, "BRAM_BYP2_4": null, "BRAM_BYP3_0": null, "BRAM_BYP3_1": null, "BRAM_BYP3_2": null, "BRAM_BYP3_3": null, "BRAM_BYP3_4": null, "BRAM_BYP4_0": null, "BRAM_BYP4_1": null, "BRAM_BYP4_2": null, "BRAM_BYP4_3": null, "BRAM_BYP4_4": null, "BRAM_BYP5_0": null, "BRAM_BYP5_1": null, "BRAM_BYP5_2": null, "BRAM_BYP5_3": null, "BRAM_BYP5_4": null, "BRAM_BYP6_0": null, "BRAM_BYP6_1": null, "BRAM_BYP6_2": null, "BRAM_BYP6_3": null, "BRAM_BYP6_4": null, "BRAM_BYP7_0": null, "BRAM_BYP7_1": null, "BRAM_BYP7_2": null, "BRAM_BYP7_3": null, "BRAM_BYP7_4": null, "BRAM_CASCINBOT_ADDRARDADDRU0": null, "BRAM_CASCINBOT_ADDRARDADDRU1": null, "BRAM_CASCINBOT_ADDRARDADDRU2": null, "BRAM_CASCINBOT_ADDRARDADDRU3": null, "BRAM_CASCINBOT_ADDRARDADDRU4": null, "BRAM_CASCINBOT_ADDRARDADDRU5": null, "BRAM_CASCINBOT_ADDRARDADDRU6": null, "BRAM_CASCINBOT_ADDRARDADDRU7": null, "BRAM_CASCINBOT_ADDRARDADDRU8": null, "BRAM_CASCINBOT_ADDRARDADDRU9": null, "BRAM_CASCINBOT_ADDRARDADDRU10": null, "BRAM_CASCINBOT_ADDRARDADDRU11": null, "BRAM_CASCINBOT_ADDRARDADDRU12": null, "BRAM_CASCINBOT_ADDRARDADDRU13": null, "BRAM_CASCINBOT_ADDRARDADDRU14": null, "BRAM_CASCINBOT_ADDRBWRADDRU0": null, "BRAM_CASCINBOT_ADDRBWRADDRU1": null, "BRAM_CASCINBOT_ADDRBWRADDRU2": null, "BRAM_CASCINBOT_ADDRBWRADDRU3": null, "BRAM_CASCINBOT_ADDRBWRADDRU4": null, "BRAM_CASCINBOT_ADDRBWRADDRU5": null, "BRAM_CASCINBOT_ADDRBWRADDRU6": null, "BRAM_CASCINBOT_ADDRBWRADDRU7": null, "BRAM_CASCINBOT_ADDRBWRADDRU8": null, "BRAM_CASCINBOT_ADDRBWRADDRU9": null, "BRAM_CASCINBOT_ADDRBWRADDRU10": null, "BRAM_CASCINBOT_ADDRBWRADDRU11": null, "BRAM_CASCINBOT_ADDRBWRADDRU12": null, "BRAM_CASCINBOT_ADDRBWRADDRU13": null, "BRAM_CASCINBOT_ADDRBWRADDRU14": null, "BRAM_CASCINTOP_ADDRARDADDRU0": null, "BRAM_CASCINTOP_ADDRARDADDRU1": null, "BRAM_CASCINTOP_ADDRARDADDRU2": null, "BRAM_CASCINTOP_ADDRARDADDRU3": null, "BRAM_CASCINTOP_ADDRARDADDRU4": null, "BRAM_CASCINTOP_ADDRARDADDRU5": null, "BRAM_CASCINTOP_ADDRARDADDRU6": null, "BRAM_CASCINTOP_ADDRARDADDRU7": null, "BRAM_CASCINTOP_ADDRARDADDRU8": null, "BRAM_CASCINTOP_ADDRARDADDRU9": null, "BRAM_CASCINTOP_ADDRARDADDRU10": null, "BRAM_CASCINTOP_ADDRARDADDRU11": null, "BRAM_CASCINTOP_ADDRARDADDRU12": null, "BRAM_CASCINTOP_ADDRARDADDRU13": null, "BRAM_CASCINTOP_ADDRARDADDRU14": null, "BRAM_CASCINTOP_ADDRBWRADDRU0": null, "BRAM_CASCINTOP_ADDRBWRADDRU1": null, "BRAM_CASCINTOP_ADDRBWRADDRU2": null, "BRAM_CASCINTOP_ADDRBWRADDRU3": null, "BRAM_CASCINTOP_ADDRBWRADDRU4": null, "BRAM_CASCINTOP_ADDRBWRADDRU5": null, "BRAM_CASCINTOP_ADDRBWRADDRU6": null, "BRAM_CASCINTOP_ADDRBWRADDRU7": null, "BRAM_CASCINTOP_ADDRBWRADDRU8": null, "BRAM_CASCINTOP_ADDRBWRADDRU9": null, "BRAM_CASCINTOP_ADDRBWRADDRU10": null, "BRAM_CASCINTOP_ADDRBWRADDRU11": null, "BRAM_CASCINTOP_ADDRBWRADDRU12": null, "BRAM_CASCINTOP_ADDRBWRADDRU13": null, "BRAM_CASCINTOP_ADDRBWRADDRU14": null, "BRAM_CASCOUT_ADDRARDADDRU0": null, "BRAM_CASCOUT_ADDRARDADDRU1": null, "BRAM_CASCOUT_ADDRARDADDRU2": null, "BRAM_CASCOUT_ADDRARDADDRU3": null, "BRAM_CASCOUT_ADDRARDADDRU4": null, "BRAM_CASCOUT_ADDRARDADDRU5": null, "BRAM_CASCOUT_ADDRARDADDRU6": null, "BRAM_CASCOUT_ADDRARDADDRU7": null, "BRAM_CASCOUT_ADDRARDADDRU8": null, "BRAM_CASCOUT_ADDRARDADDRU9": null, "BRAM_CASCOUT_ADDRARDADDRU10": null, "BRAM_CASCOUT_ADDRARDADDRU11": null, "BRAM_CASCOUT_ADDRARDADDRU12": null, "BRAM_CASCOUT_ADDRARDADDRU13": null, "BRAM_CASCOUT_ADDRARDADDRU14": null, "BRAM_CASCOUT_ADDRBWRADDRU0": null, "BRAM_CASCOUT_ADDRBWRADDRU1": null, "BRAM_CASCOUT_ADDRBWRADDRU2": null, "BRAM_CASCOUT_ADDRBWRADDRU3": null, "BRAM_CASCOUT_ADDRBWRADDRU4": null, "BRAM_CASCOUT_ADDRBWRADDRU5": null, "BRAM_CASCOUT_ADDRBWRADDRU6": null, "BRAM_CASCOUT_ADDRBWRADDRU7": null, "BRAM_CASCOUT_ADDRBWRADDRU8": null, "BRAM_CASCOUT_ADDRBWRADDRU9": null, "BRAM_CASCOUT_ADDRBWRADDRU10": null, "BRAM_CASCOUT_ADDRBWRADDRU11": null, "BRAM_CASCOUT_ADDRBWRADDRU12": null, "BRAM_CASCOUT_ADDRBWRADDRU13": null, "BRAM_CASCOUT_ADDRBWRADDRU14": null, "BRAM_CLK0_0": null, "BRAM_CLK0_1": null, "BRAM_CLK0_2": null, "BRAM_CLK0_3": null, "BRAM_CLK0_4": null, "BRAM_CLK1_0": null, "BRAM_CLK1_1": null, "BRAM_CLK1_2": null, "BRAM_CLK1_3": null, "BRAM_CLK1_4": null, "BRAM_CTRL0_0": null, "BRAM_CTRL0_1": null, "BRAM_CTRL0_2": null, "BRAM_CTRL0_3": null, "BRAM_CTRL0_4": null, "BRAM_CTRL1_0": null, "BRAM_CTRL1_1": null, "BRAM_CTRL1_2": null, "BRAM_CTRL1_3": null, "BRAM_CTRL1_4": null, "BRAM_EE2A0_0": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A0_1": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A0_2": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A0_3": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A0_4": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A1_0": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A1_1": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A1_2": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A1_3": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A1_4": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A2_0": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A2_1": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A2_2": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A2_3": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A2_4": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A3_0": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A3_1": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A3_2": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A3_3": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2A3_4": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG0_0": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG0_1": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG0_2": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG0_3": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG0_4": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG1_0": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG1_1": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG1_2": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG1_3": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG1_4": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG2_0": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG2_1": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG2_2": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG2_3": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG2_4": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG3_0": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG3_1": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG3_2": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG3_3": { "cap": "60.430", "res": "268.920" }, "BRAM_EE2BEG3_4": { "cap": "60.430", "res": "268.920" }, "BRAM_EE4A0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4A3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4B3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4BEG3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_EE4C3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_EL1BEG0_0": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG0_1": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG0_2": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG0_3": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG0_4": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG1_0": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG1_1": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG1_2": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG1_3": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG1_4": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG2_0": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG2_1": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG2_2": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG2_3": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG2_4": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG3_0": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG3_1": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG3_2": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG3_3": { "cap": "64.292", "res": "268.920" }, "BRAM_EL1BEG3_4": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG0_0": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG0_1": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG0_2": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG0_3": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG0_4": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG1_0": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG1_1": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG1_2": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG1_3": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG1_4": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG2_0": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG2_1": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG2_2": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG2_3": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG2_4": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG3_0": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG3_1": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG3_2": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG3_3": { "cap": "64.292", "res": "268.920" }, "BRAM_ER1BEG3_4": { "cap": "64.292", "res": "268.920" }, "BRAM_FAN0_0": null, "BRAM_FAN0_1": null, "BRAM_FAN0_2": null, "BRAM_FAN0_3": null, "BRAM_FAN0_4": null, "BRAM_FAN1_0": null, "BRAM_FAN1_1": null, "BRAM_FAN1_2": null, "BRAM_FAN1_3": null, "BRAM_FAN1_4": null, "BRAM_FAN2_0": null, "BRAM_FAN2_1": null, "BRAM_FAN2_2": null, "BRAM_FAN2_3": null, "BRAM_FAN2_4": null, "BRAM_FAN3_0": null, "BRAM_FAN3_1": null, "BRAM_FAN3_2": null, "BRAM_FAN3_3": null, "BRAM_FAN3_4": null, "BRAM_FAN4_0": null, "BRAM_FAN4_1": null, "BRAM_FAN4_2": null, "BRAM_FAN4_3": null, "BRAM_FAN4_4": null, "BRAM_FAN5_0": null, "BRAM_FAN5_1": null, "BRAM_FAN5_2": null, "BRAM_FAN5_3": null, "BRAM_FAN5_4": null, "BRAM_FAN6_0": null, "BRAM_FAN6_1": null, "BRAM_FAN6_2": null, "BRAM_FAN6_3": null, "BRAM_FAN6_4": null, "BRAM_FAN7_0": null, "BRAM_FAN7_1": null, "BRAM_FAN7_2": null, "BRAM_FAN7_3": null, "BRAM_FAN7_4": null, "BRAM_FIFO18_ADDRARDADDR0": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR1": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR2": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR3": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR4": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR5": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR6": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR7": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR8": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR9": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR10": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR11": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR12": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO18_ADDRARDADDR13": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRATIEHIGH0": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRATIEHIGH1": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBTIEHIGH0": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBTIEHIGH1": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR0": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR1": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR2": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR3": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR4": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR5": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR6": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR7": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR8": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR9": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR10": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR11": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR12": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ADDRBWRADDR13": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO18_ALMOSTEMPTY": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_ALMOSTFULL": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_CLKARDCLK": { "cap": "22.000", "res": "0.000" }, "BRAM_FIFO18_CLKBWRCLK": { "cap": "22.000", "res": "0.000" }, "BRAM_FIFO18_DIADI0": { "cap": "23.600", "res": "0.000" }, "BRAM_FIFO18_DIADI1": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI2": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI3": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI4": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI5": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI6": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI7": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI8": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI9": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI10": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI11": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI12": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI13": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI14": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIADI15": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI0": { "cap": "24.900", "res": "0.000" }, "BRAM_FIFO18_DIBDI1": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI2": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI3": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI4": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI5": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI6": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI7": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI8": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI9": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI10": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI11": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI12": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI13": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI14": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIBDI15": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO18_DIPADIP0": { "cap": "28.600", "res": "0.000" }, "BRAM_FIFO18_DIPADIP1": { "cap": "28.600", "res": "0.000" }, "BRAM_FIFO18_DIPBDIP0": { "cap": "28.600", "res": "0.000" }, "BRAM_FIFO18_DIPBDIP1": { "cap": "28.600", "res": "0.000" }, "BRAM_FIFO18_DOADO0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO2": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO3": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO4": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO5": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO6": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO7": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO8": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO9": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO10": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO11": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO12": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO13": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO14": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOADO15": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO2": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO3": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO4": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO5": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO6": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO7": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO8": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO9": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO10": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO11": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO12": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO13": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO14": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOBDO15": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOPADOP0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOPADOP1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOPBDOP0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_DOPBDOP1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_EMPTY": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_ENARDEN": { "cap": "30.800", "res": "0.000" }, "BRAM_FIFO18_ENBWREN": { "cap": "30.800", "res": "0.000" }, "BRAM_FIFO18_FULL": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDCOUNT0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDCOUNT1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDCOUNT2": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDCOUNT3": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDCOUNT4": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDCOUNT5": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDCOUNT6": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDCOUNT7": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDCOUNT8": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDCOUNT9": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDCOUNT10": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDCOUNT11": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_RDERR": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_REGCEAREGCE": { "cap": "30.800", "res": "0.000" }, "BRAM_FIFO18_REGCEB": { "cap": "30.800", "res": "0.000" }, "BRAM_FIFO18_REGCLKARDRCLK": { "cap": "18.800", "res": "0.000" }, "BRAM_FIFO18_REGCLKB": { "cap": "18.800", "res": "0.000" }, "BRAM_FIFO18_RSTRAMARSTRAM": { "cap": "11.400", "res": "0.000" }, "BRAM_FIFO18_RSTRAMB": { "cap": "11.400", "res": "0.000" }, "BRAM_FIFO18_RSTREGARSTREG": { "cap": "11.400", "res": "0.000" }, "BRAM_FIFO18_RSTREGB": { "cap": "11.400", "res": "0.000" }, "BRAM_FIFO18_WEA0": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO18_WEA1": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO18_WEA2": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO18_WEA3": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO18_WEBWE0": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO18_WEBWE1": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO18_WEBWE2": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO18_WEBWE3": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO18_WEBWE4": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO18_WEBWE5": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO18_WEBWE6": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO18_WEBWE7": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO18_WRCOUNT0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_WRCOUNT1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_WRCOUNT2": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_WRCOUNT3": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_WRCOUNT4": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_WRCOUNT5": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_WRCOUNT6": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_WRCOUNT7": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_WRCOUNT8": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_WRCOUNT9": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_WRCOUNT10": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_WRCOUNT11": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO18_WRERR": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL0": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL1": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL2": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL3": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL4": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL5": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL6": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL7": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL8": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL9": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL10": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL11": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL12": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL13": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL14": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRL15": { "cap": "24.300", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU0": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU1": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU2": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU3": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU4": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU5": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU6": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU7": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU8": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU9": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU10": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU11": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU12": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU13": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRARDADDRU14": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL0": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL1": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL2": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL3": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL4": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL5": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL6": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL7": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL8": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL9": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL10": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL11": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL12": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL13": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL14": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRL15": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU0": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU1": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU2": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU3": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU4": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU5": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU6": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU7": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU8": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU9": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU10": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU11": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU12": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU13": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ADDRBWRADDRU14": { "cap": "22.200", "res": "0.000" }, "BRAM_FIFO36_ALMOSTEMPTY": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_ALMOSTFULL": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_CASCADEINA": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_CASCADEINB": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_CASCADEOUTA": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_CASCADEOUTA_1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_CASCADEOUTB": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_CASCADEOUTB_1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_CLKARDCLKL": { "cap": "22.000", "res": "0.000" }, "BRAM_FIFO36_CLKARDCLKU": { "cap": "22.000", "res": "0.000" }, "BRAM_FIFO36_CLKBWRCLKL": { "cap": "22.000", "res": "0.000" }, "BRAM_FIFO36_CLKBWRCLKU": { "cap": "22.000", "res": "0.000" }, "BRAM_FIFO36_DBITERR": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DIADIL0": { "cap": "31.700", "res": "0.000" }, "BRAM_FIFO36_DIADIL1": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL2": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL3": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL4": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL5": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL6": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL7": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL8": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL9": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL10": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL11": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL12": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL13": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL14": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIL15": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU0": { "cap": "31.700", "res": "0.000" }, "BRAM_FIFO36_DIADIU1": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU2": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU3": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU4": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU5": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU6": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU7": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU8": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU9": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU10": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU11": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU12": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU13": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU14": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIADIU15": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL0": { "cap": "33.200", "res": "0.000" }, "BRAM_FIFO36_DIBDIL1": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL2": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL3": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL4": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL5": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL6": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL7": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL8": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL9": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL10": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL11": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL12": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL13": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL14": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIL15": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU0": { "cap": "33.200", "res": "0.000" }, "BRAM_FIFO36_DIBDIU1": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU2": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU3": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU4": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU5": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU6": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU7": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU8": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU9": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU10": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU11": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU12": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU13": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU14": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIBDIU15": { "cap": "8.400", "res": "0.000" }, "BRAM_FIFO36_DIPADIPL0": { "cap": "28.600", "res": "0.000" }, "BRAM_FIFO36_DIPADIPL1": { "cap": "28.600", "res": "0.000" }, "BRAM_FIFO36_DIPADIPU0": { "cap": "28.600", "res": "0.000" }, "BRAM_FIFO36_DIPADIPU1": { "cap": "28.600", "res": "0.000" }, "BRAM_FIFO36_DIPBDIPL0": { "cap": "28.600", "res": "0.000" }, "BRAM_FIFO36_DIPBDIPL1": { "cap": "28.600", "res": "0.000" }, "BRAM_FIFO36_DIPBDIPU0": { "cap": "28.600", "res": "0.000" }, "BRAM_FIFO36_DIPBDIPU1": { "cap": "28.600", "res": "0.000" }, "BRAM_FIFO36_DOADOL0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL2": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL3": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL4": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL5": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL6": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL7": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL8": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL9": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL10": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL11": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL12": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL13": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL14": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOL15": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU2": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU3": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU4": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU5": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU6": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU7": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU8": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU9": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU10": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU11": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU12": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU13": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU14": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOADOU15": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL2": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL3": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL4": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL5": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL6": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL7": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL8": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL9": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL10": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL11": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL12": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL13": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL14": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOL15": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU2": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU3": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU4": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU5": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU6": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU7": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU8": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU9": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU10": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU11": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU12": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU13": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU14": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOBDOU15": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOPADOPL0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOPADOPL1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOPADOPU0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOPADOPU1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOPBDOPL0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOPBDOPL1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOPBDOPU0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_DOPBDOPU1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_ECCPARITY0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_ECCPARITY1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_ECCPARITY2": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_ECCPARITY3": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_ECCPARITY4": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_ECCPARITY5": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_ECCPARITY6": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_ECCPARITY7": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_EMPTY": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_ENARDENL": { "cap": "30.800", "res": "0.000" }, "BRAM_FIFO36_ENARDENU": { "cap": "30.800", "res": "0.000" }, "BRAM_FIFO36_ENBWRENL": { "cap": "30.800", "res": "0.000" }, "BRAM_FIFO36_ENBWRENU": { "cap": "30.800", "res": "0.000" }, "BRAM_FIFO36_FULL": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_INJECTDBITERR": { "cap": "16.300", "res": "0.000" }, "BRAM_FIFO36_INJECTSBITERR": { "cap": "16.300", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT2": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT3": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT4": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT5": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT6": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT7": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT8": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT9": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT10": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT11": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDCOUNT12": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_RDERR": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_REGCEAREGCEL": { "cap": "30.800", "res": "0.000" }, "BRAM_FIFO36_REGCEAREGCEU": { "cap": "30.800", "res": "0.000" }, "BRAM_FIFO36_REGCEBL": { "cap": "30.800", "res": "0.000" }, "BRAM_FIFO36_REGCEBU": { "cap": "30.800", "res": "0.000" }, "BRAM_FIFO36_REGCLKARDRCLKL": { "cap": "18.800", "res": "0.000" }, "BRAM_FIFO36_REGCLKARDRCLKU": { "cap": "18.800", "res": "0.000" }, "BRAM_FIFO36_REGCLKBL": { "cap": "18.800", "res": "0.000" }, "BRAM_FIFO36_REGCLKBU": { "cap": "18.800", "res": "0.000" }, "BRAM_FIFO36_RSTRAMARSTRAMLRST": { "cap": "11.400", "res": "0.000" }, "BRAM_FIFO36_RSTRAMARSTRAMU": { "cap": "11.400", "res": "0.000" }, "BRAM_FIFO36_RSTRAMBL": { "cap": "11.400", "res": "0.000" }, "BRAM_FIFO36_RSTRAMBU": { "cap": "11.400", "res": "0.000" }, "BRAM_FIFO36_RSTREGARSTREGL": { "cap": "11.400", "res": "0.000" }, "BRAM_FIFO36_RSTREGARSTREGU": { "cap": "11.400", "res": "0.000" }, "BRAM_FIFO36_RSTREGBL": { "cap": "11.400", "res": "0.000" }, "BRAM_FIFO36_RSTREGBU": { "cap": "11.400", "res": "0.000" }, "BRAM_FIFO36_SBITERR": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_TSTBRAMRST": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT0": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT1": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT2": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT3": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT4": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT5": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT6": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT7": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT8": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT9": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT10": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT11": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTCNT12": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTFLAGIN": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTIN0": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTIN1": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTIN2": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTIN3": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTIN4": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTOFF": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTOUT0": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTOUT1": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTOUT2": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTOUT3": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTOUT4": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDCNTOFF": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS0": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS1": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS2": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS3": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS4": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS5": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS6": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS7": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS8": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS9": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS10": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS11": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTRDOS12": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWRCNTOFF": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS0": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS1": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS2": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS3": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS4": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS5": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS6": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS7": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS8": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS9": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS10": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS11": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_TSTWROS12": { "cap": "50.000", "res": "0.000" }, "BRAM_FIFO36_WEAL0": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEAL1": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEAL2": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEAL3": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEAU0": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEAU1": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEAU2": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEAU3": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEL0": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEL1": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEL2": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEL3": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEL4": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEL5": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEL6": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEL7": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEU0": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEU1": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEU2": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEU3": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEU4": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEU5": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEU6": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WEBWEU7": { "cap": "29.200", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT0": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT1": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT2": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT3": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT4": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT5": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT6": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT7": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT8": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT9": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT10": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT11": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRCOUNT12": { "cap": "25.100", "res": "0.000" }, "BRAM_FIFO36_WRERR": { "cap": "25.100", "res": "0.000" }, "BRAM_IMUX0_0": null, "BRAM_IMUX0_1": null, "BRAM_IMUX0_2": null, "BRAM_IMUX0_3": null, "BRAM_IMUX0_4": null, "BRAM_IMUX0_UTURN_0": null, "BRAM_IMUX0_UTURN_1": null, "BRAM_IMUX0_UTURN_2": null, "BRAM_IMUX0_UTURN_3": null, "BRAM_IMUX0_UTURN_4": null, "BRAM_IMUX1_0": null, "BRAM_IMUX1_1": null, "BRAM_IMUX1_2": null, "BRAM_IMUX1_3": null, "BRAM_IMUX1_4": null, "BRAM_IMUX1_UTURN_0": null, "BRAM_IMUX1_UTURN_1": null, "BRAM_IMUX1_UTURN_2": null, "BRAM_IMUX1_UTURN_3": null, "BRAM_IMUX1_UTURN_4": null, "BRAM_IMUX2_0": null, "BRAM_IMUX2_1": null, "BRAM_IMUX2_2": null, "BRAM_IMUX2_3": null, "BRAM_IMUX2_4": null, "BRAM_IMUX2_UTURN_0": null, "BRAM_IMUX2_UTURN_1": null, "BRAM_IMUX2_UTURN_2": null, "BRAM_IMUX2_UTURN_3": null, "BRAM_IMUX2_UTURN_4": null, "BRAM_IMUX3_0": null, "BRAM_IMUX3_1": null, "BRAM_IMUX3_2": null, "BRAM_IMUX3_3": null, "BRAM_IMUX3_4": null, "BRAM_IMUX3_UTURN_0": null, "BRAM_IMUX3_UTURN_1": null, "BRAM_IMUX3_UTURN_2": null, "BRAM_IMUX3_UTURN_3": null, "BRAM_IMUX3_UTURN_4": null, "BRAM_IMUX4_0": null, "BRAM_IMUX4_1": null, "BRAM_IMUX4_2": null, "BRAM_IMUX4_3": null, "BRAM_IMUX4_4": null, "BRAM_IMUX4_UTURN_0": null, "BRAM_IMUX4_UTURN_1": null, "BRAM_IMUX4_UTURN_2": null, "BRAM_IMUX4_UTURN_3": null, "BRAM_IMUX4_UTURN_4": null, "BRAM_IMUX5_0": null, "BRAM_IMUX5_1": null, "BRAM_IMUX5_2": null, "BRAM_IMUX5_3": null, "BRAM_IMUX5_4": null, "BRAM_IMUX5_UTURN_0": null, "BRAM_IMUX5_UTURN_1": null, "BRAM_IMUX5_UTURN_2": null, "BRAM_IMUX5_UTURN_3": null, "BRAM_IMUX5_UTURN_4": null, "BRAM_IMUX6_0": null, "BRAM_IMUX6_1": null, "BRAM_IMUX6_2": null, "BRAM_IMUX6_3": null, "BRAM_IMUX6_4": null, "BRAM_IMUX6_UTURN_0": null, "BRAM_IMUX6_UTURN_1": null, "BRAM_IMUX6_UTURN_2": null, "BRAM_IMUX6_UTURN_3": null, "BRAM_IMUX6_UTURN_4": null, "BRAM_IMUX7_0": null, "BRAM_IMUX7_1": null, "BRAM_IMUX7_2": null, "BRAM_IMUX7_3": null, "BRAM_IMUX7_4": null, "BRAM_IMUX7_UTURN_0": null, "BRAM_IMUX7_UTURN_1": null, "BRAM_IMUX7_UTURN_2": null, "BRAM_IMUX7_UTURN_3": null, "BRAM_IMUX7_UTURN_4": null, "BRAM_IMUX8_0": null, "BRAM_IMUX8_1": null, "BRAM_IMUX8_2": null, "BRAM_IMUX8_3": null, "BRAM_IMUX8_4": null, "BRAM_IMUX8_UTURN_0": null, "BRAM_IMUX8_UTURN_1": null, "BRAM_IMUX8_UTURN_2": null, "BRAM_IMUX8_UTURN_3": null, "BRAM_IMUX8_UTURN_4": null, "BRAM_IMUX9_0": null, "BRAM_IMUX9_1": null, "BRAM_IMUX9_2": null, "BRAM_IMUX9_3": null, "BRAM_IMUX9_4": null, "BRAM_IMUX9_UTURN_0": null, "BRAM_IMUX9_UTURN_1": null, "BRAM_IMUX9_UTURN_2": null, "BRAM_IMUX9_UTURN_3": null, "BRAM_IMUX9_UTURN_4": null, "BRAM_IMUX10_0": null, "BRAM_IMUX10_1": null, "BRAM_IMUX10_2": null, "BRAM_IMUX10_3": null, "BRAM_IMUX10_4": null, "BRAM_IMUX10_UTURN_0": null, "BRAM_IMUX10_UTURN_1": null, "BRAM_IMUX10_UTURN_2": null, "BRAM_IMUX10_UTURN_3": null, "BRAM_IMUX10_UTURN_4": null, "BRAM_IMUX11_0": null, "BRAM_IMUX11_1": null, "BRAM_IMUX11_2": null, "BRAM_IMUX11_3": null, "BRAM_IMUX11_4": null, "BRAM_IMUX11_UTURN_0": null, "BRAM_IMUX11_UTURN_1": null, "BRAM_IMUX11_UTURN_2": null, "BRAM_IMUX11_UTURN_3": null, "BRAM_IMUX11_UTURN_4": null, "BRAM_IMUX12_0": null, "BRAM_IMUX12_1": null, "BRAM_IMUX12_2": null, "BRAM_IMUX12_3": null, "BRAM_IMUX12_4": null, "BRAM_IMUX12_UTURN_0": null, "BRAM_IMUX12_UTURN_1": null, "BRAM_IMUX12_UTURN_2": null, "BRAM_IMUX12_UTURN_3": null, "BRAM_IMUX12_UTURN_4": null, "BRAM_IMUX13_0": null, "BRAM_IMUX13_1": null, "BRAM_IMUX13_2": null, "BRAM_IMUX13_3": null, "BRAM_IMUX13_4": null, "BRAM_IMUX13_UTURN_0": null, "BRAM_IMUX13_UTURN_1": null, "BRAM_IMUX13_UTURN_2": null, "BRAM_IMUX13_UTURN_3": null, "BRAM_IMUX13_UTURN_4": null, "BRAM_IMUX14_0": null, "BRAM_IMUX14_1": null, "BRAM_IMUX14_2": null, "BRAM_IMUX14_3": null, "BRAM_IMUX14_4": null, "BRAM_IMUX14_UTURN_0": null, "BRAM_IMUX14_UTURN_1": null, "BRAM_IMUX14_UTURN_2": null, "BRAM_IMUX14_UTURN_3": null, "BRAM_IMUX14_UTURN_4": null, "BRAM_IMUX15_0": null, "BRAM_IMUX15_1": null, "BRAM_IMUX15_2": null, "BRAM_IMUX15_3": null, "BRAM_IMUX15_4": null, "BRAM_IMUX15_UTURN_0": null, "BRAM_IMUX15_UTURN_1": null, "BRAM_IMUX15_UTURN_2": null, "BRAM_IMUX15_UTURN_3": null, "BRAM_IMUX15_UTURN_4": null, "BRAM_IMUX16_0": null, "BRAM_IMUX16_1": null, "BRAM_IMUX16_2": null, "BRAM_IMUX16_3": null, "BRAM_IMUX16_4": null, "BRAM_IMUX16_UTURN_0": null, "BRAM_IMUX16_UTURN_1": null, "BRAM_IMUX16_UTURN_2": null, "BRAM_IMUX16_UTURN_3": null, "BRAM_IMUX16_UTURN_4": null, "BRAM_IMUX17_0": null, "BRAM_IMUX17_1": null, "BRAM_IMUX17_2": null, "BRAM_IMUX17_3": null, "BRAM_IMUX17_4": null, "BRAM_IMUX17_UTURN_0": null, "BRAM_IMUX17_UTURN_1": null, "BRAM_IMUX17_UTURN_2": null, "BRAM_IMUX17_UTURN_3": null, "BRAM_IMUX17_UTURN_4": null, "BRAM_IMUX18_0": null, "BRAM_IMUX18_1": null, "BRAM_IMUX18_2": null, "BRAM_IMUX18_3": null, "BRAM_IMUX18_4": null, "BRAM_IMUX18_UTURN_0": null, "BRAM_IMUX18_UTURN_1": null, "BRAM_IMUX18_UTURN_2": null, "BRAM_IMUX18_UTURN_3": null, "BRAM_IMUX18_UTURN_4": null, "BRAM_IMUX19_0": null, "BRAM_IMUX19_1": null, "BRAM_IMUX19_2": null, "BRAM_IMUX19_3": null, "BRAM_IMUX19_4": null, "BRAM_IMUX19_UTURN_0": null, "BRAM_IMUX19_UTURN_1": null, "BRAM_IMUX19_UTURN_2": null, "BRAM_IMUX19_UTURN_3": null, "BRAM_IMUX19_UTURN_4": null, "BRAM_IMUX20_0": null, "BRAM_IMUX20_1": null, "BRAM_IMUX20_2": null, "BRAM_IMUX20_3": null, "BRAM_IMUX20_4": null, "BRAM_IMUX20_UTURN_0": null, "BRAM_IMUX20_UTURN_1": null, "BRAM_IMUX20_UTURN_2": null, "BRAM_IMUX20_UTURN_3": null, "BRAM_IMUX20_UTURN_4": null, "BRAM_IMUX21_0": null, "BRAM_IMUX21_1": null, "BRAM_IMUX21_2": null, "BRAM_IMUX21_3": null, "BRAM_IMUX21_4": null, "BRAM_IMUX21_UTURN_0": null, "BRAM_IMUX21_UTURN_1": null, "BRAM_IMUX21_UTURN_2": null, "BRAM_IMUX21_UTURN_3": null, "BRAM_IMUX21_UTURN_4": null, "BRAM_IMUX22_0": null, "BRAM_IMUX22_1": null, "BRAM_IMUX22_2": null, "BRAM_IMUX22_3": null, "BRAM_IMUX22_4": null, "BRAM_IMUX22_UTURN_0": null, "BRAM_IMUX22_UTURN_1": null, "BRAM_IMUX22_UTURN_2": null, "BRAM_IMUX22_UTURN_3": null, "BRAM_IMUX22_UTURN_4": null, "BRAM_IMUX23_0": null, "BRAM_IMUX23_1": null, "BRAM_IMUX23_2": null, "BRAM_IMUX23_3": null, "BRAM_IMUX23_4": null, "BRAM_IMUX23_UTURN_0": null, "BRAM_IMUX23_UTURN_1": null, "BRAM_IMUX23_UTURN_2": null, "BRAM_IMUX23_UTURN_3": null, "BRAM_IMUX23_UTURN_4": null, "BRAM_IMUX24_0": null, "BRAM_IMUX24_1": null, "BRAM_IMUX24_2": null, "BRAM_IMUX24_3": null, "BRAM_IMUX24_4": null, "BRAM_IMUX24_UTURN_0": null, "BRAM_IMUX24_UTURN_1": null, "BRAM_IMUX24_UTURN_2": null, "BRAM_IMUX24_UTURN_3": null, "BRAM_IMUX24_UTURN_4": null, "BRAM_IMUX25_0": null, "BRAM_IMUX25_1": null, "BRAM_IMUX25_2": null, "BRAM_IMUX25_3": null, "BRAM_IMUX25_4": null, "BRAM_IMUX25_UTURN_0": null, "BRAM_IMUX25_UTURN_1": null, "BRAM_IMUX25_UTURN_2": null, "BRAM_IMUX25_UTURN_3": null, "BRAM_IMUX25_UTURN_4": null, "BRAM_IMUX26_0": null, "BRAM_IMUX26_1": null, "BRAM_IMUX26_2": null, "BRAM_IMUX26_3": null, "BRAM_IMUX26_4": null, "BRAM_IMUX26_UTURN_0": null, "BRAM_IMUX26_UTURN_1": null, "BRAM_IMUX26_UTURN_2": null, "BRAM_IMUX26_UTURN_3": null, "BRAM_IMUX26_UTURN_4": null, "BRAM_IMUX27_0": null, "BRAM_IMUX27_1": null, "BRAM_IMUX27_2": null, "BRAM_IMUX27_3": null, "BRAM_IMUX27_4": null, "BRAM_IMUX27_UTURN_0": null, "BRAM_IMUX27_UTURN_1": null, "BRAM_IMUX27_UTURN_2": null, "BRAM_IMUX27_UTURN_3": null, "BRAM_IMUX27_UTURN_4": null, "BRAM_IMUX28_0": null, "BRAM_IMUX28_1": null, "BRAM_IMUX28_2": null, "BRAM_IMUX28_3": null, "BRAM_IMUX28_4": null, "BRAM_IMUX28_UTURN_0": null, "BRAM_IMUX28_UTURN_1": null, "BRAM_IMUX28_UTURN_2": null, "BRAM_IMUX28_UTURN_3": null, "BRAM_IMUX28_UTURN_4": null, "BRAM_IMUX29_0": null, "BRAM_IMUX29_1": null, "BRAM_IMUX29_2": null, "BRAM_IMUX29_3": null, "BRAM_IMUX29_4": null, "BRAM_IMUX29_UTURN_0": null, "BRAM_IMUX29_UTURN_1": null, "BRAM_IMUX29_UTURN_2": null, "BRAM_IMUX29_UTURN_3": null, "BRAM_IMUX29_UTURN_4": null, "BRAM_IMUX30_0": null, "BRAM_IMUX30_1": null, "BRAM_IMUX30_2": null, "BRAM_IMUX30_3": null, "BRAM_IMUX30_4": null, "BRAM_IMUX30_UTURN_0": null, "BRAM_IMUX30_UTURN_1": null, "BRAM_IMUX30_UTURN_2": null, "BRAM_IMUX30_UTURN_3": null, "BRAM_IMUX30_UTURN_4": null, "BRAM_IMUX31_0": null, "BRAM_IMUX31_1": null, "BRAM_IMUX31_2": null, "BRAM_IMUX31_3": null, "BRAM_IMUX31_4": null, "BRAM_IMUX31_UTURN_0": null, "BRAM_IMUX31_UTURN_1": null, "BRAM_IMUX31_UTURN_2": null, "BRAM_IMUX31_UTURN_3": null, "BRAM_IMUX31_UTURN_4": null, "BRAM_IMUX32_0": null, "BRAM_IMUX32_1": null, "BRAM_IMUX32_2": null, "BRAM_IMUX32_3": null, "BRAM_IMUX32_4": null, "BRAM_IMUX32_UTURN_0": null, "BRAM_IMUX32_UTURN_1": null, "BRAM_IMUX32_UTURN_2": null, "BRAM_IMUX32_UTURN_3": null, "BRAM_IMUX32_UTURN_4": null, "BRAM_IMUX33_0": null, "BRAM_IMUX33_1": null, "BRAM_IMUX33_2": null, "BRAM_IMUX33_3": null, "BRAM_IMUX33_4": null, "BRAM_IMUX33_UTURN_0": null, "BRAM_IMUX33_UTURN_1": null, "BRAM_IMUX33_UTURN_2": null, "BRAM_IMUX33_UTURN_3": null, "BRAM_IMUX33_UTURN_4": null, "BRAM_IMUX34_0": null, "BRAM_IMUX34_1": null, "BRAM_IMUX34_2": null, "BRAM_IMUX34_3": null, "BRAM_IMUX34_4": null, "BRAM_IMUX34_UTURN_0": null, "BRAM_IMUX34_UTURN_1": null, "BRAM_IMUX34_UTURN_2": null, "BRAM_IMUX34_UTURN_3": null, "BRAM_IMUX34_UTURN_4": null, "BRAM_IMUX35_0": null, "BRAM_IMUX35_1": null, "BRAM_IMUX35_2": null, "BRAM_IMUX35_3": null, "BRAM_IMUX35_4": null, "BRAM_IMUX35_UTURN_0": null, "BRAM_IMUX35_UTURN_1": null, "BRAM_IMUX35_UTURN_2": null, "BRAM_IMUX35_UTURN_3": null, "BRAM_IMUX35_UTURN_4": null, "BRAM_IMUX36_0": null, "BRAM_IMUX36_1": null, "BRAM_IMUX36_2": null, "BRAM_IMUX36_3": null, "BRAM_IMUX36_4": null, "BRAM_IMUX36_UTURN_0": null, "BRAM_IMUX36_UTURN_1": null, "BRAM_IMUX36_UTURN_2": null, "BRAM_IMUX36_UTURN_3": null, "BRAM_IMUX36_UTURN_4": null, "BRAM_IMUX37_0": null, "BRAM_IMUX37_1": null, "BRAM_IMUX37_2": null, "BRAM_IMUX37_3": null, "BRAM_IMUX37_4": null, "BRAM_IMUX37_UTURN_0": null, "BRAM_IMUX37_UTURN_1": null, "BRAM_IMUX37_UTURN_2": null, "BRAM_IMUX37_UTURN_3": null, "BRAM_IMUX37_UTURN_4": null, "BRAM_IMUX38_0": null, "BRAM_IMUX38_1": null, "BRAM_IMUX38_2": null, "BRAM_IMUX38_3": null, "BRAM_IMUX38_4": null, "BRAM_IMUX38_UTURN_0": null, "BRAM_IMUX38_UTURN_1": null, "BRAM_IMUX38_UTURN_2": null, "BRAM_IMUX38_UTURN_3": null, "BRAM_IMUX38_UTURN_4": null, "BRAM_IMUX39_0": null, "BRAM_IMUX39_1": null, "BRAM_IMUX39_2": null, "BRAM_IMUX39_3": null, "BRAM_IMUX39_4": null, "BRAM_IMUX39_UTURN_0": null, "BRAM_IMUX39_UTURN_1": null, "BRAM_IMUX39_UTURN_2": null, "BRAM_IMUX39_UTURN_3": null, "BRAM_IMUX39_UTURN_4": null, "BRAM_IMUX40_0": null, "BRAM_IMUX40_1": null, "BRAM_IMUX40_2": null, "BRAM_IMUX40_3": null, "BRAM_IMUX40_4": null, "BRAM_IMUX40_UTURN_0": null, "BRAM_IMUX40_UTURN_1": null, "BRAM_IMUX40_UTURN_2": null, "BRAM_IMUX40_UTURN_3": null, "BRAM_IMUX40_UTURN_4": null, "BRAM_IMUX41_0": null, "BRAM_IMUX41_1": null, "BRAM_IMUX41_2": null, "BRAM_IMUX41_3": null, "BRAM_IMUX41_4": null, "BRAM_IMUX41_UTURN_0": null, "BRAM_IMUX41_UTURN_1": null, "BRAM_IMUX41_UTURN_2": null, "BRAM_IMUX41_UTURN_3": null, "BRAM_IMUX41_UTURN_4": null, "BRAM_IMUX42_0": null, "BRAM_IMUX42_1": null, "BRAM_IMUX42_2": null, "BRAM_IMUX42_3": null, "BRAM_IMUX42_4": null, "BRAM_IMUX42_UTURN_0": null, "BRAM_IMUX42_UTURN_1": null, "BRAM_IMUX42_UTURN_2": null, "BRAM_IMUX42_UTURN_3": null, "BRAM_IMUX42_UTURN_4": null, "BRAM_IMUX43_0": null, "BRAM_IMUX43_1": null, "BRAM_IMUX43_2": null, "BRAM_IMUX43_3": null, "BRAM_IMUX43_4": null, "BRAM_IMUX43_UTURN_0": null, "BRAM_IMUX43_UTURN_1": null, "BRAM_IMUX43_UTURN_2": null, "BRAM_IMUX43_UTURN_3": null, "BRAM_IMUX43_UTURN_4": null, "BRAM_IMUX44_0": null, "BRAM_IMUX44_1": null, "BRAM_IMUX44_2": null, "BRAM_IMUX44_3": null, "BRAM_IMUX44_4": null, "BRAM_IMUX44_UTURN_0": null, "BRAM_IMUX44_UTURN_1": null, "BRAM_IMUX44_UTURN_2": null, "BRAM_IMUX44_UTURN_3": null, "BRAM_IMUX44_UTURN_4": null, "BRAM_IMUX45_0": null, "BRAM_IMUX45_1": null, "BRAM_IMUX45_2": null, "BRAM_IMUX45_3": null, "BRAM_IMUX45_4": null, "BRAM_IMUX45_UTURN_0": null, "BRAM_IMUX45_UTURN_1": null, "BRAM_IMUX45_UTURN_2": null, "BRAM_IMUX45_UTURN_3": null, "BRAM_IMUX45_UTURN_4": null, "BRAM_IMUX46_0": null, "BRAM_IMUX46_1": null, "BRAM_IMUX46_2": null, "BRAM_IMUX46_3": null, "BRAM_IMUX46_4": null, "BRAM_IMUX46_UTURN_0": null, "BRAM_IMUX46_UTURN_1": null, "BRAM_IMUX46_UTURN_2": null, "BRAM_IMUX46_UTURN_3": null, "BRAM_IMUX46_UTURN_4": null, "BRAM_IMUX47_0": null, "BRAM_IMUX47_1": null, "BRAM_IMUX47_2": null, "BRAM_IMUX47_3": null, "BRAM_IMUX47_4": null, "BRAM_IMUX47_UTURN_0": null, "BRAM_IMUX47_UTURN_1": null, "BRAM_IMUX47_UTURN_2": null, "BRAM_IMUX47_UTURN_3": null, "BRAM_IMUX47_UTURN_4": null, "BRAM_IMUX_ADDRARDADDRL0": null, "BRAM_IMUX_ADDRARDADDRL1": null, "BRAM_IMUX_ADDRARDADDRL2": null, "BRAM_IMUX_ADDRARDADDRL3": null, "BRAM_IMUX_ADDRARDADDRL4": null, "BRAM_IMUX_ADDRARDADDRL5": null, "BRAM_IMUX_ADDRARDADDRL6": null, "BRAM_IMUX_ADDRARDADDRL7": null, "BRAM_IMUX_ADDRARDADDRL8": null, "BRAM_IMUX_ADDRARDADDRL9": null, "BRAM_IMUX_ADDRARDADDRL10": null, "BRAM_IMUX_ADDRARDADDRL11": null, "BRAM_IMUX_ADDRARDADDRL12": null, "BRAM_IMUX_ADDRARDADDRL13": null, "BRAM_IMUX_ADDRARDADDRL14": null, "BRAM_IMUX_ADDRARDADDRL15": null, "BRAM_IMUX_ADDRARDADDRU0": null, "BRAM_IMUX_ADDRARDADDRU1": null, "BRAM_IMUX_ADDRARDADDRU2": null, "BRAM_IMUX_ADDRARDADDRU3": null, "BRAM_IMUX_ADDRARDADDRU4": null, "BRAM_IMUX_ADDRARDADDRU5": null, "BRAM_IMUX_ADDRARDADDRU6": null, "BRAM_IMUX_ADDRARDADDRU7": null, "BRAM_IMUX_ADDRARDADDRU8": null, "BRAM_IMUX_ADDRARDADDRU9": null, "BRAM_IMUX_ADDRARDADDRU10": null, "BRAM_IMUX_ADDRARDADDRU11": null, "BRAM_IMUX_ADDRARDADDRU12": null, "BRAM_IMUX_ADDRARDADDRU13": null, "BRAM_IMUX_ADDRARDADDRU14": null, "BRAM_IMUX_ADDRBWRADDRL0": null, "BRAM_IMUX_ADDRBWRADDRL1": null, "BRAM_IMUX_ADDRBWRADDRL2": null, "BRAM_IMUX_ADDRBWRADDRL3": null, "BRAM_IMUX_ADDRBWRADDRL4": null, "BRAM_IMUX_ADDRBWRADDRL5": null, "BRAM_IMUX_ADDRBWRADDRL6": null, "BRAM_IMUX_ADDRBWRADDRL7": null, "BRAM_IMUX_ADDRBWRADDRL8": null, "BRAM_IMUX_ADDRBWRADDRL9": null, "BRAM_IMUX_ADDRBWRADDRL10": null, "BRAM_IMUX_ADDRBWRADDRL11": null, "BRAM_IMUX_ADDRBWRADDRL12": null, "BRAM_IMUX_ADDRBWRADDRL13": null, "BRAM_IMUX_ADDRBWRADDRL14": null, "BRAM_IMUX_ADDRBWRADDRL15": null, "BRAM_IMUX_ADDRBWRADDRU0": null, "BRAM_IMUX_ADDRBWRADDRU1": null, "BRAM_IMUX_ADDRBWRADDRU2": null, "BRAM_IMUX_ADDRBWRADDRU3": null, "BRAM_IMUX_ADDRBWRADDRU4": null, "BRAM_IMUX_ADDRBWRADDRU5": null, "BRAM_IMUX_ADDRBWRADDRU6": null, "BRAM_IMUX_ADDRBWRADDRU7": null, "BRAM_IMUX_ADDRBWRADDRU8": null, "BRAM_IMUX_ADDRBWRADDRU9": null, "BRAM_IMUX_ADDRBWRADDRU10": null, "BRAM_IMUX_ADDRBWRADDRU11": null, "BRAM_IMUX_ADDRBWRADDRU12": null, "BRAM_IMUX_ADDRBWRADDRU13": null, "BRAM_IMUX_ADDRBWRADDRU14": null, "BRAM_LH1_0": null, "BRAM_LH1_1": null, "BRAM_LH1_2": null, "BRAM_LH1_3": null, "BRAM_LH1_4": null, "BRAM_LH2_0": null, "BRAM_LH2_1": null, "BRAM_LH2_2": null, "BRAM_LH2_3": null, "BRAM_LH2_4": null, "BRAM_LH3_0": null, "BRAM_LH3_1": null, "BRAM_LH3_2": null, "BRAM_LH3_3": null, "BRAM_LH3_4": null, "BRAM_LH4_0": null, "BRAM_LH4_1": null, "BRAM_LH4_2": null, "BRAM_LH4_3": null, "BRAM_LH4_4": null, "BRAM_LH5_0": { "cap": "51.040", "res": "12.860" }, "BRAM_LH5_1": { "cap": "51.040", "res": "12.860" }, "BRAM_LH5_2": { "cap": "51.040", "res": "12.860" }, "BRAM_LH5_3": { "cap": "51.040", "res": "12.860" }, "BRAM_LH5_4": { "cap": "51.040", "res": "12.860" }, "BRAM_LH6_0": { "cap": "51.040", "res": "12.860" }, "BRAM_LH6_1": { "cap": "51.040", "res": "12.860" }, "BRAM_LH6_2": { "cap": "51.040", "res": "12.860" }, "BRAM_LH6_3": { "cap": "51.040", "res": "12.860" }, "BRAM_LH6_4": { "cap": "51.040", "res": "12.860" }, "BRAM_LH7_0": { "cap": "51.040", "res": "12.860" }, "BRAM_LH7_1": { "cap": "51.040", "res": "12.860" }, "BRAM_LH7_2": { "cap": "51.040", "res": "12.860" }, "BRAM_LH7_3": { "cap": "51.040", "res": "12.860" }, "BRAM_LH7_4": { "cap": "51.040", "res": "12.860" }, "BRAM_LH8_0": { "cap": "51.040", "res": "12.860" }, "BRAM_LH8_1": { "cap": "51.040", "res": "12.860" }, "BRAM_LH8_2": { "cap": "51.040", "res": "12.860" }, "BRAM_LH8_3": { "cap": "51.040", "res": "12.860" }, "BRAM_LH8_4": { "cap": "51.040", "res": "12.860" }, "BRAM_LH9_0": { "cap": "51.040", "res": "12.860" }, "BRAM_LH9_1": { "cap": "51.040", "res": "12.860" }, "BRAM_LH9_2": { "cap": "51.040", "res": "12.860" }, "BRAM_LH9_3": { "cap": "51.040", "res": "12.860" }, "BRAM_LH9_4": { "cap": "51.040", "res": "12.860" }, "BRAM_LH10_0": { "cap": "51.040", "res": "12.860" }, "BRAM_LH10_1": { "cap": "51.040", "res": "12.860" }, "BRAM_LH10_2": { "cap": "51.040", "res": "12.860" }, "BRAM_LH10_3": { "cap": "51.040", "res": "12.860" }, "BRAM_LH10_4": { "cap": "51.040", "res": "12.860" }, "BRAM_LH11_0": { "cap": "51.040", "res": "12.860" }, "BRAM_LH11_1": { "cap": "51.040", "res": "12.860" }, "BRAM_LH11_2": { "cap": "51.040", "res": "12.860" }, "BRAM_LH11_3": { "cap": "51.040", "res": "12.860" }, "BRAM_LH11_4": { "cap": "51.040", "res": "12.860" }, "BRAM_LH12_0": { "cap": "51.040", "res": "12.860" }, "BRAM_LH12_1": { "cap": "51.040", "res": "12.860" }, "BRAM_LH12_2": { "cap": "51.040", "res": "12.860" }, "BRAM_LH12_3": { "cap": "51.040", "res": "12.860" }, "BRAM_LH12_4": { "cap": "51.040", "res": "12.860" }, "BRAM_LOGIC_OUTS_B0_0": null, "BRAM_LOGIC_OUTS_B0_1": null, "BRAM_LOGIC_OUTS_B0_2": null, "BRAM_LOGIC_OUTS_B0_3": null, "BRAM_LOGIC_OUTS_B0_4": null, "BRAM_LOGIC_OUTS_B1_0": null, "BRAM_LOGIC_OUTS_B1_1": null, "BRAM_LOGIC_OUTS_B1_2": null, "BRAM_LOGIC_OUTS_B1_3": null, "BRAM_LOGIC_OUTS_B1_4": null, "BRAM_LOGIC_OUTS_B2_0": null, "BRAM_LOGIC_OUTS_B2_1": null, "BRAM_LOGIC_OUTS_B2_2": null, "BRAM_LOGIC_OUTS_B2_3": null, "BRAM_LOGIC_OUTS_B2_4": null, "BRAM_LOGIC_OUTS_B3_0": null, "BRAM_LOGIC_OUTS_B3_1": null, "BRAM_LOGIC_OUTS_B3_2": null, "BRAM_LOGIC_OUTS_B3_3": null, "BRAM_LOGIC_OUTS_B3_4": null, "BRAM_LOGIC_OUTS_B4_0": null, "BRAM_LOGIC_OUTS_B4_1": null, "BRAM_LOGIC_OUTS_B4_2": null, "BRAM_LOGIC_OUTS_B4_3": null, "BRAM_LOGIC_OUTS_B4_4": null, "BRAM_LOGIC_OUTS_B5_0": null, "BRAM_LOGIC_OUTS_B5_1": null, "BRAM_LOGIC_OUTS_B5_2": null, "BRAM_LOGIC_OUTS_B5_3": null, "BRAM_LOGIC_OUTS_B5_4": null, "BRAM_LOGIC_OUTS_B6_0": null, "BRAM_LOGIC_OUTS_B6_1": null, "BRAM_LOGIC_OUTS_B6_2": null, "BRAM_LOGIC_OUTS_B6_3": null, "BRAM_LOGIC_OUTS_B6_4": null, "BRAM_LOGIC_OUTS_B7_0": null, "BRAM_LOGIC_OUTS_B7_1": null, "BRAM_LOGIC_OUTS_B7_2": null, "BRAM_LOGIC_OUTS_B7_3": null, "BRAM_LOGIC_OUTS_B7_4": null, "BRAM_LOGIC_OUTS_B8_0": null, "BRAM_LOGIC_OUTS_B8_1": null, "BRAM_LOGIC_OUTS_B8_2": null, "BRAM_LOGIC_OUTS_B8_3": null, "BRAM_LOGIC_OUTS_B8_4": null, "BRAM_LOGIC_OUTS_B9_0": null, "BRAM_LOGIC_OUTS_B9_1": null, "BRAM_LOGIC_OUTS_B9_2": null, "BRAM_LOGIC_OUTS_B9_3": null, "BRAM_LOGIC_OUTS_B9_4": null, "BRAM_LOGIC_OUTS_B10_0": null, "BRAM_LOGIC_OUTS_B10_1": null, "BRAM_LOGIC_OUTS_B10_2": null, "BRAM_LOGIC_OUTS_B10_3": null, "BRAM_LOGIC_OUTS_B10_4": null, "BRAM_LOGIC_OUTS_B11_0": null, "BRAM_LOGIC_OUTS_B11_1": null, "BRAM_LOGIC_OUTS_B11_2": null, "BRAM_LOGIC_OUTS_B11_3": null, "BRAM_LOGIC_OUTS_B11_4": null, "BRAM_LOGIC_OUTS_B12_0": null, "BRAM_LOGIC_OUTS_B12_1": null, "BRAM_LOGIC_OUTS_B12_2": null, "BRAM_LOGIC_OUTS_B12_3": null, "BRAM_LOGIC_OUTS_B12_4": null, "BRAM_LOGIC_OUTS_B13_0": null, "BRAM_LOGIC_OUTS_B13_1": null, "BRAM_LOGIC_OUTS_B13_2": null, "BRAM_LOGIC_OUTS_B13_3": null, "BRAM_LOGIC_OUTS_B13_4": null, "BRAM_LOGIC_OUTS_B14_0": null, "BRAM_LOGIC_OUTS_B14_1": null, "BRAM_LOGIC_OUTS_B14_2": null, "BRAM_LOGIC_OUTS_B14_3": null, "BRAM_LOGIC_OUTS_B14_4": null, "BRAM_LOGIC_OUTS_B15_0": null, "BRAM_LOGIC_OUTS_B15_1": null, "BRAM_LOGIC_OUTS_B15_2": null, "BRAM_LOGIC_OUTS_B15_3": null, "BRAM_LOGIC_OUTS_B15_4": null, "BRAM_LOGIC_OUTS_B16_0": null, "BRAM_LOGIC_OUTS_B16_1": null, "BRAM_LOGIC_OUTS_B16_2": null, "BRAM_LOGIC_OUTS_B16_3": null, "BRAM_LOGIC_OUTS_B16_4": null, "BRAM_LOGIC_OUTS_B17_0": null, "BRAM_LOGIC_OUTS_B17_1": null, "BRAM_LOGIC_OUTS_B17_2": null, "BRAM_LOGIC_OUTS_B17_3": null, "BRAM_LOGIC_OUTS_B17_4": null, "BRAM_LOGIC_OUTS_B18_0": null, "BRAM_LOGIC_OUTS_B18_1": null, "BRAM_LOGIC_OUTS_B18_2": null, "BRAM_LOGIC_OUTS_B18_3": null, "BRAM_LOGIC_OUTS_B18_4": null, "BRAM_LOGIC_OUTS_B19_0": null, "BRAM_LOGIC_OUTS_B19_1": null, "BRAM_LOGIC_OUTS_B19_2": null, "BRAM_LOGIC_OUTS_B19_3": null, "BRAM_LOGIC_OUTS_B19_4": null, "BRAM_LOGIC_OUTS_B20_0": null, "BRAM_LOGIC_OUTS_B20_1": null, "BRAM_LOGIC_OUTS_B20_2": null, "BRAM_LOGIC_OUTS_B20_3": null, "BRAM_LOGIC_OUTS_B20_4": null, "BRAM_LOGIC_OUTS_B21_0": null, "BRAM_LOGIC_OUTS_B21_1": null, "BRAM_LOGIC_OUTS_B21_2": null, "BRAM_LOGIC_OUTS_B21_3": null, "BRAM_LOGIC_OUTS_B21_4": null, "BRAM_LOGIC_OUTS_B22_0": null, "BRAM_LOGIC_OUTS_B22_1": null, "BRAM_LOGIC_OUTS_B22_2": null, "BRAM_LOGIC_OUTS_B22_3": null, "BRAM_LOGIC_OUTS_B22_4": null, "BRAM_LOGIC_OUTS_B23_0": null, "BRAM_LOGIC_OUTS_B23_1": null, "BRAM_LOGIC_OUTS_B23_2": null, "BRAM_LOGIC_OUTS_B23_3": null, "BRAM_LOGIC_OUTS_B23_4": null, "BRAM_MONITOR_N_0": null, "BRAM_MONITOR_N_1": null, "BRAM_MONITOR_N_2": null, "BRAM_MONITOR_N_3": null, "BRAM_MONITOR_N_4": null, "BRAM_MONITOR_P_0": null, "BRAM_MONITOR_P_1": null, "BRAM_MONITOR_P_2": null, "BRAM_MONITOR_P_3": null, "BRAM_MONITOR_P_4": null, "BRAM_NE2A0_0": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A0_1": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A0_2": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A0_3": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A0_4": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A1_0": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A1_1": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A1_2": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A1_3": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A1_4": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A2_0": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A2_1": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A2_2": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A2_3": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A2_4": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A3_0": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A3_1": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A3_2": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A3_3": { "cap": "60.430", "res": "268.920" }, "BRAM_NE2A3_4": { "cap": "60.430", "res": "268.920" }, "BRAM_NE4BEG0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4BEG3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NE4C3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NW2A0_0": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A0_1": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A0_2": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A0_3": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A0_4": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A1_0": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A1_1": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A1_2": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A1_3": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A1_4": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A2_0": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A2_1": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A2_2": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A2_3": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A2_4": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A3_0": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A3_1": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A3_2": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A3_3": { "cap": "60.430", "res": "268.920" }, "BRAM_NW2A3_4": { "cap": "60.430", "res": "268.920" }, "BRAM_NW4A0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4A3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_NW4END3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_PMVBRAM_O": null, "BRAM_PMVBRAM_ODIV2": null, "BRAM_PMVBRAM_ODIV2_1": null, "BRAM_PMVBRAM_ODIV4": null, "BRAM_PMVBRAM_O_1": null, "BRAM_PMVBRAM_O_2": null, "BRAM_PMVBRAM_SELECT1": null, "BRAM_PMVBRAM_SELECT2": null, "BRAM_PMVBRAM_SELECT3": null, "BRAM_PMVBRAM_SELECT4": null, "BRAM_RAMB18_ADDRARDADDR0": { "cap": "24.300", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR1": { "cap": "24.300", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR2": { "cap": "24.300", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR3": { "cap": "24.300", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR4": { "cap": "24.300", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR5": { "cap": "24.300", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR6": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR7": { "cap": "24.300", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR8": { "cap": "24.300", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR9": { "cap": "24.300", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR10": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR11": { "cap": "24.300", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR12": { "cap": "24.300", "res": "0.000" }, "BRAM_RAMB18_ADDRARDADDR13": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRATIEHIGH0": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRATIEHIGH1": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBTIEHIGH0": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBTIEHIGH1": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR0": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR1": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR2": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR3": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR4": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR5": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR6": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR7": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR8": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR9": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR10": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR11": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR12": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ADDRBWRADDR13": { "cap": "22.200", "res": "0.000" }, "BRAM_RAMB18_ALMOSTEMPTY": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_ALMOSTFULL": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_CLKARDCLK": { "cap": "22.000", "res": "0.000" }, "BRAM_RAMB18_CLKBWRCLK": { "cap": "22.000", "res": "0.000" }, "BRAM_RAMB18_DIADI0": { "cap": "31.700", "res": "0.000" }, "BRAM_RAMB18_DIADI1": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI2": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI3": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI4": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI5": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI6": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI7": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI8": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI9": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI10": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI11": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI12": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI13": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI14": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIADI15": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI0": { "cap": "33.200", "res": "0.000" }, "BRAM_RAMB18_DIBDI1": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI2": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI3": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI4": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI5": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI6": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI7": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI8": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI9": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI10": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI11": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI12": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI13": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI14": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIBDI15": { "cap": "8.400", "res": "0.000" }, "BRAM_RAMB18_DIPADIP0": { "cap": "28.600", "res": "0.000" }, "BRAM_RAMB18_DIPADIP1": { "cap": "28.600", "res": "0.000" }, "BRAM_RAMB18_DIPBDIP0": { "cap": "28.600", "res": "0.000" }, "BRAM_RAMB18_DIPBDIP1": { "cap": "28.600", "res": "0.000" }, "BRAM_RAMB18_DOADO0": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO1": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO2": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO3": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO4": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO5": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO6": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO7": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO8": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO9": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO10": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO11": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO12": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO13": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO14": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOADO15": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO0": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO1": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO2": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO3": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO4": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO5": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO6": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO7": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO8": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO9": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO10": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO11": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO12": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO13": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO14": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOBDO15": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOPADOP0": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOPADOP1": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOPBDOP0": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_DOPBDOP1": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_EMPTY": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_ENARDEN": { "cap": "30.800", "res": "0.000" }, "BRAM_RAMB18_ENBWREN": { "cap": "30.800", "res": "0.000" }, "BRAM_RAMB18_FULL": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDCOUNT0": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDCOUNT1": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDCOUNT2": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDCOUNT3": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDCOUNT4": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDCOUNT5": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDCOUNT6": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDCOUNT7": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDCOUNT8": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDCOUNT9": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDCOUNT10": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDCOUNT11": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_RDERR": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_REGCEAREGCE": { "cap": "30.800", "res": "0.000" }, "BRAM_RAMB18_REGCEB": { "cap": "30.800", "res": "0.000" }, "BRAM_RAMB18_REGCLKARDRCLK": { "cap": "18.800", "res": "0.000" }, "BRAM_RAMB18_REGCLKB": { "cap": "18.800", "res": "0.000" }, "BRAM_RAMB18_RSTRAMARSTRAM": { "cap": "11.400", "res": "0.000" }, "BRAM_RAMB18_RSTRAMB": { "cap": "11.400", "res": "0.000" }, "BRAM_RAMB18_RSTREGARSTREG": { "cap": "11.400", "res": "0.000" }, "BRAM_RAMB18_RSTREGB": { "cap": "11.400", "res": "0.000" }, "BRAM_RAMB18_WEA0": { "cap": "29.200", "res": "0.000" }, "BRAM_RAMB18_WEA1": { "cap": "29.200", "res": "0.000" }, "BRAM_RAMB18_WEA2": { "cap": "29.200", "res": "0.000" }, "BRAM_RAMB18_WEA3": { "cap": "29.200", "res": "0.000" }, "BRAM_RAMB18_WEBWE0": { "cap": "29.200", "res": "0.000" }, "BRAM_RAMB18_WEBWE1": { "cap": "29.200", "res": "0.000" }, "BRAM_RAMB18_WEBWE2": { "cap": "29.200", "res": "0.000" }, "BRAM_RAMB18_WEBWE3": { "cap": "29.200", "res": "0.000" }, "BRAM_RAMB18_WEBWE4": { "cap": "29.200", "res": "0.000" }, "BRAM_RAMB18_WEBWE5": { "cap": "29.200", "res": "0.000" }, "BRAM_RAMB18_WEBWE6": { "cap": "29.200", "res": "0.000" }, "BRAM_RAMB18_WEBWE7": { "cap": "29.200", "res": "0.000" }, "BRAM_RAMB18_WRCOUNT0": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_WRCOUNT1": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_WRCOUNT2": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_WRCOUNT3": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_WRCOUNT4": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_WRCOUNT5": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_WRCOUNT6": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_WRCOUNT7": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_WRCOUNT8": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_WRCOUNT9": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_WRCOUNT10": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_WRCOUNT11": { "cap": "25.100", "res": "0.000" }, "BRAM_RAMB18_WRERR": { "cap": "25.100", "res": "0.000" }, "BRAM_SE2A0_0": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A0_1": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A0_2": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A0_3": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A0_4": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A1_0": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A1_1": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A1_2": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A1_3": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A1_4": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A2_0": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A2_1": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A2_2": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A2_3": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A2_4": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A3_0": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A3_1": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A3_2": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A3_3": { "cap": "60.430", "res": "268.920" }, "BRAM_SE2A3_4": { "cap": "60.430", "res": "268.920" }, "BRAM_SE4BEG0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4BEG3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SE4C3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SW2A0_0": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A0_1": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A0_2": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A0_3": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A0_4": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A1_0": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A1_1": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A1_2": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A1_3": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A1_4": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A2_0": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A2_1": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A2_2": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A2_3": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A2_4": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A3_0": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A3_1": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A3_2": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A3_3": { "cap": "60.430", "res": "268.920" }, "BRAM_SW2A3_4": { "cap": "60.430", "res": "268.920" }, "BRAM_SW4A0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4A3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_SW4END3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_UTURN_ADDRARDADDRL0": null, "BRAM_UTURN_ADDRARDADDRL1": null, "BRAM_UTURN_ADDRARDADDRL2": null, "BRAM_UTURN_ADDRARDADDRL3": null, "BRAM_UTURN_ADDRARDADDRL4": null, "BRAM_UTURN_ADDRARDADDRL5": null, "BRAM_UTURN_ADDRARDADDRL6": null, "BRAM_UTURN_ADDRARDADDRL7": null, "BRAM_UTURN_ADDRARDADDRL8": null, "BRAM_UTURN_ADDRARDADDRL9": null, "BRAM_UTURN_ADDRARDADDRL10": null, "BRAM_UTURN_ADDRARDADDRL11": null, "BRAM_UTURN_ADDRARDADDRL12": null, "BRAM_UTURN_ADDRARDADDRL13": null, "BRAM_UTURN_ADDRARDADDRL14": null, "BRAM_UTURN_ADDRARDADDRL15": null, "BRAM_UTURN_ADDRARDADDRU0": null, "BRAM_UTURN_ADDRARDADDRU1": null, "BRAM_UTURN_ADDRARDADDRU2": null, "BRAM_UTURN_ADDRARDADDRU3": null, "BRAM_UTURN_ADDRARDADDRU4": null, "BRAM_UTURN_ADDRARDADDRU5": null, "BRAM_UTURN_ADDRARDADDRU6": null, "BRAM_UTURN_ADDRARDADDRU7": null, "BRAM_UTURN_ADDRARDADDRU8": null, "BRAM_UTURN_ADDRARDADDRU9": null, "BRAM_UTURN_ADDRARDADDRU10": null, "BRAM_UTURN_ADDRARDADDRU11": null, "BRAM_UTURN_ADDRARDADDRU12": null, "BRAM_UTURN_ADDRARDADDRU13": null, "BRAM_UTURN_ADDRARDADDRU14": null, "BRAM_UTURN_ADDRBWRADDRL0": null, "BRAM_UTURN_ADDRBWRADDRL1": null, "BRAM_UTURN_ADDRBWRADDRL2": null, "BRAM_UTURN_ADDRBWRADDRL3": null, "BRAM_UTURN_ADDRBWRADDRL4": null, "BRAM_UTURN_ADDRBWRADDRL5": null, "BRAM_UTURN_ADDRBWRADDRL6": null, "BRAM_UTURN_ADDRBWRADDRL7": null, "BRAM_UTURN_ADDRBWRADDRL8": null, "BRAM_UTURN_ADDRBWRADDRL9": null, "BRAM_UTURN_ADDRBWRADDRL10": null, "BRAM_UTURN_ADDRBWRADDRL11": null, "BRAM_UTURN_ADDRBWRADDRL12": null, "BRAM_UTURN_ADDRBWRADDRL13": null, "BRAM_UTURN_ADDRBWRADDRL14": null, "BRAM_UTURN_ADDRBWRADDRL15": null, "BRAM_UTURN_ADDRBWRADDRU0": null, "BRAM_UTURN_ADDRBWRADDRU1": null, "BRAM_UTURN_ADDRBWRADDRU2": null, "BRAM_UTURN_ADDRBWRADDRU3": null, "BRAM_UTURN_ADDRBWRADDRU4": null, "BRAM_UTURN_ADDRBWRADDRU5": null, "BRAM_UTURN_ADDRBWRADDRU6": null, "BRAM_UTURN_ADDRBWRADDRU7": null, "BRAM_UTURN_ADDRBWRADDRU8": null, "BRAM_UTURN_ADDRBWRADDRU9": null, "BRAM_UTURN_ADDRBWRADDRU10": null, "BRAM_UTURN_ADDRBWRADDRU11": null, "BRAM_UTURN_ADDRBWRADDRU12": null, "BRAM_UTURN_ADDRBWRADDRU13": null, "BRAM_UTURN_ADDRBWRADDRU14": null, "BRAM_WL1END0_0": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END0_1": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END0_2": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END0_3": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END0_4": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END1_0": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END1_1": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END1_2": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END1_3": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END1_4": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END2_0": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END2_1": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END2_2": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END2_3": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END2_4": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END3_0": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END3_1": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END3_2": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END3_3": { "cap": "64.292", "res": "268.920" }, "BRAM_WL1END3_4": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END0_0": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END0_1": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END0_2": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END0_3": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END0_4": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END1_0": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END1_1": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END1_2": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END1_3": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END1_4": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END2_0": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END2_1": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END2_2": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END2_3": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END2_4": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END3_0": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END3_1": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END3_2": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END3_3": { "cap": "64.292", "res": "268.920" }, "BRAM_WR1END3_4": { "cap": "64.292", "res": "268.920" }, "BRAM_WW2A0_0": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A0_1": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A0_2": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A0_3": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A0_4": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A1_0": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A1_1": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A1_2": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A1_3": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A1_4": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A2_0": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A2_1": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A2_2": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A2_3": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A2_4": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A3_0": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A3_1": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A3_2": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A3_3": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2A3_4": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END0_0": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END0_1": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END0_2": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END0_3": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END0_4": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END1_0": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END1_1": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END1_2": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END1_3": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END1_4": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END2_0": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END2_1": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END2_2": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END2_3": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END2_4": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END3_0": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END3_1": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END3_2": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END3_3": { "cap": "60.430", "res": "268.920" }, "BRAM_WW2END3_4": { "cap": "60.430", "res": "268.920" }, "BRAM_WW4A0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4A3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4B3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4C3_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END0_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END0_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END0_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END0_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END0_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END1_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END1_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END1_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END1_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END1_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END2_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END2_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END2_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END2_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END2_4": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END3_0": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END3_1": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END3_2": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END3_3": { "cap": "55.660", "res": "268.920" }, "BRAM_WW4END3_4": { "cap": "55.660", "res": "268.920" } } }