{ "pips": { "CLBLL_L.CLBLL_BYP0->CLBLL_L_AX": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_AX", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_BYP0" }, "CLBLL_L.CLBLL_BYP1->CLBLL_LL_AX": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_AX", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_BYP1" }, "CLBLL_L.CLBLL_BYP2->CLBLL_L_CX": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_CX", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_BYP2" }, "CLBLL_L.CLBLL_BYP3->CLBLL_LL_CX": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_CX", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_BYP3" }, "CLBLL_L.CLBLL_BYP4->CLBLL_LL_BX": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_BX", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_BYP4" }, "CLBLL_L.CLBLL_BYP5->CLBLL_L_BX": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_BX", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_BYP5" }, "CLBLL_L.CLBLL_BYP6->CLBLL_LL_DX": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_DX", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_BYP6" }, "CLBLL_L.CLBLL_BYP7->CLBLL_L_DX": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_DX", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_BYP7" }, "CLBLL_L.CLBLL_CLK0->CLBLL_L_CLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_CLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_CLK0" }, "CLBLL_L.CLBLL_CLK1->CLBLL_LL_CLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_CLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_CLK1" }, "CLBLL_L.CLBLL_CTRL0->CLBLL_L_SR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_SR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_CTRL0" }, "CLBLL_L.CLBLL_CTRL1->CLBLL_LL_SR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_SR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_CTRL1" }, "CLBLL_L.CLBLL_FAN6->CLBLL_L_CE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_CE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_FAN6" }, "CLBLL_L.CLBLL_FAN7->CLBLL_LL_CE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_CE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_FAN7" }, "CLBLL_L.CLBLL_IMUX0->CLBLL_L_A3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_A3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX0" }, "CLBLL_L.CLBLL_IMUX1->CLBLL_LL_A3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_A3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX1" }, "CLBLL_L.CLBLL_IMUX2->CLBLL_LL_A2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_A2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX2" }, "CLBLL_L.CLBLL_IMUX3->CLBLL_L_A2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_A2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX3" }, "CLBLL_L.CLBLL_IMUX4->CLBLL_LL_A6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_A6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX4" }, "CLBLL_L.CLBLL_IMUX5->CLBLL_L_A6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_A6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX5" }, "CLBLL_L.CLBLL_IMUX6->CLBLL_L_A1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_A1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX6" }, "CLBLL_L.CLBLL_IMUX7->CLBLL_LL_A1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_A1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX7" }, "CLBLL_L.CLBLL_IMUX8->CLBLL_LL_A5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_A5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX8" }, "CLBLL_L.CLBLL_IMUX9->CLBLL_L_A5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_A5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX9" }, "CLBLL_L.CLBLL_IMUX10->CLBLL_L_A4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_A4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX10" }, "CLBLL_L.CLBLL_IMUX11->CLBLL_LL_A4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_A4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX11" }, "CLBLL_L.CLBLL_IMUX12->CLBLL_LL_B6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_B6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX12" }, "CLBLL_L.CLBLL_IMUX13->CLBLL_L_B6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_B6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX13" }, "CLBLL_L.CLBLL_IMUX14->CLBLL_L_B1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_B1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX14" }, "CLBLL_L.CLBLL_IMUX15->CLBLL_LL_B1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_B1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX15" }, "CLBLL_L.CLBLL_IMUX16->CLBLL_L_B3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_B3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX16" }, "CLBLL_L.CLBLL_IMUX17->CLBLL_LL_B3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_B3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX17" }, "CLBLL_L.CLBLL_IMUX18->CLBLL_LL_B2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_B2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX18" }, "CLBLL_L.CLBLL_IMUX19->CLBLL_L_B2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_B2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX19" }, "CLBLL_L.CLBLL_IMUX20->CLBLL_L_C2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_C2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX20" }, "CLBLL_L.CLBLL_IMUX21->CLBLL_L_C4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_C4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX21" }, "CLBLL_L.CLBLL_IMUX22->CLBLL_LL_C3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_C3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX22" }, "CLBLL_L.CLBLL_IMUX23->CLBLL_L_C3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_C3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX23" }, "CLBLL_L.CLBLL_IMUX24->CLBLL_LL_B5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_B5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX24" }, "CLBLL_L.CLBLL_IMUX25->CLBLL_L_B5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_B5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX25" }, "CLBLL_L.CLBLL_IMUX26->CLBLL_L_B4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_B4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX26" }, "CLBLL_L.CLBLL_IMUX27->CLBLL_LL_B4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_B4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX27" }, "CLBLL_L.CLBLL_IMUX28->CLBLL_LL_C4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_C4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX28" }, "CLBLL_L.CLBLL_IMUX29->CLBLL_LL_C2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_C2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX29" }, "CLBLL_L.CLBLL_IMUX30->CLBLL_L_C5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_C5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX30" }, "CLBLL_L.CLBLL_IMUX31->CLBLL_LL_C5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_C5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX31" }, "CLBLL_L.CLBLL_IMUX32->CLBLL_LL_C1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_C1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX32" }, "CLBLL_L.CLBLL_IMUX33->CLBLL_L_C1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_C1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX33" }, "CLBLL_L.CLBLL_IMUX34->CLBLL_L_C6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_C6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX34" }, "CLBLL_L.CLBLL_IMUX35->CLBLL_LL_C6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_C6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX35" }, "CLBLL_L.CLBLL_IMUX36->CLBLL_L_D2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_D2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX36" }, "CLBLL_L.CLBLL_IMUX37->CLBLL_L_D4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_D4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX37" }, "CLBLL_L.CLBLL_IMUX38->CLBLL_LL_D3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_D3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX38" }, "CLBLL_L.CLBLL_IMUX39->CLBLL_L_D3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_D3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX39" }, "CLBLL_L.CLBLL_IMUX40->CLBLL_LL_D1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_D1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX40" }, "CLBLL_L.CLBLL_IMUX41->CLBLL_L_D1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_D1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX41" }, "CLBLL_L.CLBLL_IMUX42->CLBLL_L_D6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_L_D6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX42" }, "CLBLL_L.CLBLL_IMUX43->CLBLL_LL_D6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LL_D6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_IMUX43" }, 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"src_to_dst": { "delay": [ "0.045", "0.056", "0.100", "0.124" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLBLL_LL_A5" }, "CLBLL_L.CLBLL_LL_A6->>CLBLL_LL_A": { "can_invert": "0", "dst_to_src": { "delay": [ "0.045", "0.056", "0.100", "0.124" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.045", "0.056", "0.100", "0.124" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLBLL_LL_A6" }, "CLBLL_L.CLBLL_LL_A->>CLBLL_LL_AMUX": { "can_invert": "0", "dst_to_src": { "delay": [ "0.071", "0.088", "0.168", "0.209" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLBLL_LL_AMUX", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.071", "0.088", "0.168", "0.209" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLBLL_LL_A" }, "CLBLL_L.CLBLL_LL_A->CLBLL_LOGIC_OUTS12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LOGIC_OUTS12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_LL_A" }, "CLBLL_L.CLBLL_LL_AMUX->CLBLL_LOGIC_OUTS20": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LOGIC_OUTS20", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_LL_AMUX" }, "CLBLL_L.CLBLL_LL_AQ->CLBLL_LOGIC_OUTS4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LOGIC_OUTS4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_LL_AQ" }, "CLBLL_L.CLBLL_LL_B1->>CLBLL_LL_B": { "can_invert": "0", "dst_to_src": { "delay": [ "0.045", "0.056", "0.100", "0.124" ], "in_cap": null, "res": "0.0" }, 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"0.100", "0.124" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLBLL_LL_B6" }, "CLBLL_L.CLBLL_LL_B->>CLBLL_LL_BMUX": { "can_invert": "0", "dst_to_src": { "delay": [ "0.073", "0.091", "0.168", "0.208" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLBLL_LL_BMUX", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.073", "0.091", "0.168", "0.208" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLBLL_LL_B" }, "CLBLL_L.CLBLL_LL_B->CLBLL_LOGIC_OUTS13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LOGIC_OUTS13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_LL_B" }, "CLBLL_L.CLBLL_LL_BMUX->CLBLL_LOGIC_OUTS21": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LOGIC_OUTS21", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_LL_BMUX" }, "CLBLL_L.CLBLL_LL_BQ->CLBLL_LOGIC_OUTS5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLBLL_LOGIC_OUTS5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLBLL_LL_BQ" }, "CLBLL_L.CLBLL_LL_C1->>CLBLL_LL_C": { "can_invert": "0", "dst_to_src": { "delay": [ "0.045", "0.056", "0.100", "0.124" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLBLL_LL_C", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.045", "0.056", "0.100", "0.124" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLBLL_LL_C1" }, "CLBLL_L.CLBLL_LL_C2->>CLBLL_LL_C": { "can_invert": "0", "dst_to_src": { "delay": [ "0.045", "0.056", "0.100", "0.124" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLBLL_LL_C", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.045", "0.056", "0.100", "0.124" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLBLL_LL_C2" }, "CLBLL_L.CLBLL_LL_C3->>CLBLL_LL_C": { "can_invert": "0", "dst_to_src": { "delay": [ "0.045", "0.056", "0.100", "0.124" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLBLL_LL_C", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.045", "0.056", "0.100", "0.124" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLBLL_LL_C3" }, "CLBLL_L.CLBLL_LL_C4->>CLBLL_LL_C": { "can_invert": "0", "dst_to_src": { "delay": [ "0.045", "0.056", "0.100", "0.124" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLBLL_LL_C", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.045", "0.056", "0.100", "0.124" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLBLL_LL_C4" }, "CLBLL_L.CLBLL_LL_C5->>CLBLL_LL_C": { "can_invert": "0", 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