{ "pips": { "GTP_COMMON_MID_LEFT.GTPE2_CLK0_1->GTPE2_COMMON_PLL0LOCKDETCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL0LOCKDETCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_CLK0_1" }, "GTP_COMMON_MID_LEFT.GTPE2_CLK0_5->GTPE2_COMMON_GTGREFCLK0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_GTGREFCLK0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_CLK0_5" }, "GTP_COMMON_MID_LEFT.GTPE2_CLK1_1->GTPE2_COMMON_PLL1LOCKDETCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL1LOCKDETCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_CLK1_1" }, "GTP_COMMON_MID_LEFT.GTPE2_CLK1_4->GTPE2_COMMON_GTGREFCLK1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_GTGREFCLK1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_CLK1_4" }, "GTP_COMMON_MID_LEFT.GTPE2_CLK1_5->GTPE2_COMMON_DRPCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_CLK1_5" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DMONITOROUT0->GTPE2_LOGIC_OUTS_B8_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B8_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DMONITOROUT0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DMONITOROUT1->GTPE2_LOGIC_OUTS_B8_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B8_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DMONITOROUT1" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DMONITOROUT2->GTPE2_LOGIC_OUTS_B8_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B8_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DMONITOROUT2" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DMONITOROUT3->GTPE2_LOGIC_OUTS_B8_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B8_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DMONITOROUT3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DMONITOROUT4->GTPE2_LOGIC_OUTS_B8_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B8_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DMONITOROUT4" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DMONITOROUT5->GTPE2_LOGIC_OUTS_B14_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B14_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DMONITOROUT5" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DMONITOROUT6->GTPE2_LOGIC_OUTS_B14_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B14_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DMONITOROUT6" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DMONITOROUT7->GTPE2_LOGIC_OUTS_B14_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B14_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DMONITOROUT7" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO0->GTPE2_LOGIC_OUTS_B9_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B9_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO1->GTPE2_LOGIC_OUTS_B9_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B9_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO1" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO2->GTPE2_LOGIC_OUTS_B9_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B9_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO2" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO3->GTPE2_LOGIC_OUTS_B9_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B9_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO4->GTPE2_LOGIC_OUTS_B9_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B9_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO4" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO5->GTPE2_LOGIC_OUTS_B16_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B16_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO5" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO6->GTPE2_LOGIC_OUTS_B16_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B16_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO6" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO7->GTPE2_LOGIC_OUTS_B16_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B16_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO7" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO8->GTPE2_LOGIC_OUTS_B16_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B16_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO8" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO9->GTPE2_LOGIC_OUTS_B16_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B16_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO9" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO10->GTPE2_LOGIC_OUTS_B10_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B10_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO10" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO11->GTPE2_LOGIC_OUTS_B10_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B10_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO11" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO12->GTPE2_LOGIC_OUTS_B10_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B10_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO12" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO13->GTPE2_LOGIC_OUTS_B10_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B10_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO13" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO14->GTPE2_LOGIC_OUTS_B10_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B10_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO14" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPDO15->GTPE2_LOGIC_OUTS_B18_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B18_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPDO15" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_DRPRDY->GTPE2_LOGIC_OUTS_B17_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B17_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_DRPRDY" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0FBCLKLOST->GTPE2_LOGIC_OUTS_B17_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B17_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PLL0FBCLKLOST" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0LOCK->GTPE2_LOGIC_OUTS_B17_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B17_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PLL0LOCK" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0OUTCLK->GTPE2_COMMON_PLLOUTCLK0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLOUTCLK0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PLL0OUTCLK" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLK->GTPE2_COMMON_PLLREFCLK0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLREFCLK0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PLL0REFCLK" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL0REFCLKLOST->GTPE2_LOGIC_OUTS_B17_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B17_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PLL0REFCLKLOST" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1FBCLKLOST->GTPE2_LOGIC_OUTS_B18_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B18_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PLL1FBCLKLOST" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1LOCK->GTPE2_LOGIC_OUTS_B11_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B11_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PLL1LOCK" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1OUTCLK->GTPE2_COMMON_PLLOUTCLK1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLOUTCLK1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PLL1OUTCLK" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLK->GTPE2_COMMON_PLLREFCLK1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLREFCLK1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PLL1REFCLK" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PLL1REFCLKLOST->GTPE2_LOGIC_OUTS_B11_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B11_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PLL1REFCLKLOST" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT0->GTPE2_LOGIC_OUTS_B13_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B13_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT1->GTPE2_LOGIC_OUTS_B13_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B13_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT1" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT2->GTPE2_LOGIC_OUTS_B13_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B13_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT2" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT3->GTPE2_LOGIC_OUTS_B13_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B13_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT4->GTPE2_LOGIC_OUTS_B13_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B13_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT4" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT5->GTPE2_LOGIC_OUTS_B19_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B19_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT5" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT6->GTPE2_LOGIC_OUTS_B19_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B19_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT6" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT7->GTPE2_LOGIC_OUTS_B19_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B19_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT7" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT8->GTPE2_LOGIC_OUTS_B19_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B19_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT8" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT9->GTPE2_LOGIC_OUTS_B19_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B19_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT9" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT10->GTPE2_LOGIC_OUTS_B20_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B20_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT10" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT11->GTPE2_LOGIC_OUTS_B20_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B20_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT11" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT12->GTPE2_LOGIC_OUTS_B20_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B20_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT12" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT13->GTPE2_LOGIC_OUTS_B20_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B20_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT13" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT14->GTPE2_LOGIC_OUTS_B20_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B20_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT14" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_PMARSVDOUT15->GTPE2_LOGIC_OUTS_B18_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B18_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_PMARSVDOUT15" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLK0->>GTPE2_COMMON_GTREFCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTPE2_COMMON_GTREFCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_REFCLK0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLK0->>HCLK_GTP_REFCK_EASTCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_GTP_REFCK_EASTCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "GTPE2_COMMON_REFCLK0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLK0->>HCLK_GTP_REFCK_EASTCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_GTP_REFCK_EASTCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "GTPE2_COMMON_REFCLK0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLK1->>GTPE2_COMMON_GTREFCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTPE2_COMMON_GTREFCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_REFCLK1" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLK1->>HCLK_GTP_REFCK_EASTCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_GTP_REFCK_EASTCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "GTPE2_COMMON_REFCLK1" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLK1->>HCLK_GTP_REFCK_EASTCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_GTP_REFCK_EASTCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "GTPE2_COMMON_REFCLK1" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLKOUTMONITOR0->GTPE2_LOGIC_OUTS_B17_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B17_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_REFCLKOUTMONITOR0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_REFCLKOUTMONITOR1->GTPE2_LOGIC_OUTS_B18_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_LOGIC_OUTS_B18_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_COMMON_REFCLKOUTMONITOR1" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_0->>GTPE2_COMMON_RXOUTCLK_MUX_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "GTPE2_COMMON_RXOUTCLK_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_1->>GTPE2_COMMON_RXOUTCLK_MUX_1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "GTPE2_COMMON_RXOUTCLK_MUX_1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "GTPE2_COMMON_RXOUTCLK_1" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_2->>GTPE2_COMMON_RXOUTCLK_MUX_2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "GTPE2_COMMON_RXOUTCLK_MUX_2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "GTPE2_COMMON_RXOUTCLK_2" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_3->>GTPE2_COMMON_RXOUTCLK_MUX_3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "GTPE2_COMMON_RXOUTCLK_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_0->>HCLK_GTP_CK_IN12": { "can_invert": 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"is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_RXOUTCLK_MUX_3->>HCLK_GTP_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_RXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_0->>GTPE2_COMMON_TXOUTCLK_MUX_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "GTPE2_COMMON_TXOUTCLK_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_1->>GTPE2_COMMON_TXOUTCLK_MUX_1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "GTPE2_COMMON_TXOUTCLK_MUX_1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "GTPE2_COMMON_TXOUTCLK_1" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_2->>GTPE2_COMMON_TXOUTCLK_MUX_2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "GTPE2_COMMON_TXOUTCLK_MUX_2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "GTPE2_COMMON_TXOUTCLK_2" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_3->>GTPE2_COMMON_TXOUTCLK_MUX_3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "GTPE2_COMMON_TXOUTCLK_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_0->>HCLK_GTP_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_0" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_1->>HCLK_GTP_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_1" }, 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], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_2" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_2->>HCLK_GTP_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_2" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_2->>HCLK_GTP_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_2" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_2->>HCLK_GTP_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_2" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3->>HCLK_GTP_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3" }, 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], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3->>HCLK_GTP_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3->>HCLK_GTP_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3->>HCLK_GTP_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3->>HCLK_GTP_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3->>HCLK_GTP_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3->>HCLK_GTP_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3->>HCLK_GTP_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3->>HCLK_GTP_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3->>HCLK_GTP_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_COMMON_TXOUTCLK_MUX_3->>HCLK_GTP_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTPE2_COMMON_TXOUTCLK_MUX_3" }, "GTP_COMMON_MID_LEFT.GTPE2_CTRL0_3->GTPE2_COMMON_PLL0RESET": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL0RESET", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_CTRL0_3" }, "GTP_COMMON_MID_LEFT.GTPE2_CTRL1_3->GTPE2_COMMON_PLL1RESET": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL1RESET", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_CTRL1_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX0_1->IBUFDS_GTPE2_1_CEB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTPE2_1_CEB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX0_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX0_2->GTPE2_COMMON_PLLRSVD115": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD115", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX0_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX0_3->GTPE2_COMMON_PLLRSVD114": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD114", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX0_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX0_4->GTPE2_COMMON_PLLRSVD113": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD113", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX0_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX0_5->GTPE2_COMMON_PLLRSVD112": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD112", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX0_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX2_1->GTPE2_COMMON_PLL1REFCLKSEL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL1REFCLKSEL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX2_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX2_2->GTPE2_COMMON_PLL1REFCLKSEL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL1REFCLKSEL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX2_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX2_3->GTPE2_COMMON_PLL0REFCLKSEL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL0REFCLKSEL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX2_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX2_4->GTPE2_COMMON_PLL0REFCLKSEL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL0REFCLKSEL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX2_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX2_5->GTPE2_COMMON_PLL0REFCLKSEL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL0REFCLKSEL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX2_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX3_1->IBUFDS_GTPE2_0_CEB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTPE2_0_CEB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX3_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX3_3->GTPE2_COMMON_BGPDB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_BGPDB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX3_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX3_5->GTPE2_COMMON_RCALENB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_RCALENB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX3_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX5_1->GTPE2_COMMON_PLLRSVD24": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD24", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX5_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX5_2->GTPE2_COMMON_PLLRSVD23": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD23", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX5_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX5_3->GTPE2_COMMON_PLLRSVD22": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD22", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX5_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX5_4->GTPE2_COMMON_PLLRSVD21": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD21", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX5_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX5_5->GTPE2_COMMON_PLLRSVD20": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD20", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX5_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX14_2->GTPE2_COMMON_DRPDI11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX14_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX14_4->GTPE2_COMMON_DRPDI15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX14_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX14_5->GTPE2_COMMON_DRPDI13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX14_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX20_1->GTPE2_COMMON_PMARSVD4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PMARSVD4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX20_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX20_2->GTPE2_COMMON_PMARSVD3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PMARSVD3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX20_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX20_3->GTPE2_COMMON_PMARSVD2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PMARSVD2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX20_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX20_4->GTPE2_COMMON_PMARSVD1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PMARSVD1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX20_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX20_5->GTPE2_COMMON_PMARSVD0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PMARSVD0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX20_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX22_1->GTPE2_COMMON_BGMONITORENB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_BGMONITORENB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX22_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX22_2->GTPE2_COMMON_DRPDI10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX22_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX22_3->GTPE2_COMMON_DRPEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX22_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX22_4->GTPE2_COMMON_DRPDI14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX22_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX22_5->GTPE2_COMMON_DRPDI12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX22_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX24_1->GTPE2_COMMON_PLLRSVD19": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD19", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX24_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX24_2->GTPE2_COMMON_PLLRSVD17": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD17", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX24_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX24_3->GTPE2_COMMON_PLLRSVD15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX24_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX24_4->GTPE2_COMMON_PLLRSVD13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX24_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX24_5->GTPE2_COMMON_PLLRSVD11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX24_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX27_1->GTPE2_COMMON_BGBYPASSB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_BGBYPASSB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX27_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX27_2->GTPE2_COMMON_DRPADDR7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPADDR7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX27_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX27_3->GTPE2_COMMON_DRPADDR5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPADDR5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX27_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX27_4->GTPE2_COMMON_DRPADDR3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPADDR3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX27_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX27_5->GTPE2_COMMON_DRPADDR1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPADDR1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX27_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX30_1->GTPE2_COMMON_DRPDI9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX30_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX30_2->GTPE2_COMMON_DRPDI7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX30_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX30_3->GTPE2_COMMON_DRPDI5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX30_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX30_4->GTPE2_COMMON_DRPDI3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX30_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX30_5->GTPE2_COMMON_DRPDI1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX30_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX32_1->GTPE2_COMMON_PLLRSVD18": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD18", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX32_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX32_2->GTPE2_COMMON_PLLRSVD16": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD16", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX32_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX32_3->GTPE2_COMMON_PLLRSVD14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX32_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX32_4->GTPE2_COMMON_PLLRSVD12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX32_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX32_5->GTPE2_COMMON_PLLRSVD10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX32_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX35_1->GTPE2_COMMON_DRPWE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPWE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX35_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX35_2->GTPE2_COMMON_DRPADDR6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPADDR6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX35_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX35_3->GTPE2_COMMON_DRPADDR4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPADDR4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX35_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX35_4->GTPE2_COMMON_DRPADDR2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPADDR2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX35_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX35_5->GTPE2_COMMON_DRPADDR0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPADDR0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX35_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX38_1->GTPE2_COMMON_DRPDI8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX38_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX38_2->GTPE2_COMMON_DRPDI6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX38_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX38_3->GTPE2_COMMON_DRPDI4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX38_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX38_4->GTPE2_COMMON_DRPDI2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX38_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX38_5->GTPE2_COMMON_DRPDI0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_DRPDI0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX38_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX40_4->GTPE2_COMMON_PLLRSVD111": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD111", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX40_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX40_5->GTPE2_COMMON_PLLRSVD110": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLLRSVD110", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX40_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX41_2->GTPE2_COMMON_PMARSVD7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PMARSVD7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX41_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX41_3->GTPE2_COMMON_PLL1REFCLKSEL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL1REFCLKSEL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX41_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX41_4->GTPE2_COMMON_PMARSVD6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PMARSVD6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX41_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX41_5->GTPE2_COMMON_PMARSVD5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PMARSVD5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX41_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX42_1->GTPE2_COMMON_PLL1PD": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL1PD", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX42_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX42_2->GTPE2_COMMON_PLL1LOCKEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL1LOCKEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX42_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX42_3->GTPE2_COMMON_PLL0PD": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL0PD", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX42_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX42_4->GTPE2_COMMON_PLL0LOCKEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_PLL0LOCKEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX42_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX42_5->GTPE2_COMMON_BGRCALOVRDENB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_BGRCALOVRDENB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX42_5" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX45_1->GTPE2_COMMON_BGRCALOVRD4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_BGRCALOVRD4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX45_1" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX45_2->GTPE2_COMMON_BGRCALOVRD3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_BGRCALOVRD3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX45_2" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX45_3->GTPE2_COMMON_BGRCALOVRD2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_BGRCALOVRD2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX45_3" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX45_4->GTPE2_COMMON_BGRCALOVRD1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_BGRCALOVRD1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX45_4" }, "GTP_COMMON_MID_LEFT.GTPE2_IMUX45_5->GTPE2_COMMON_BGRCALOVRD0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_BGRCALOVRD0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTPE2_IMUX45_5" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX0->>HCLK_GTP_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX0" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX0->>HCLK_GTP_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX0" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX1->>HCLK_GTP_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX1" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX1->>HCLK_GTP_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX1" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX2->>HCLK_GTP_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX2" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX2->>HCLK_GTP_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX2" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX3->>HCLK_GTP_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX3" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX3->>HCLK_GTP_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX3" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX4->>HCLK_GTP_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX4" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX4->>HCLK_GTP_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX4" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX5->>HCLK_GTP_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX5" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX5->>HCLK_GTP_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX5" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX6->>HCLK_GTP_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX6" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX6->>HCLK_GTP_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX6" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX7->>HCLK_GTP_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX7" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX7->>HCLK_GTP_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX7" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX8->>HCLK_GTP_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX8" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX8->>HCLK_GTP_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX8" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX9->>HCLK_GTP_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX9" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX9->>HCLK_GTP_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX9" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX10->>HCLK_GTP_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX10" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX10->>HCLK_GTP_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX10" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX11->>HCLK_GTP_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX11" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX11->>HCLK_GTP_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX11" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX12->>HCLK_GTP_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX12" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX12->>HCLK_GTP_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX12" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX13->>HCLK_GTP_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX13" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_CK_MUX13->>HCLK_GTP_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_GTP_CK_MUX13" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_REFCK_WESTCLK0->GTPE2_COMMON_GTWESTREFCLK0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_GTWESTREFCLK0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "HCLK_GTP_REFCK_WESTCLK0" }, "GTP_COMMON_MID_LEFT.HCLK_GTP_REFCK_WESTCLK1->GTPE2_COMMON_GTWESTREFCLK1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_GTWESTREFCLK1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "HCLK_GTP_REFCK_WESTCLK1" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_CLKTESTSIG_SEG->IBUFDS_GTPE2_0_CLKTESTSIG": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTPE2_0_CLKTESTSIG", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTPE2_0_CLKTESTSIG_SEG" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_I->IBUFDS_GTPE2_0_I_SEG": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTPE2_0_I_SEG", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTPE2_0_I" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_IB->IBUFDS_GTPE2_0_IB_SEG": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTPE2_0_IB_SEG", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTPE2_0_IB" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT->>IBUFDS_GTPE2_0_MGTCLKOUT_MUX": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_0_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_O->GTPE2_COMMON_REFCLK0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_REFCLK0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTPE2_0_O" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_O->IBUFDS_GTPE2_0_MGTCLKOUT": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTPE2_0_MGTCLKOUT", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTPE2_0_O" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_0_ODIV2->IBUFDS_GTPE2_0_MGTCLKOUT": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTPE2_0_MGTCLKOUT", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTPE2_0_ODIV2" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_CLKTESTSIG_SEG->IBUFDS_GTPE2_1_CLKTESTSIG": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTPE2_1_CLKTESTSIG", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTPE2_1_CLKTESTSIG_SEG" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_I->IBUFDS_GTPE2_1_I_SEG": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTPE2_1_I_SEG", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTPE2_1_I" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_IB->IBUFDS_GTPE2_1_IB_SEG": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTPE2_1_IB_SEG", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTPE2_1_IB" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT->>IBUFDS_GTPE2_1_MGTCLKOUT_MUX": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_MGTCLKOUT_MUX->>HCLK_GTP_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_GTP_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "IBUFDS_GTPE2_1_MGTCLKOUT_MUX" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_O->GTPE2_COMMON_REFCLK1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTPE2_COMMON_REFCLK1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTPE2_1_O" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_O->IBUFDS_GTPE2_1_MGTCLKOUT": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTPE2_1_MGTCLKOUT", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTPE2_1_O" }, "GTP_COMMON_MID_LEFT.IBUFDS_GTPE2_1_ODIV2->IBUFDS_GTPE2_1_MGTCLKOUT": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTPE2_1_MGTCLKOUT", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTPE2_1_ODIV2" } }, "sites": [ { "name": "X0Y0", "prefix": "GTPE2_COMMON", "site_pins": { "BGBYPASSB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_BGBYPASSB" }, "BGMONITORENB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_BGMONITORENB" }, "BGPDB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_BGPDB" }, "BGRCALOVRD0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_BGRCALOVRD0" }, "BGRCALOVRD1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_BGRCALOVRD1" }, "BGRCALOVRD2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_BGRCALOVRD2" }, "BGRCALOVRD3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_BGRCALOVRD3" }, "BGRCALOVRD4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_BGRCALOVRD4" }, "BGRCALOVRDENB": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_BGRCALOVRDENB" }, "DMONITOROUT0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DMONITOROUT0" }, "DMONITOROUT1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DMONITOROUT1" }, "DMONITOROUT2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DMONITOROUT2" }, "DMONITOROUT3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DMONITOROUT3" }, "DMONITOROUT4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DMONITOROUT4" }, "DMONITOROUT5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DMONITOROUT5" }, "DMONITOROUT6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DMONITOROUT6" }, "DMONITOROUT7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DMONITOROUT7" }, "DRPADDR0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPADDR0" }, "DRPADDR1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPADDR1" }, "DRPADDR2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPADDR2" }, "DRPADDR3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPADDR3" }, "DRPADDR4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPADDR4" }, "DRPADDR5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPADDR5" }, "DRPADDR6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPADDR6" }, "DRPADDR7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPADDR7" }, "DRPCLK": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPCLK" }, "DRPDI0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI0" }, "DRPDI1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI1" }, "DRPDI2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI2" }, "DRPDI3": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI3" }, "DRPDI4": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI4" }, "DRPDI5": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI5" }, "DRPDI6": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI6" }, "DRPDI7": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI7" }, "DRPDI8": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI8" }, "DRPDI9": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI9" }, "DRPDI10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI10" }, "DRPDI11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI11" }, "DRPDI12": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI12" }, "DRPDI13": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI13" }, "DRPDI14": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI14" }, "DRPDI15": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPDI15" }, "DRPDO0": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO0" }, "DRPDO1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO1" }, "DRPDO2": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO2" }, "DRPDO3": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO3" }, "DRPDO4": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO4" }, "DRPDO5": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO5" }, "DRPDO6": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO6" }, "DRPDO7": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO7" }, "DRPDO8": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO8" }, "DRPDO9": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO9" }, "DRPDO10": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO10" }, "DRPDO11": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO11" }, "DRPDO12": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO12" }, "DRPDO13": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO13" }, "DRPDO14": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO14" }, "DRPDO15": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPDO15" }, "DRPEN": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPEN" }, "DRPRDY": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_DRPRDY" }, "DRPWE": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_DRPWE" }, "GTEASTREFCLK0": null, "GTEASTREFCLK1": null, "GTGREFCLK0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_GTGREFCLK0" }, "GTGREFCLK1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_GTGREFCLK1" }, "GTREFCLK0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_GTREFCLK0" }, "GTREFCLK1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_GTREFCLK1" }, "GTWESTREFCLK0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_GTWESTREFCLK0" }, "GTWESTREFCLK1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_GTWESTREFCLK1" }, "PLL0FBCLKLOST": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_PLL0FBCLKLOST" }, "PLL0LOCK": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_PLL0LOCK" }, "PLL0LOCKDETCLK": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_PLL0LOCKDETCLK" }, "PLL0LOCKEN": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_PLL0LOCKEN" }, "PLL0OUTCLK": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_PLL0OUTCLK" }, "PLL0OUTREFCLK": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_PLL0REFCLK" }, "PLL0PD": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_PLL0PD" }, "PLL0REFCLKLOST": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_PLL0REFCLKLOST" }, "PLL0REFCLKSEL0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_PLL0REFCLKSEL0" }, "PLL0REFCLKSEL1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_PLL0REFCLKSEL1" }, "PLL0REFCLKSEL2": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_PLL0REFCLKSEL2" }, "PLL0RESET": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_PLL0RESET" }, "PLL1FBCLKLOST": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_PLL1FBCLKLOST" }, "PLL1LOCK": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_PLL1LOCK" }, "PLL1LOCKDETCLK": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_PLL1LOCKDETCLK" }, "PLL1LOCKEN": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_PLL1LOCKEN" }, "PLL1OUTCLK": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_PLL1OUTCLK" }, "PLL1OUTREFCLK": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_PLL1REFCLK" }, "PLL1PD": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_PLL1PD" }, "PLL1REFCLKLOST": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "GTPE2_COMMON_PLL1REFCLKLOST" }, "PLL1REFCLKSEL0": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "GTPE2_COMMON_PLL1REFCLKSEL0" }, "PLL1REFCLKSEL1": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", 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"GTPE2_LOGIC_OUTS_B16_2": null, "GTPE2_LOGIC_OUTS_B16_3": null, "GTPE2_LOGIC_OUTS_B16_4": null, "GTPE2_LOGIC_OUTS_B16_5": null, "GTPE2_LOGIC_OUTS_B17_0": null, "GTPE2_LOGIC_OUTS_B17_1": null, "GTPE2_LOGIC_OUTS_B17_2": null, "GTPE2_LOGIC_OUTS_B17_3": null, "GTPE2_LOGIC_OUTS_B17_4": null, "GTPE2_LOGIC_OUTS_B17_5": null, "GTPE2_LOGIC_OUTS_B18_0": null, "GTPE2_LOGIC_OUTS_B18_1": null, "GTPE2_LOGIC_OUTS_B18_2": null, "GTPE2_LOGIC_OUTS_B18_3": null, "GTPE2_LOGIC_OUTS_B18_4": null, "GTPE2_LOGIC_OUTS_B18_5": null, "GTPE2_LOGIC_OUTS_B19_0": null, "GTPE2_LOGIC_OUTS_B19_1": null, "GTPE2_LOGIC_OUTS_B19_2": null, "GTPE2_LOGIC_OUTS_B19_3": null, "GTPE2_LOGIC_OUTS_B19_4": null, "GTPE2_LOGIC_OUTS_B19_5": null, "GTPE2_LOGIC_OUTS_B20_0": null, "GTPE2_LOGIC_OUTS_B20_1": null, "GTPE2_LOGIC_OUTS_B20_2": null, "GTPE2_LOGIC_OUTS_B20_3": null, "GTPE2_LOGIC_OUTS_B20_4": null, "GTPE2_LOGIC_OUTS_B20_5": null, "GTPE2_LOGIC_OUTS_B21_0": null, "GTPE2_LOGIC_OUTS_B21_1": null, "GTPE2_LOGIC_OUTS_B21_2": null, "GTPE2_LOGIC_OUTS_B21_3": null, "GTPE2_LOGIC_OUTS_B21_4": null, "GTPE2_LOGIC_OUTS_B21_5": null, "GTPE2_LOGIC_OUTS_B22_0": null, "GTPE2_LOGIC_OUTS_B22_1": null, "GTPE2_LOGIC_OUTS_B22_2": null, "GTPE2_LOGIC_OUTS_B22_3": null, "GTPE2_LOGIC_OUTS_B22_4": null, "GTPE2_LOGIC_OUTS_B22_5": null, "GTPE2_LOGIC_OUTS_B23_0": null, "GTPE2_LOGIC_OUTS_B23_1": null, "GTPE2_LOGIC_OUTS_B23_2": null, "GTPE2_LOGIC_OUTS_B23_3": null, "GTPE2_LOGIC_OUTS_B23_4": null, "GTPE2_LOGIC_OUTS_B23_5": null, "HCLK_GTP_CK_BUFHCLK0": null, "HCLK_GTP_CK_BUFHCLK1": null, "HCLK_GTP_CK_BUFHCLK2": null, "HCLK_GTP_CK_BUFHCLK3": null, "HCLK_GTP_CK_BUFHCLK4": null, "HCLK_GTP_CK_BUFHCLK5": null, "HCLK_GTP_CK_BUFHCLK6": null, "HCLK_GTP_CK_BUFHCLK7": null, "HCLK_GTP_CK_BUFHCLK8": null, "HCLK_GTP_CK_BUFHCLK9": null, "HCLK_GTP_CK_BUFHCLK10": null, "HCLK_GTP_CK_BUFHCLK11": null, "HCLK_GTP_CK_BUFRCLK0": null, "HCLK_GTP_CK_BUFRCLK1": null, "HCLK_GTP_CK_BUFRCLK2": null, "HCLK_GTP_CK_BUFRCLK3": null, "HCLK_GTP_CK_IN0": null, "HCLK_GTP_CK_IN1": null, "HCLK_GTP_CK_IN2": null, "HCLK_GTP_CK_IN3": null, "HCLK_GTP_CK_IN4": null, "HCLK_GTP_CK_IN5": null, "HCLK_GTP_CK_IN6": null, "HCLK_GTP_CK_IN7": null, "HCLK_GTP_CK_IN8": null, "HCLK_GTP_CK_IN9": null, "HCLK_GTP_CK_IN10": null, "HCLK_GTP_CK_IN11": null, "HCLK_GTP_CK_IN12": null, "HCLK_GTP_CK_IN13": null, "HCLK_GTP_CK_MUX0": null, "HCLK_GTP_CK_MUX1": null, "HCLK_GTP_CK_MUX2": null, "HCLK_GTP_CK_MUX3": null, "HCLK_GTP_CK_MUX4": null, "HCLK_GTP_CK_MUX5": null, "HCLK_GTP_CK_MUX6": null, "HCLK_GTP_CK_MUX7": null, "HCLK_GTP_CK_MUX8": null, "HCLK_GTP_CK_MUX9": null, "HCLK_GTP_CK_MUX10": null, "HCLK_GTP_CK_MUX11": null, "HCLK_GTP_CK_MUX12": null, "HCLK_GTP_CK_MUX13": null, "HCLK_GTP_REFCK_EASTCLK0": null, "HCLK_GTP_REFCK_EASTCLK1": null, "HCLK_GTP_REFCK_WESTCLK0": null, "HCLK_GTP_REFCK_WESTCLK1": null, "IBUFDS_GTPE2_0_CEB": { "cap": "0.100", "res": "0.000" }, "IBUFDS_GTPE2_0_CLKTESTSIG": { "cap": "0.100", "res": "0.000" }, "IBUFDS_GTPE2_0_CLKTESTSIG_SEG": null, "IBUFDS_GTPE2_0_I": { "cap": "0.100", "res": "0.000" }, "IBUFDS_GTPE2_0_IB": { "cap": "0.100", "res": "0.000" }, "IBUFDS_GTPE2_0_IB_SEG": { "cap": "0.100", "res": "0.000" }, "IBUFDS_GTPE2_0_I_SEG": { "cap": "0.100", "res": "0.000" }, "IBUFDS_GTPE2_0_MGTCLKOUT": null, "IBUFDS_GTPE2_0_MGTCLKOUT_MUX": null, "IBUFDS_GTPE2_0_O": null, "IBUFDS_GTPE2_0_ODIV2": null, "IBUFDS_GTPE2_1_CEB": { "cap": "0.100", "res": "0.000" }, "IBUFDS_GTPE2_1_CLKTESTSIG": { "cap": "0.100", "res": "0.000" }, "IBUFDS_GTPE2_1_CLKTESTSIG_SEG": null, "IBUFDS_GTPE2_1_I": { "cap": "0.100", "res": "0.000" }, "IBUFDS_GTPE2_1_IB": { "cap": "0.100", "res": "0.000" }, "IBUFDS_GTPE2_1_IB_SEG": { "cap": "0.100", "res": "0.000" }, "IBUFDS_GTPE2_1_I_SEG": { "cap": "0.100", "res": "0.000" }, "IBUFDS_GTPE2_1_MGTCLKOUT": null, "IBUFDS_GTPE2_1_MGTCLKOUT_MUX": null, "IBUFDS_GTPE2_1_O": null, "IBUFDS_GTPE2_1_ODIV2": null } }