{ "pips": { "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_IMUX_RC0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IMUX_RC0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP3_0" }, "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_RCLK_DIV_CLR0_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP3_0" }, "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_RCLK_DIV_CLR3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP3_0" }, "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_IMUX_RC3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IMUX_RC3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP3_1" }, "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_RCLK_DIV_CE0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP3_1" }, "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_RCLK_DIV_CE3_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP3_1" }, "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_IMUX_RC1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IMUX_RC1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP4_0" }, "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_RCLK_DIV_CLR1_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP4_0" }, "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_RCLK_DIV_CLR2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP4_0" }, "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_IMUX_RC2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IMUX_RC2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP4_1" }, "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_RCLK_DIV_CE1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP4_1" }, "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_RCLK_DIV_CE2_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP4_1" }, "LIOI3_TBYTESRC.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY1_CINVCTRL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP6_0" }, "LIOI3_TBYTESRC.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP6_1" }, "LIOI3_TBYTESRC.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI3_IDELAY1_IFDLY2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP7_0" }, "LIOI3_TBYTESRC.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI3_IDELAY0_IFDLY2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP7_1" }, "LIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC1_CLKDIV", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CLK0_0" }, "LIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CLK0_0" }, "LIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CLK0_1" }, "LIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CLK0_1" }, "LIOI3_TBYTESRC.IOI_CLK1_0->IOI_IDELAY1_C": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY1_C", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CLK1_0" }, "LIOI3_TBYTESRC.IOI_CLK1_1->IOI_IDELAY0_C": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CLK1_1" }, "LIOI3_TBYTESRC.IOI_CTRL0_0->IOI_OLOGIC1_SR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC1_SR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CTRL0_0" }, "LIOI3_TBYTESRC.IOI_CTRL0_1->IOI_OLOGIC0_SR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CTRL0_1" }, "LIOI3_TBYTESRC.IOI_CTRL1_0->IOI_ILOGIC1_SR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC1_SR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CTRL1_0" }, "LIOI3_TBYTESRC.IOI_CTRL1_1->IOI_ILOGIC0_SR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CTRL1_1" }, "LIOI3_TBYTESRC.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI3_IDELAY1_IFDLY0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_FAN4_0" }, "LIOI3_TBYTESRC.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI3_IDELAY0_IFDLY0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_FAN4_1" }, "LIOI3_TBYTESRC.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI3_IDELAY1_IFDLY1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_FAN5_0" }, "LIOI3_TBYTESRC.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI3_IDELAY0_IFDLY1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_FAN5_1" }, "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS20_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS1_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS19_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS15_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS11_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT0" }, "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT1" }, "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT2" }, "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT3" }, "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT4" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.004", "0.015", "0.027", "0.030" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_LOGIC_OUTS18_1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.004", "0.015", "0.027", "0.030" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_ILOGIC0_O" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_O->LIOI_I2GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI_I2GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_O" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS0_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q1" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS23_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q2" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS9_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q3" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS10_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q4" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS14_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q5" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS3_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q6" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS7_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q7" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS8_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q8" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.004", "0.015", "0.027", "0.030" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.004", "0.015", "0.027", "0.030" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_ILOGIC1_O" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC1_Q1" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC1_Q2" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC1_Q3" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC1_Q4" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC1_Q5" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC1_Q6" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC1_Q7" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC1_Q8" }, "LIOI3_TBYTESRC.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC1_BITSLIP", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX0_0" }, "LIOI3_TBYTESRC.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX0_1" }, "LIOI3_TBYTESRC.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC1_TCE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX1_0" }, "LIOI3_TBYTESRC.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX1_1" }, "LIOI3_TBYTESRC.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX4_0" }, "LIOI3_TBYTESRC.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX4_1" }, "LIOI3_TBYTESRC.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC1_CE1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX5_0" }, "LIOI3_TBYTESRC.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX5_1" }, "LIOI3_TBYTESRC.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI_DCI_T_TERM1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX6_0" }, "LIOI3_TBYTESRC.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI_DCI_T_TERM0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX6_1" }, "LIOI3_TBYTESRC.IOI_IMUX7_0->IOI_OLOGIC1_T2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC1_T2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX7_0" }, "LIOI3_TBYTESRC.IOI_IMUX7_1->IOI_OLOGIC0_T2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX7_1" }, "LIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_TBYTESRC.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_TBYTESRC.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX8_1" }, "LIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX8_1" }, "LIOI3_TBYTESRC.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX8_1" }, "LIOI3_TBYTESRC.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX8_1" }, "LIOI3_TBYTESRC.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI_IBUF_DISABLE1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX9_0" }, "LIOI3_TBYTESRC.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI_IBUF_DISABLE0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX9_1" }, "LIOI3_TBYTESRC.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX10_0" }, "LIOI3_TBYTESRC.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX10_1" }, "LIOI3_TBYTESRC.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY1_REGRST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX12_0" }, "LIOI3_TBYTESRC.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX12_1" }, "LIOI3_TBYTESRC.IOI_IMUX13_0->IOI_OLOGIC1_T3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC1_T3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX13_0" }, "LIOI3_TBYTESRC.IOI_IMUX13_1->IOI_OLOGIC0_T3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX13_1" }, "LIOI3_TBYTESRC.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC1_CE2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX14_0" }, "LIOI3_TBYTESRC.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX14_1" }, "LIOI3_TBYTESRC.IOI_IMUX15_0->IOI_OLOGIC1_T1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC1_T1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX15_0" }, "LIOI3_TBYTESRC.IOI_IMUX15_1->IOI_OLOGIC0_T1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX15_1" }, "LIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX20_0" }, "LIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX20_0" }, "LIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], 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"LIOI3_TBYTESRC.IOI_IMUX21_1->IOI_OLOGIC0_T4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX21_1" }, "LIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX22_0" }, "LIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX22_0" }, "LIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX22_1" }, "LIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX22_1" }, "LIOI3_TBYTESRC.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY1_DATAIN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX25_0" }, "LIOI3_TBYTESRC.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX25_1" }, "LIOI3_TBYTESRC.IOI_IMUX26_0->IOI_IDELAY1_INC": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY1_INC", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX26_0" }, "LIOI3_TBYTESRC.IOI_IMUX26_1->IOI_IDELAY0_INC": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX26_1" }, "LIOI3_TBYTESRC.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC1_OCE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX29_0" }, "LIOI3_TBYTESRC.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX29_1" }, "LIOI3_TBYTESRC.IOI_IMUX30_0->IOI_IDELAY1_LD": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY1_LD", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX30_0" }, "LIOI3_TBYTESRC.IOI_IMUX30_1->IOI_IDELAY0_LD": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX30_1" }, "LIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLKM_1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX31_0" }, "LIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLK_1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX31_0" }, "LIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX31_1" }, "LIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.123", "0.142", "0.386", "0.393" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX31_1" }, "LIOI3_TBYTESRC.IOI_IMUX32_0->IOI_IDELAY1_CE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY1_CE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX32_0" }, "LIOI3_TBYTESRC.IOI_IMUX32_1->IOI_IDELAY0_CE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX32_1" }, "LIOI3_TBYTESRC.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY1_LDPIPEEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX33_0" }, "LIOI3_TBYTESRC.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX33_1" }, "LIOI3_TBYTESRC.IOI_IMUX34_0->IOI_OLOGIC1_D1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC1_D1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX34_0" }, "LIOI3_TBYTESRC.IOI_IMUX34_1->IOI_OLOGIC0_D1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX34_1" }, "LIOI3_TBYTESRC.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX35_0" }, "LIOI3_TBYTESRC.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX35_1" }, "LIOI3_TBYTESRC.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX36_0" }, "LIOI3_TBYTESRC.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX36_1" }, "LIOI3_TBYTESRC.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX37_0" }, "LIOI3_TBYTESRC.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX37_1" }, "LIOI3_TBYTESRC.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX38_0" }, "LIOI3_TBYTESRC.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX38_1" }, "LIOI3_TBYTESRC.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": 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"src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_1": { "can_invert": "0", "dst_to_src": { "delay": [ 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"src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.079", "0.083" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLKM_0" }, "LIOI3_TBYTESRC.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLKM_0" }, "LIOI3_TBYTESRC.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLKM_1" }, "LIOI3_TBYTESRC.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLKM_1" }, "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLK_0" }, "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLK_0" }, "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLK_0" }, "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLK_0" }, "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC1_OCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLK_1" }, "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLK_1" }, "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC1_CLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLK_1" }, "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLK_1" }, "LIOI3_TBYTESRC.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.331", "0.999", "1.156" ], "in_cap": null, "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_OFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.100", "0.331", "0.999", "1.156" ], "in_cap": null, "res": "0.0" }, "src_wire": "IOI_OLOGIC0_D1" }, "LIOI3_TBYTESRC.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.331", "0.999", "1.156" ], "in_cap": null, "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_OQ", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.100", "0.331", "0.999", "1.156" ], "in_cap": null, "res": "0.0" }, "src_wire": "IOI_OLOGIC0_D1" }, "LIOI3_TBYTESRC.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS5_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" }, "LIOI3_TBYTESRC.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.350", "0.403", "0.958", "1.102" ], "in_cap": null, "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_TFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.350", "0.403", "0.958", "1.102" ], "in_cap": null, "res": "0.0" }, "src_wire": "IOI_OLOGIC0_T1" }, "LIOI3_TBYTESRC.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { "can_invert": "0", "dst_to_src": { "delay": [ "0.350", "0.403", "0.958", "1.102" ], "in_cap": null, "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_TQ", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.350", "0.403", "0.958", "1.102" ], "in_cap": null, "res": "0.0" }, "src_wire": "IOI_OLOGIC0_T1" }, "LIOI3_TBYTESRC.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.331", "0.999", "1.156" ], "in_cap": null, "res": "0.0" }, "dst_wire": "LIOI_OLOGIC1_OFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.100", "0.331", "0.999", "1.156" ], "in_cap": null, "res": "0.0" }, "src_wire": "IOI_OLOGIC1_D1" }, "LIOI3_TBYTESRC.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.331", "0.999", "1.156" ], "in_cap": null, "res": "0.0" }, "dst_wire": "LIOI_OLOGIC1_OQ", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.100", "0.331", "0.999", "1.156" ], "in_cap": null, "res": "0.0" }, "src_wire": "IOI_OLOGIC1_D1" }, "LIOI3_TBYTESRC.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS5_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OLOGIC1_IOCLKGLITCH" }, "LIOI3_TBYTESRC.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.350", "0.403", "0.958", "1.102" ], "in_cap": null, "res": "0.0" }, "dst_wire": "LIOI_OLOGIC1_TFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.350", "0.403", "0.958", "1.102" ], "in_cap": null, "res": "0.0" }, "src_wire": "IOI_OLOGIC1_T1" }, "LIOI3_TBYTESRC.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { "can_invert": "0", "dst_to_src": { "delay": [ "0.350", "0.403", "0.958", "1.102" ], "in_cap": null, "res": "0.0" }, "dst_wire": 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"IOI_PHASER_TO_IO_ICLK" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.029", "0.032", "0.085", "0.092" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.029", "0.032", "0.085", "0.092" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", "dst_to_src": { "delay": [ "0.029", "0.032", "0.085", "0.092" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.029", "0.032", "0.085", "0.092" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", "dst_to_src": { "delay": [ "0.029", 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"LIOI3_IDELAY1_IFDLY1": null, "LIOI3_IDELAY1_IFDLY2": null, "LIOI_DCI_T_TERM0": null, "LIOI_DCI_T_TERM1": null, "LIOI_DIFF_TERM_INT_EN": null, "LIOI_I0": null, "LIOI_I1": null, "LIOI_I2GCLK_BOT1": null, "LIOI_I2GCLK_TOP0": null, "LIOI_I2GCLK_TOP1": null, "LIOI_IBUF0": null, "LIOI_IBUF1": null, "LIOI_IBUF_DISABLE0": null, "LIOI_IBUF_DISABLE1": null, "LIOI_IDELAY0_DATAOUT": null, "LIOI_IDELAY0_IDATAIN": null, "LIOI_IDELAY1_DATAOUT": null, "LIOI_IDELAY1_IDATAIN": null, "LIOI_ILOGIC0_D": null, "LIOI_ILOGIC0_DDLY": null, "LIOI_ILOGIC0_OFB": null, "LIOI_ILOGIC0_TFB": null, "LIOI_ILOGIC1_D": null, "LIOI_ILOGIC1_DDLY": null, "LIOI_ILOGIC1_OFB": null, "LIOI_ILOGIC1_TFB": null, "LIOI_ISIN10": null, "LIOI_ISIN11": null, "LIOI_ISIN20": null, "LIOI_ISIN21": null, "LIOI_ISOUT10": null, "LIOI_ISOUT11": null, "LIOI_ISOUT20": null, "LIOI_ISOUT21": null, "LIOI_KEEPER_INT_EN_0": null, "LIOI_KEEPER_INT_EN_1": null, "LIOI_O0": null, "LIOI_O1": null, "LIOI_ODELAY0_DATAOUT": null, "LIOI_ODELAY0_ODATAIN": null, "LIOI_ODELAY0_OFDLY0": null, "LIOI_ODELAY0_OFDLY1": null, "LIOI_ODELAY0_OFDLY2": null, "LIOI_ODELAY1_DATAOUT": null, "LIOI_ODELAY1_ODATAIN": null, "LIOI_ODELAY1_OFDLY0": null, "LIOI_ODELAY1_OFDLY1": null, "LIOI_ODELAY1_OFDLY2": null, "LIOI_OLOGIC0_CLKDIVF": null, "LIOI_OLOGIC0_OFB": null, "LIOI_OLOGIC0_OQ": null, "LIOI_OLOGIC0_TFB": null, "LIOI_OLOGIC0_TFB_LOCAL": null, "LIOI_OLOGIC0_TQ": null, "LIOI_OLOGIC1_CLKDIVF": null, "LIOI_OLOGIC1_OFB": null, "LIOI_OLOGIC1_OQ": null, "LIOI_OLOGIC1_TFB": null, "LIOI_OLOGIC1_TFB_LOCAL": null, "LIOI_OLOGIC1_TQ": null, "LIOI_OSIN10": null, "LIOI_OSIN11": null, "LIOI_OSIN20": null, "LIOI_OSIN21": null, "LIOI_OSOUT10": null, "LIOI_OSOUT11": null, "LIOI_OSOUT20": null, "LIOI_OSOUT21": null, "LIOI_PD_INT_EN_0": null, "LIOI_PD_INT_EN_1": null, "LIOI_PU_INT_EN_0": null, "LIOI_PU_INT_EN_1": null, "LIOI_T0": null, "LIOI_T1": null } }