{
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            "src_to_dst": {
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            "src_wire": "PCIE_CFGDEVCONTROLEXTTAGEN"
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                "in_cap": null,
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            "src_to_dst": {
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            "src_to_dst": {
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            "src_to_dst": {
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            "src_to_dst": {
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            "src_to_dst": {
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            "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ1"
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            "src_to_dst": {
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            "src_wire": "PCIE_CFGDEVCONTROLNOSNOOPEN"
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            "src_to_dst": {
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                "res": "0.000"
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            "src_wire": "PCIE_CFGDEVCONTROLPHANTOMEN"
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                "res": "0.000"
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            "is_pseudo": "0",
            "src_to_dst": {
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                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_CFGDEVCONTROLURERRREPORTINGEN"
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        "PCIE_BOT.PCIE_CFGDEVSTATUSCORRERRDETECTED->PCIE_LOGIC_OUTS_B16_L_9": {
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                "res": "0.000"
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            "is_pseudo": "0",
            "src_to_dst": {
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                "res": "0.000"
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            "src_wire": "PCIE_CFGDEVSTATUSCORRERRDETECTED"
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            "src_to_dst": {
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            "src_wire": "PCIE_CFGDEVSTATUSFATALERRDETECTED"
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                "res": "0.000"
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            "src_wire": "PCIE_CFGDEVSTATUSNONFATALERRDETECTED"
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            "dst_wire": "PCIE_LOGIC_OUTS_B17_L_10",
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            "src_to_dst": {
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                "res": "0.000"
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            "src_wire": "PCIE_CFGDEVSTATUSURDETECTED"
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                "res": "0.000"
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            "src_to_dst": {
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                "res": "0.000"
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            "src_wire": "PCIE_CFGERRAERHEADERLOGSETN"
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            "src_wire": "PCIE_CFGERRCPLRDYN"
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                "in_cap": null,
                "res": "0.000"
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            "dst_wire": "PCIE_LOGIC_OUTS_B17_L_5",
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            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
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                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_CFGINTERRUPTDO0"
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                "in_cap": null,
                "res": "0.000"
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            "dst_wire": "PCIE_LOGIC_OUTS_B12_L_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
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                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_CFGINTERRUPTDO1"
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        "PCIE_BOT.PCIE_CFGINTERRUPTDO2->PCIE_LOGIC_OUTS_B13_L_8": {
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            "dst_to_src": {
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                "in_cap": null,
                "res": "0.000"
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            "dst_wire": "PCIE_LOGIC_OUTS_B13_L_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
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                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_CFGINTERRUPTDO2"
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        "PCIE_BOT.PCIE_CFGINTERRUPTDO3->PCIE_LOGIC_OUTS_B14_L_8": {
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            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
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            "dst_wire": "PCIE_LOGIC_OUTS_B14_L_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGINTERRUPTDO3"
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        "PCIE_BOT.PCIE_CFGINTERRUPTDO4->PCIE_LOGIC_OUTS_B15_L_8": {
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            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B15_L_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_CFGINTERRUPTDO4"
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        "PCIE_BOT.PCIE_CFGINTERRUPTDO5->PCIE_LOGIC_OUTS_B12_L_9": {
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            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B12_L_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGINTERRUPTDO5"
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        "PCIE_BOT.PCIE_CFGINTERRUPTDO6->PCIE_LOGIC_OUTS_B13_L_9": {
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            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
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            "dst_wire": "PCIE_LOGIC_OUTS_B13_L_9",
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            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_CFGINTERRUPTDO6"
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        "PCIE_BOT.PCIE_CFGINTERRUPTDO7->PCIE_LOGIC_OUTS_B14_L_9": {
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            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
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            "dst_wire": "PCIE_LOGIC_OUTS_B14_L_9",
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            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_CFGINTERRUPTDO7"
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        "PCIE_BOT.PCIE_CFGINTERRUPTMMENABLE0->PCIE_LOGIC_OUTS_B16_R_10": {
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                "delay": null,
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                "res": "0.000"
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            "dst_wire": "PCIE_LOGIC_OUTS_B16_R_10",
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            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
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                "res": "0.000"
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            "src_wire": "PCIE_CFGINTERRUPTMMENABLE0"
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        "PCIE_BOT.PCIE_CFGINTERRUPTMMENABLE1->PCIE_LOGIC_OUTS_B17_R_10": {
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        "PCIE_BOT.PCIE_CFGMGMTDO9->PCIE_LOGIC_OUTS_B14_R_12": {
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        "PCIE_BOT.PCIE_CFGMGMTRDWRDONEN->PCIE_LOGIC_OUTS_B16_R_12": {
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            "src_wire": "PCIE_CFGMGMTRDWRDONEN"
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            "src_wire": "PCIE_CFGMSGDATA0"
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        "PCIE_BOT.PCIE_CFGMSGDATA1->PCIE_LOGIC_OUTS_B13_L_10": {
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            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA1"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA2->PCIE_LOGIC_OUTS_B14_L_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B14_L_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA2"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA3->PCIE_LOGIC_OUTS_B15_L_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B15_L_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA3"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA4->PCIE_LOGIC_OUTS_B17_L_11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B17_L_11",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA4"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA5->PCIE_LOGIC_OUTS_B18_L_11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B18_L_11",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA5"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA6->PCIE_LOGIC_OUTS_B16_L_12": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B16_L_12",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA6"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA7->PCIE_LOGIC_OUTS_B17_L_12": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B17_L_12",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA7"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA8->PCIE_LOGIC_OUTS_B18_L_12": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B18_L_12",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA8"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA9->PCIE_LOGIC_OUTS_B19_L_12": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B19_L_12",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA9"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA10->PCIE_LOGIC_OUTS_B12_L_14": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B12_L_14",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA10"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA11->PCIE_LOGIC_OUTS_B14_L_14": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B14_L_14",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA11"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA12->PCIE_LOGIC_OUTS_B16_L_14": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B16_L_14",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA12"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA13->PCIE_LOGIC_OUTS_B17_L_14": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B17_L_14",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA13"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA14->PCIE_LOGIC_OUTS_B12_L_15": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B12_L_15",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA14"
        },
        "PCIE_BOT.PCIE_CFGMSGDATA15->PCIE_LOGIC_OUTS_B13_L_15": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B13_L_15",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGDATA15"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVED->PCIE_LOGIC_OUTS_B15_L_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B15_L_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVED"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTA->PCIE_LOGIC_OUTS_B10_L_16": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B10_L_16",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTA"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTB->PCIE_LOGIC_OUTS_B14_L_16": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B14_L_16",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTB"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTC->PCIE_LOGIC_OUTS_B17_L_17": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B17_L_17",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTC"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTD->PCIE_LOGIC_OUTS_B19_L_17": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B19_L_17",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTD"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTA->PCIE_LOGIC_OUTS_B12_L_16": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B12_L_16",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTA"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTB->PCIE_LOGIC_OUTS_B15_L_17": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B15_L_17",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTB"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTC->PCIE_LOGIC_OUTS_B18_L_17": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B18_L_17",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTC"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTD->PCIE_LOGIC_OUTS_B12_L_18": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B12_L_18",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTD"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRCOR->PCIE_LOGIC_OUTS_B14_L_15": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B14_L_15",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDERRCOR"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRFATAL->PCIE_LOGIC_OUTS_B8_L_16": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B8_L_16",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDERRFATAL"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRNONFATAL->PCIE_LOGIC_OUTS_B15_L_15": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B15_L_15",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDERRNONFATAL"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMASNAK->PCIE_LOGIC_OUTS_B10_L_19": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B10_L_19",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDPMASNAK"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMETO->PCIE_LOGIC_OUTS_B17_L_18": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B17_L_18",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDPMETO"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMETOACK->PCIE_LOGIC_OUTS_B16_L_18": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B16_L_18",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDPMETOACK"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMPME->PCIE_LOGIC_OUTS_B14_L_18": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B14_L_18",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDPMPME"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT->PCIE_LOGIC_OUTS_B8_L_19": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B8_L_19",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT"
        },
        "PCIE_BOT.PCIE_CFGMSGRECEIVEDUNLOCK->PCIE_LOGIC_OUTS_B9_L_19": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B9_L_19",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGMSGRECEIVEDUNLOCK"
        },
        "PCIE_BOT.PCIE_CFGPCIELINKSTATE0->PCIE_LOGIC_OUTS_B11_L_19": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B11_L_19",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGPCIELINKSTATE0"
        },
        "PCIE_BOT.PCIE_CFGROOTCONTROLPMEINTEN->PCIE_LOGIC_OUTS_B16_L_19": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B16_L_19",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGROOTCONTROLPMEINTEN"
        },
        "PCIE_BOT.PCIE_CFGROOTCONTROLSYSERRCORRERREN->PCIE_LOGIC_OUTS_B20_L_16": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B20_L_16",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGROOTCONTROLSYSERRCORRERREN"
        },
        "PCIE_BOT.PCIE_CFGROOTCONTROLSYSERRFATALERREN->PCIE_LOGIC_OUTS_B22_L_18": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B22_L_18",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_CFGROOTCONTROLSYSERRFATALERREN"
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            "dst_wire": "PCIE_CFGPMFORCESTATE0",
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            "dst_wire": "PCIE_CFGPMSENDPMETON",
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            "dst_wire": "PCIE_CFGDSN0",
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            "dst_wire": "PCIE_CFGDSN4",
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGDSN20",
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            "dst_wire": "PCIE_CFGDSN24",
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGDSN28",
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGDSN32",
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            "src_to_dst": {
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGDSN36",
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            "src_to_dst": {
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            "dst_wire": "PCIE_CFGDSN40",
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            "src_to_dst": {
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGDSN44",
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            "src_to_dst": {
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                "res": "0.000"
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            "src_wire": "PCIE_IMUX11_L_16"
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGDSN48",
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            "dst_wire": "PCIE_CFGDSN52",
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            "src_to_dst": {
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            "src_to_dst": {
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                "res": "0.000"
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            "dst_wire": "PCIE_TRNTD90",
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            "src_to_dst": {
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                "res": "0.000"
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            "dst_wire": "PCIE_TRNTD86",
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            "dst_wire": "PCIE_CFGMGMTDI5",
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGERRAERHEADERLOG57",
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGERRAERHEADERLOG50",
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGERRAERHEADERLOG40",
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGERRAERHEADERLOG34",
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            "src_wire": "PCIE_IMUX11_R_9"
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGERRAERHEADERLOG32",
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGERRAERHEADERLOG28",
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            "src_wire": "PCIE_IMUX11_R_11"
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGERRAERHEADERLOG24",
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                "res": "0.000"
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGERRAERHEADERLOG20",
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                "res": "0.000"
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            "src_wire": "PCIE_IMUX11_R_13"
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                "res": "0.000"
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            "dst_wire": "PCIE_CFGERRAERHEADERLOG16",
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                "res": "0.000"
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                "in_cap": null,
                "res": "0.000"
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            "dst_wire": "PCIE_CFGERRECRCN",
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                "res": "0.000"
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                "delay": null,
                "in_cap": null,
                "res": "0.000"
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            "dst_wire": "PCIE_CFGERRPOISONEDN",
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            "src_to_dst": {
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                "in_cap": null,
                "res": "0.000"
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            "src_wire": "PCIE_IMUX11_R_16"
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                "res": "0.000"
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                "in_cap": null,
                "res": "0.000"
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                "res": "0.000"
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                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B3_L_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_TRNTBUFAV3"
        },
        "PCIE_BOT.PCIE_TRNTBUFAV4->PCIE_LOGIC_OUTS_B5_L_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B5_L_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_TRNTBUFAV4"
        },
        "PCIE_BOT.PCIE_TRNTBUFAV5->PCIE_LOGIC_OUTS_B7_L_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B7_L_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_TRNTBUFAV5"
        },
        "PCIE_BOT.PCIE_TRNTCFGREQ->PCIE_LOGIC_OUTS_B0_L_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B0_L_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_TRNTCFGREQ"
        },
        "PCIE_BOT.PCIE_TRNTDLLPDSTRDY->PCIE_LOGIC_OUTS_B11_L_11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B11_L_11",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_TRNTDLLPDSTRDY"
        },
        "PCIE_BOT.PCIE_TRNTDSTRDY0->PCIE_LOGIC_OUTS_B1_R_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B1_R_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_TRNTDSTRDY0"
        },
        "PCIE_BOT.PCIE_TRNTDSTRDY1->PCIE_LOGIC_OUTS_B1_R_15": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B1_R_15",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_TRNTDSTRDY1"
        },
        "PCIE_BOT.PCIE_TRNTDSTRDY2->PCIE_LOGIC_OUTS_B3_R_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B3_R_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_TRNTDSTRDY2"
        },
        "PCIE_BOT.PCIE_TRNTERRDROP->PCIE_LOGIC_OUTS_B2_L_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B2_L_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_TRNTERRDROP"
        },
        "PCIE_BOT.PCIE_USERRSTN->PCIE_LOGIC_OUTS_B12_R_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "PCIE_LOGIC_OUTS_B12_R_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "PCIE_USERRSTN"
        }
    },
    "sites": [
        {
            "name": "X0Y0",
            "prefix": "PCIE",
            "site_pins": {
                "CFGAERECRCCHECKEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGAERECRCCHECKEN"
                },
                "CFGAERECRCGENEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGAERECRCGENEN"
                },
                "CFGAERINTERRUPTMSGNUM0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGAERINTERRUPTMSGNUM0"
                },
                "CFGAERINTERRUPTMSGNUM1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGAERINTERRUPTMSGNUM1"
                },
                "CFGAERINTERRUPTMSGNUM2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGAERINTERRUPTMSGNUM2"
                },
                "CFGAERINTERRUPTMSGNUM3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGAERINTERRUPTMSGNUM3"
                },
                "CFGAERINTERRUPTMSGNUM4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGAERINTERRUPTMSGNUM4"
                },
                "CFGAERROOTERRCORRERRRECEIVED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGAERROOTERRCORRERRRECEIVED"
                },
                "CFGAERROOTERRCORRERRREPORTINGEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGAERROOTERRCORRERRREPORTINGEN"
                },
                "CFGAERROOTERRFATALERRRECEIVED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGAERROOTERRFATALERRRECEIVED"
                },
                "CFGAERROOTERRFATALERRREPORTINGEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGAERROOTERRFATALERRREPORTINGEN"
                },
                "CFGAERROOTERRNONFATALERRRECEIVED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGAERROOTERRNONFATALERRRECEIVED"
                },
                "CFGAERROOTERRNONFATALERRREPORTINGEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGAERROOTERRNONFATALERRREPORTINGEN"
                },
                "CFGBRIDGESERREN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGBRIDGESERREN"
                },
                "CFGCOMMANDBUSMASTERENABLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGCOMMANDBUSMASTERENABLE"
                },
                "CFGCOMMANDINTERRUPTDISABLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGCOMMANDINTERRUPTDISABLE"
                },
                "CFGCOMMANDIOENABLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGCOMMANDIOENABLE"
                },
                "CFGCOMMANDMEMENABLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGCOMMANDMEMENABLE"
                },
                "CFGCOMMANDSERREN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGCOMMANDSERREN"
                },
                "CFGDEVCONTROL2ARIFORWARDEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROL2ARIFORWARDEN"
                },
                "CFGDEVCONTROL2ATOMICEGRESSBLOCK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROL2ATOMICEGRESSBLOCK"
                },
                "CFGDEVCONTROL2ATOMICREQUESTEREN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROL2ATOMICREQUESTEREN"
                },
                "CFGDEVCONTROL2CPLTIMEOUTDIS": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROL2CPLTIMEOUTDIS"
                },
                "CFGDEVCONTROL2CPLTIMEOUTVAL0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL0"
                },
                "CFGDEVCONTROL2CPLTIMEOUTVAL1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL1"
                },
                "CFGDEVCONTROL2CPLTIMEOUTVAL2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL2"
                },
                "CFGDEVCONTROL2CPLTIMEOUTVAL3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL3"
                },
                "CFGDEVCONTROL2IDOCPLEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROL2IDOCPLEN"
                },
                "CFGDEVCONTROL2IDOREQEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROL2IDOREQEN"
                },
                "CFGDEVCONTROL2LTREN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROL2LTREN"
                },
                "CFGDEVCONTROL2TLPPREFIXBLOCK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK"
                },
                "CFGDEVCONTROLAUXPOWEREN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLAUXPOWEREN"
                },
                "CFGDEVCONTROLCORRERRREPORTINGEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN"
                },
                "CFGDEVCONTROLENABLERO": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLENABLERO"
                },
                "CFGDEVCONTROLEXTTAGEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLEXTTAGEN"
                },
                "CFGDEVCONTROLFATALERRREPORTINGEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN"
                },
                "CFGDEVCONTROLMAXPAYLOAD0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD0"
                },
                "CFGDEVCONTROLMAXPAYLOAD1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD1"
                },
                "CFGDEVCONTROLMAXPAYLOAD2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD2"
                },
                "CFGDEVCONTROLMAXREADREQ0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLMAXREADREQ0"
                },
                "CFGDEVCONTROLMAXREADREQ1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLMAXREADREQ1"
                },
                "CFGDEVCONTROLMAXREADREQ2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLMAXREADREQ2"
                },
                "CFGDEVCONTROLNONFATALREPORTINGEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN"
                },
                "CFGDEVCONTROLNOSNOOPEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLNOSNOOPEN"
                },
                "CFGDEVCONTROLPHANTOMEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLPHANTOMEN"
                },
                "CFGDEVCONTROLURERRREPORTINGEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVCONTROLURERRREPORTINGEN"
                },
                "CFGDEVID0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID0"
                },
                "CFGDEVID1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID1"
                },
                "CFGDEVID2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID2"
                },
                "CFGDEVID3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID3"
                },
                "CFGDEVID4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID4"
                },
                "CFGDEVID5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID5"
                },
                "CFGDEVID6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID6"
                },
                "CFGDEVID7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID7"
                },
                "CFGDEVID8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID8"
                },
                "CFGDEVID9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID9"
                },
                "CFGDEVID10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID10"
                },
                "CFGDEVID11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID11"
                },
                "CFGDEVID12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID12"
                },
                "CFGDEVID13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID13"
                },
                "CFGDEVID14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID14"
                },
                "CFGDEVID15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDEVID15"
                },
                "CFGDEVSTATUSCORRERRDETECTED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVSTATUSCORRERRDETECTED"
                },
                "CFGDEVSTATUSFATALERRDETECTED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVSTATUSFATALERRDETECTED"
                },
                "CFGDEVSTATUSNONFATALERRDETECTED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVSTATUSNONFATALERRDETECTED"
                },
                "CFGDEVSTATUSURDETECTED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGDEVSTATUSURDETECTED"
                },
                "CFGDSBUSNUMBER0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSBUSNUMBER0"
                },
                "CFGDSBUSNUMBER1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSBUSNUMBER1"
                },
                "CFGDSBUSNUMBER2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSBUSNUMBER2"
                },
                "CFGDSBUSNUMBER3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSBUSNUMBER3"
                },
                "CFGDSBUSNUMBER4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSBUSNUMBER4"
                },
                "CFGDSBUSNUMBER5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSBUSNUMBER5"
                },
                "CFGDSBUSNUMBER6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSBUSNUMBER6"
                },
                "CFGDSBUSNUMBER7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSBUSNUMBER7"
                },
                "CFGDSDEVICENUMBER0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSDEVICENUMBER0"
                },
                "CFGDSDEVICENUMBER1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSDEVICENUMBER1"
                },
                "CFGDSDEVICENUMBER2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSDEVICENUMBER2"
                },
                "CFGDSDEVICENUMBER3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSDEVICENUMBER3"
                },
                "CFGDSDEVICENUMBER4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSDEVICENUMBER4"
                },
                "CFGDSFUNCTIONNUMBER0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSFUNCTIONNUMBER0"
                },
                "CFGDSFUNCTIONNUMBER1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSFUNCTIONNUMBER1"
                },
                "CFGDSFUNCTIONNUMBER2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSFUNCTIONNUMBER2"
                },
                "CFGDSN0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN0"
                },
                "CFGDSN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN1"
                },
                "CFGDSN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN2"
                },
                "CFGDSN3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN3"
                },
                "CFGDSN4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN4"
                },
                "CFGDSN5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN5"
                },
                "CFGDSN6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN6"
                },
                "CFGDSN7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN7"
                },
                "CFGDSN8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN8"
                },
                "CFGDSN9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN9"
                },
                "CFGDSN10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN10"
                },
                "CFGDSN11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN11"
                },
                "CFGDSN12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN12"
                },
                "CFGDSN13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN13"
                },
                "CFGDSN14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN14"
                },
                "CFGDSN15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN15"
                },
                "CFGDSN16": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN16"
                },
                "CFGDSN17": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN17"
                },
                "CFGDSN18": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN18"
                },
                "CFGDSN19": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN19"
                },
                "CFGDSN20": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN20"
                },
                "CFGDSN21": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN21"
                },
                "CFGDSN22": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN22"
                },
                "CFGDSN23": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN23"
                },
                "CFGDSN24": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN24"
                },
                "CFGDSN25": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN25"
                },
                "CFGDSN26": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN26"
                },
                "CFGDSN27": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN27"
                },
                "CFGDSN28": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN28"
                },
                "CFGDSN29": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN29"
                },
                "CFGDSN30": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN30"
                },
                "CFGDSN31": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN31"
                },
                "CFGDSN32": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN32"
                },
                "CFGDSN33": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN33"
                },
                "CFGDSN34": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN34"
                },
                "CFGDSN35": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN35"
                },
                "CFGDSN36": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN36"
                },
                "CFGDSN37": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN37"
                },
                "CFGDSN38": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN38"
                },
                "CFGDSN39": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN39"
                },
                "CFGDSN40": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN40"
                },
                "CFGDSN41": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN41"
                },
                "CFGDSN42": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN42"
                },
                "CFGDSN43": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN43"
                },
                "CFGDSN44": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN44"
                },
                "CFGDSN45": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN45"
                },
                "CFGDSN46": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN46"
                },
                "CFGDSN47": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN47"
                },
                "CFGDSN48": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN48"
                },
                "CFGDSN49": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN49"
                },
                "CFGDSN50": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN50"
                },
                "CFGDSN51": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN51"
                },
                "CFGDSN52": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN52"
                },
                "CFGDSN53": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN53"
                },
                "CFGDSN54": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN54"
                },
                "CFGDSN55": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN55"
                },
                "CFGDSN56": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN56"
                },
                "CFGDSN57": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN57"
                },
                "CFGDSN58": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN58"
                },
                "CFGDSN59": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN59"
                },
                "CFGDSN60": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN60"
                },
                "CFGDSN61": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN61"
                },
                "CFGDSN62": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN62"
                },
                "CFGDSN63": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGDSN63"
                },
                "CFGERRACSN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRACSN"
                },
                "CFGERRAERHEADERLOG0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG0"
                },
                "CFGERRAERHEADERLOG1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG1"
                },
                "CFGERRAERHEADERLOG2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG2"
                },
                "CFGERRAERHEADERLOG3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG3"
                },
                "CFGERRAERHEADERLOG4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG4"
                },
                "CFGERRAERHEADERLOG5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG5"
                },
                "CFGERRAERHEADERLOG6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG6"
                },
                "CFGERRAERHEADERLOG7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG7"
                },
                "CFGERRAERHEADERLOG8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG8"
                },
                "CFGERRAERHEADERLOG9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG9"
                },
                "CFGERRAERHEADERLOG10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG10"
                },
                "CFGERRAERHEADERLOG11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG11"
                },
                "CFGERRAERHEADERLOG12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG12"
                },
                "CFGERRAERHEADERLOG13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG13"
                },
                "CFGERRAERHEADERLOG14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
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                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG106"
                },
                "CFGERRAERHEADERLOG107": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG107"
                },
                "CFGERRAERHEADERLOG108": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG108"
                },
                "CFGERRAERHEADERLOG109": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG109"
                },
                "CFGERRAERHEADERLOG110": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG110"
                },
                "CFGERRAERHEADERLOG111": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG111"
                },
                "CFGERRAERHEADERLOG112": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG112"
                },
                "CFGERRAERHEADERLOG113": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG113"
                },
                "CFGERRAERHEADERLOG114": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG114"
                },
                "CFGERRAERHEADERLOG115": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG115"
                },
                "CFGERRAERHEADERLOG116": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG116"
                },
                "CFGERRAERHEADERLOG117": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG117"
                },
                "CFGERRAERHEADERLOG118": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG118"
                },
                "CFGERRAERHEADERLOG119": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG119"
                },
                "CFGERRAERHEADERLOG120": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG120"
                },
                "CFGERRAERHEADERLOG121": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG121"
                },
                "CFGERRAERHEADERLOG122": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRAERHEADERLOG122"
                },
                "CFGERRAERHEADERLOG123": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG123"
                },
                "CFGERRAERHEADERLOG124": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG124"
                },
                "CFGERRAERHEADERLOG125": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG125"
                },
                "CFGERRAERHEADERLOG126": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG126"
                },
                "CFGERRAERHEADERLOG127": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRAERHEADERLOG127"
                },
                "CFGERRAERHEADERLOGSETN": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_CFGERRAERHEADERLOGSETN"
                },
                "CFGERRATOMICEGRESSBLOCKEDN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRATOMICEGRESSBLOCKEDN"
                },
                "CFGERRCORN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRCORN"
                },
                "CFGERRCPLABORTN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRCPLABORTN"
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                "CFGERRCPLRDYN": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_CFGERRCPLRDYN"
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                "CFGERRCPLTIMEOUTN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRCPLTIMEOUTN"
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                "CFGERRCPLUNEXPECTN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRCPLUNEXPECTN"
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                "CFGERRECRCN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRECRCN"
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                "CFGERRINTERNALCORN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRINTERNALCORN"
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                "CFGERRINTERNALUNCORN": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRINTERNALUNCORN"
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                "CFGERRLOCKEDN": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRLOCKEDN"
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                "CFGERRMALFORMEDN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRMALFORMEDN"
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                "CFGERRMCBLOCKEDN": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRMCBLOCKEDN"
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                "CFGERRNORECOVERYN": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRNORECOVERYN"
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                "CFGERRPOISONEDN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRPOISONEDN"
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                "CFGERRPOSTEDN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRPOSTEDN"
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                "CFGERRTLPCPLHEADER0": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER0"
                },
                "CFGERRTLPCPLHEADER1": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGERRTLPCPLHEADER1"
                },
                "CFGERRTLPCPLHEADER2": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER2"
                },
                "CFGERRTLPCPLHEADER3": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER3"
                },
                "CFGERRTLPCPLHEADER4": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER4"
                },
                "CFGERRTLPCPLHEADER5": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER5"
                },
                "CFGERRTLPCPLHEADER6": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER6"
                },
                "CFGERRTLPCPLHEADER7": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER7"
                },
                "CFGERRTLPCPLHEADER8": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER8"
                },
                "CFGERRTLPCPLHEADER9": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER9"
                },
                "CFGERRTLPCPLHEADER10": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER10"
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                "CFGERRTLPCPLHEADER11": {
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER11"
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                "CFGERRTLPCPLHEADER12": {
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER12"
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                "CFGERRTLPCPLHEADER13": {
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER13"
                },
                "CFGERRTLPCPLHEADER14": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER14"
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                "CFGERRTLPCPLHEADER15": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER15"
                },
                "CFGERRTLPCPLHEADER16": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER16"
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                "CFGERRTLPCPLHEADER17": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER17"
                },
                "CFGERRTLPCPLHEADER18": {
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                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER18"
                },
                "CFGERRTLPCPLHEADER19": {
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                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER19"
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                "CFGERRTLPCPLHEADER20": {
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                    "delay": [
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                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER20"
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                "CFGERRTLPCPLHEADER21": {
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                    "delay": [
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                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER21"
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                "CFGERRTLPCPLHEADER22": {
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                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER22"
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                "CFGERRTLPCPLHEADER23": {
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                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER23"
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                "CFGERRTLPCPLHEADER24": {
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                    "wire": "PCIE_CFGERRTLPCPLHEADER24"
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                "CFGERRTLPCPLHEADER25": {
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                    "wire": "PCIE_CFGERRTLPCPLHEADER25"
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                "CFGERRTLPCPLHEADER26": {
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                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER26"
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                "CFGERRTLPCPLHEADER27": {
                    "cap": "0.000",
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                        "0.000"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER27"
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                "CFGERRTLPCPLHEADER28": {
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                    "wire": "PCIE_CFGERRTLPCPLHEADER28"
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                    "wire": "PCIE_CFGERRTLPCPLHEADER29"
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                "CFGERRTLPCPLHEADER30": {
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                    "wire": "PCIE_CFGERRTLPCPLHEADER30"
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                "CFGERRTLPCPLHEADER31": {
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                    "wire": "PCIE_CFGERRTLPCPLHEADER31"
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                "CFGERRTLPCPLHEADER32": {
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                    "wire": "PCIE_CFGERRTLPCPLHEADER32"
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                "CFGERRTLPCPLHEADER33": {
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                    "wire": "PCIE_CFGERRTLPCPLHEADER33"
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                "CFGERRTLPCPLHEADER34": {
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                    "wire": "PCIE_CFGERRTLPCPLHEADER35"
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                "CFGERRTLPCPLHEADER38": {
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                    "wire": "PCIE_CFGERRTLPCPLHEADER38"
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                "CFGERRTLPCPLHEADER39": {
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                "CFGERRTLPCPLHEADER40": {
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                "CFGERRTLPCPLHEADER42": {
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                "CFGERRTLPCPLHEADER43": {
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                    "wire": "PCIE_CFGERRURN"
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                    "wire": "PCIE_CFGFORCECOMMONCLOCKOFF"
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                "CFGFORCEEXTENDEDSYNCON": {
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                    "delay": [
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                    "wire": "PCIE_CFGFORCEEXTENDEDSYNCON"
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                    "wire": "PCIE_CFGFORCEMPS0"
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                "CFGFORCEMPS1": {
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                "CFGFORCEMPS2": {
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                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGFORCEMPS2"
                },
                "CFGINTERRUPTASSERTN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGINTERRUPTASSERTN"
                },
                "CFGINTERRUPTDI0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGINTERRUPTDI0"
                },
                "CFGINTERRUPTDI1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGINTERRUPTDI1"
                },
                "CFGINTERRUPTDI2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGINTERRUPTDI2"
                },
                "CFGINTERRUPTDI3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGINTERRUPTDI3"
                },
                "CFGINTERRUPTDI4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGINTERRUPTDI4"
                },
                "CFGINTERRUPTDI5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGINTERRUPTDI5"
                },
                "CFGINTERRUPTDI6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGINTERRUPTDI6"
                },
                "CFGINTERRUPTDI7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGINTERRUPTDI7"
                },
                "CFGINTERRUPTDO0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTDO0"
                },
                "CFGINTERRUPTDO1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTDO1"
                },
                "CFGINTERRUPTDO2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTDO2"
                },
                "CFGINTERRUPTDO3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTDO3"
                },
                "CFGINTERRUPTDO4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTDO4"
                },
                "CFGINTERRUPTDO5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTDO5"
                },
                "CFGINTERRUPTDO6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTDO6"
                },
                "CFGINTERRUPTDO7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTDO7"
                },
                "CFGINTERRUPTMMENABLE0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTMMENABLE0"
                },
                "CFGINTERRUPTMMENABLE1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTMMENABLE1"
                },
                "CFGINTERRUPTMMENABLE2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTMMENABLE2"
                },
                "CFGINTERRUPTMSIENABLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTMSIENABLE"
                },
                "CFGINTERRUPTMSIXENABLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTMSIXENABLE"
                },
                "CFGINTERRUPTMSIXFM": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTMSIXFM"
                },
                "CFGINTERRUPTN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGINTERRUPTN"
                },
                "CFGINTERRUPTRDYN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGINTERRUPTRDYN"
                },
                "CFGINTERRUPTSTATN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGINTERRUPTSTATN"
                },
                "CFGLINKCONTROLASPMCONTROL0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKCONTROLASPMCONTROL0"
                },
                "CFGLINKCONTROLASPMCONTROL1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKCONTROLASPMCONTROL1"
                },
                "CFGLINKCONTROLAUTOBANDWIDTHINTEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKCONTROLAUTOBANDWIDTHINTEN"
                },
                "CFGLINKCONTROLBANDWIDTHINTEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKCONTROLBANDWIDTHINTEN"
                },
                "CFGLINKCONTROLCLOCKPMEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKCONTROLCLOCKPMEN"
                },
                "CFGLINKCONTROLCOMMONCLOCK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKCONTROLCOMMONCLOCK"
                },
                "CFGLINKCONTROLEXTENDEDSYNC": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKCONTROLEXTENDEDSYNC"
                },
                "CFGLINKCONTROLHWAUTOWIDTHDIS": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKCONTROLHWAUTOWIDTHDIS"
                },
                "CFGLINKCONTROLLINKDISABLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKCONTROLLINKDISABLE"
                },
                "CFGLINKCONTROLRCB": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKCONTROLRCB"
                },
                "CFGLINKCONTROLRETRAINLINK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKCONTROLRETRAINLINK"
                },
                "CFGLINKSTATUSAUTOBANDWIDTHSTATUS": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS"
                },
                "CFGLINKSTATUSBANDWIDTHSTATUS": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKSTATUSBANDWIDTHSTATUS"
                },
                "CFGLINKSTATUSCURRENTSPEED0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKSTATUSCURRENTSPEED0"
                },
                "CFGLINKSTATUSCURRENTSPEED1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKSTATUSCURRENTSPEED1"
                },
                "CFGLINKSTATUSDLLACTIVE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKSTATUSDLLACTIVE"
                },
                "CFGLINKSTATUSLINKTRAINING": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKSTATUSLINKTRAINING"
                },
                "CFGLINKSTATUSNEGOTIATEDWIDTH0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0"
                },
                "CFGLINKSTATUSNEGOTIATEDWIDTH1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1"
                },
                "CFGLINKSTATUSNEGOTIATEDWIDTH2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2"
                },
                "CFGLINKSTATUSNEGOTIATEDWIDTH3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3"
                },
                "CFGMGMTBYTEENN0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTBYTEENN0"
                },
                "CFGMGMTBYTEENN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTBYTEENN1"
                },
                "CFGMGMTBYTEENN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTBYTEENN2"
                },
                "CFGMGMTBYTEENN3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTBYTEENN3"
                },
                "CFGMGMTDI0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI0"
                },
                "CFGMGMTDI1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI1"
                },
                "CFGMGMTDI2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI2"
                },
                "CFGMGMTDI3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI3"
                },
                "CFGMGMTDI4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI4"
                },
                "CFGMGMTDI5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI5"
                },
                "CFGMGMTDI6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI6"
                },
                "CFGMGMTDI7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI7"
                },
                "CFGMGMTDI8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI8"
                },
                "CFGMGMTDI9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI9"
                },
                "CFGMGMTDI10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI10"
                },
                "CFGMGMTDI11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI11"
                },
                "CFGMGMTDI12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI12"
                },
                "CFGMGMTDI13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI13"
                },
                "CFGMGMTDI14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI14"
                },
                "CFGMGMTDI15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI15"
                },
                "CFGMGMTDI16": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI16"
                },
                "CFGMGMTDI17": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI17"
                },
                "CFGMGMTDI18": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI18"
                },
                "CFGMGMTDI19": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI19"
                },
                "CFGMGMTDI20": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI20"
                },
                "CFGMGMTDI21": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI21"
                },
                "CFGMGMTDI22": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI22"
                },
                "CFGMGMTDI23": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI23"
                },
                "CFGMGMTDI24": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI24"
                },
                "CFGMGMTDI25": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI25"
                },
                "CFGMGMTDI26": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI26"
                },
                "CFGMGMTDI27": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI27"
                },
                "CFGMGMTDI28": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI28"
                },
                "CFGMGMTDI29": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI29"
                },
                "CFGMGMTDI30": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI30"
                },
                "CFGMGMTDI31": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDI31"
                },
                "CFGMGMTDO0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO0"
                },
                "CFGMGMTDO1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO1"
                },
                "CFGMGMTDO2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO2"
                },
                "CFGMGMTDO3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO3"
                },
                "CFGMGMTDO4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO4"
                },
                "CFGMGMTDO5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO5"
                },
                "CFGMGMTDO6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO6"
                },
                "CFGMGMTDO7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO7"
                },
                "CFGMGMTDO8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO8"
                },
                "CFGMGMTDO9": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO9"
                },
                "CFGMGMTDO10": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO10"
                },
                "CFGMGMTDO11": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO11"
                },
                "CFGMGMTDO12": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO12"
                },
                "CFGMGMTDO13": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO13"
                },
                "CFGMGMTDO14": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO14"
                },
                "CFGMGMTDO15": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO15"
                },
                "CFGMGMTDO16": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO16"
                },
                "CFGMGMTDO17": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO17"
                },
                "CFGMGMTDO18": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO18"
                },
                "CFGMGMTDO19": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO19"
                },
                "CFGMGMTDO20": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO20"
                },
                "CFGMGMTDO21": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO21"
                },
                "CFGMGMTDO22": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO22"
                },
                "CFGMGMTDO23": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO23"
                },
                "CFGMGMTDO24": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO24"
                },
                "CFGMGMTDO25": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO25"
                },
                "CFGMGMTDO26": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO26"
                },
                "CFGMGMTDO27": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO27"
                },
                "CFGMGMTDO28": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO28"
                },
                "CFGMGMTDO29": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO29"
                },
                "CFGMGMTDO30": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO30"
                },
                "CFGMGMTDO31": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTDO31"
                },
                "CFGMGMTDWADDR0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDWADDR0"
                },
                "CFGMGMTDWADDR1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDWADDR1"
                },
                "CFGMGMTDWADDR2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDWADDR2"
                },
                "CFGMGMTDWADDR3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDWADDR3"
                },
                "CFGMGMTDWADDR4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDWADDR4"
                },
                "CFGMGMTDWADDR5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDWADDR5"
                },
                "CFGMGMTDWADDR6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDWADDR6"
                },
                "CFGMGMTDWADDR7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDWADDR7"
                },
                "CFGMGMTDWADDR8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDWADDR8"
                },
                "CFGMGMTDWADDR9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTDWADDR9"
                },
                "CFGMGMTRDENN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTRDENN"
                },
                "CFGMGMTRDWRDONEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMGMTRDWRDONEN"
                },
                "CFGMGMTWRENN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTWRENN"
                },
                "CFGMGMTWRREADONLYN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTWRREADONLYN"
                },
                "CFGMGMTWRRW1CASRWN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGMGMTWRRW1CASRWN"
                },
                "CFGMSGDATA0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA0"
                },
                "CFGMSGDATA1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA1"
                },
                "CFGMSGDATA2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA2"
                },
                "CFGMSGDATA3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA3"
                },
                "CFGMSGDATA4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA4"
                },
                "CFGMSGDATA5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA5"
                },
                "CFGMSGDATA6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA6"
                },
                "CFGMSGDATA7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA7"
                },
                "CFGMSGDATA8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA8"
                },
                "CFGMSGDATA9": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA9"
                },
                "CFGMSGDATA10": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA10"
                },
                "CFGMSGDATA11": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA11"
                },
                "CFGMSGDATA12": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA12"
                },
                "CFGMSGDATA13": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA13"
                },
                "CFGMSGDATA14": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA14"
                },
                "CFGMSGDATA15": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGDATA15"
                },
                "CFGMSGRECEIVED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVED"
                },
                "CFGMSGRECEIVEDASSERTINTA": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDASSERTINTA"
                },
                "CFGMSGRECEIVEDASSERTINTB": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDASSERTINTB"
                },
                "CFGMSGRECEIVEDASSERTINTC": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDASSERTINTC"
                },
                "CFGMSGRECEIVEDASSERTINTD": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDASSERTINTD"
                },
                "CFGMSGRECEIVEDDEASSERTINTA": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTA"
                },
                "CFGMSGRECEIVEDDEASSERTINTB": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTB"
                },
                "CFGMSGRECEIVEDDEASSERTINTC": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTC"
                },
                "CFGMSGRECEIVEDDEASSERTINTD": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTD"
                },
                "CFGMSGRECEIVEDERRCOR": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDERRCOR"
                },
                "CFGMSGRECEIVEDERRFATAL": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDERRFATAL"
                },
                "CFGMSGRECEIVEDERRNONFATAL": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDERRNONFATAL"
                },
                "CFGMSGRECEIVEDPMASNAK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDPMASNAK"
                },
                "CFGMSGRECEIVEDPMETO": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDPMETO"
                },
                "CFGMSGRECEIVEDPMETOACK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDPMETOACK"
                },
                "CFGMSGRECEIVEDPMPME": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDPMPME"
                },
                "CFGMSGRECEIVEDSETSLOTPOWERLIMIT": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT"
                },
                "CFGMSGRECEIVEDUNLOCK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGMSGRECEIVEDUNLOCK"
                },
                "CFGPCIECAPINTERRUPTMSGNUM0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM0"
                },
                "CFGPCIECAPINTERRUPTMSGNUM1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM1"
                },
                "CFGPCIECAPINTERRUPTMSGNUM2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM2"
                },
                "CFGPCIECAPINTERRUPTMSGNUM3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM3"
                },
                "CFGPCIECAPINTERRUPTMSGNUM4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPCIECAPINTERRUPTMSGNUM4"
                },
                "CFGPCIELINKSTATE0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGPCIELINKSTATE0"
                },
                "CFGPCIELINKSTATE1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGPCIELINKSTATE1"
                },
                "CFGPCIELINKSTATE2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGPCIELINKSTATE2"
                },
                "CFGPMCSRPMEEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGPMCSRPMEEN"
                },
                "CFGPMCSRPMESTATUS": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGPMCSRPMESTATUS"
                },
                "CFGPMCSRPOWERSTATE0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGPMCSRPOWERSTATE0"
                },
                "CFGPMCSRPOWERSTATE1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGPMCSRPOWERSTATE1"
                },
                "CFGPMFORCESTATE0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPMFORCESTATE0"
                },
                "CFGPMFORCESTATE1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPMFORCESTATE1"
                },
                "CFGPMFORCESTATEENN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPMFORCESTATEENN"
                },
                "CFGPMHALTASPML0SN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPMHALTASPML0SN"
                },
                "CFGPMHALTASPML1N": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPMHALTASPML1N"
                },
                "CFGPMRCVASREQL1N": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGPMRCVASREQL1N"
                },
                "CFGPMRCVENTERL1N": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGPMRCVENTERL1N"
                },
                "CFGPMRCVENTERL23N": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGPMRCVENTERL23N"
                },
                "CFGPMRCVREQACKN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGPMRCVREQACKN"
                },
                "CFGPMSENDPMETON": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPMSENDPMETON"
                },
                "CFGPMTURNOFFOKN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPMTURNOFFOKN"
                },
                "CFGPMWAKEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPMWAKEN"
                },
                "CFGPORTNUMBER0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPORTNUMBER0"
                },
                "CFGPORTNUMBER1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPORTNUMBER1"
                },
                "CFGPORTNUMBER2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPORTNUMBER2"
                },
                "CFGPORTNUMBER3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPORTNUMBER3"
                },
                "CFGPORTNUMBER4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPORTNUMBER4"
                },
                "CFGPORTNUMBER5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPORTNUMBER5"
                },
                "CFGPORTNUMBER6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPORTNUMBER6"
                },
                "CFGPORTNUMBER7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGPORTNUMBER7"
                },
                "CFGREVID0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGREVID0"
                },
                "CFGREVID1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGREVID1"
                },
                "CFGREVID2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGREVID2"
                },
                "CFGREVID3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGREVID3"
                },
                "CFGREVID4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGREVID4"
                },
                "CFGREVID5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGREVID5"
                },
                "CFGREVID6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGREVID6"
                },
                "CFGREVID7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGREVID7"
                },
                "CFGROOTCONTROLPMEINTEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGROOTCONTROLPMEINTEN"
                },
                "CFGROOTCONTROLSYSERRCORRERREN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGROOTCONTROLSYSERRCORRERREN"
                },
                "CFGROOTCONTROLSYSERRFATALERREN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGROOTCONTROLSYSERRFATALERREN"
                },
                "CFGROOTCONTROLSYSERRNONFATALERREN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGROOTCONTROLSYSERRNONFATALERREN"
                },
                "CFGSLOTCONTROLELECTROMECHILCTLPULSE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE"
                },
                "CFGSUBSYSID0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID0"
                },
                "CFGSUBSYSID1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID1"
                },
                "CFGSUBSYSID2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID2"
                },
                "CFGSUBSYSID3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID3"
                },
                "CFGSUBSYSID4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID4"
                },
                "CFGSUBSYSID5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID5"
                },
                "CFGSUBSYSID6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID6"
                },
                "CFGSUBSYSID7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID7"
                },
                "CFGSUBSYSID8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID8"
                },
                "CFGSUBSYSID9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID9"
                },
                "CFGSUBSYSID10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID10"
                },
                "CFGSUBSYSID11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID11"
                },
                "CFGSUBSYSID12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID12"
                },
                "CFGSUBSYSID13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID13"
                },
                "CFGSUBSYSID14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID14"
                },
                "CFGSUBSYSID15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSID15"
                },
                "CFGSUBSYSVENDID0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID0"
                },
                "CFGSUBSYSVENDID1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID1"
                },
                "CFGSUBSYSVENDID2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID2"
                },
                "CFGSUBSYSVENDID3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID3"
                },
                "CFGSUBSYSVENDID4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID4"
                },
                "CFGSUBSYSVENDID5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID5"
                },
                "CFGSUBSYSVENDID6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID6"
                },
                "CFGSUBSYSVENDID7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID7"
                },
                "CFGSUBSYSVENDID8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID8"
                },
                "CFGSUBSYSVENDID9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID9"
                },
                "CFGSUBSYSVENDID10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID10"
                },
                "CFGSUBSYSVENDID11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID11"
                },
                "CFGSUBSYSVENDID12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID12"
                },
                "CFGSUBSYSVENDID13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID13"
                },
                "CFGSUBSYSVENDID14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID14"
                },
                "CFGSUBSYSVENDID15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGSUBSYSVENDID15"
                },
                "CFGTRANSACTION": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGTRANSACTION"
                },
                "CFGTRANSACTIONADDR0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGTRANSACTIONADDR0"
                },
                "CFGTRANSACTIONADDR1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGTRANSACTIONADDR1"
                },
                "CFGTRANSACTIONADDR2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGTRANSACTIONADDR2"
                },
                "CFGTRANSACTIONADDR3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGTRANSACTIONADDR3"
                },
                "CFGTRANSACTIONADDR4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGTRANSACTIONADDR4"
                },
                "CFGTRANSACTIONADDR5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGTRANSACTIONADDR5"
                },
                "CFGTRANSACTIONADDR6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGTRANSACTIONADDR6"
                },
                "CFGTRANSACTIONTYPE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGTRANSACTIONTYPE"
                },
                "CFGTRNPENDINGN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGTRNPENDINGN"
                },
                "CFGVCTCVCMAP0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGVCTCVCMAP0"
                },
                "CFGVCTCVCMAP1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGVCTCVCMAP1"
                },
                "CFGVCTCVCMAP2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGVCTCVCMAP2"
                },
                "CFGVCTCVCMAP3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGVCTCVCMAP3"
                },
                "CFGVCTCVCMAP4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGVCTCVCMAP4"
                },
                "CFGVCTCVCMAP5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGVCTCVCMAP5"
                },
                "CFGVCTCVCMAP6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_CFGVCTCVCMAP6"
                },
                "CFGVENDID0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID0"
                },
                "CFGVENDID1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID1"
                },
                "CFGVENDID2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID2"
                },
                "CFGVENDID3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID3"
                },
                "CFGVENDID4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID4"
                },
                "CFGVENDID5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID5"
                },
                "CFGVENDID6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID6"
                },
                "CFGVENDID7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID7"
                },
                "CFGVENDID8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID8"
                },
                "CFGVENDID9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID9"
                },
                "CFGVENDID10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID10"
                },
                "CFGVENDID11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID11"
                },
                "CFGVENDID12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID12"
                },
                "CFGVENDID13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID13"
                },
                "CFGVENDID14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID14"
                },
                "CFGVENDID15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CFGVENDID15"
                },
                "CMRSTN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CMRSTN"
                },
                "CMSTICKYRSTN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_CMSTICKYRSTN"
                },
                "DBGMODE0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DBGMODE0"
                },
                "DBGMODE1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DBGMODE1"
                },
                "DBGSCLRA": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGSCLRA"
                },
                "DBGSCLRB": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGSCLRB"
                },
                "DBGSCLRC": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGSCLRC"
                },
                "DBGSCLRD": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGSCLRD"
                },
                "DBGSCLRE": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGSCLRE"
                },
                "DBGSCLRF": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGSCLRF"
                },
                "DBGSCLRG": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGSCLRG"
                },
                "DBGSCLRH": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGSCLRH"
                },
                "DBGSCLRI": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGSCLRI"
                },
                "DBGSCLRJ": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGSCLRJ"
                },
                "DBGSCLRK": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGSCLRK"
                },
                "DBGSUBMODE": {
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                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DBGSUBMODE"
                },
                "DBGVECA0": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA0"
                },
                "DBGVECA1": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA1"
                },
                "DBGVECA2": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA2"
                },
                "DBGVECA3": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA3"
                },
                "DBGVECA4": {
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DBGVECA4"
                },
                "DBGVECA5": {
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA5"
                },
                "DBGVECA6": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA6"
                },
                "DBGVECA7": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA7"
                },
                "DBGVECA8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA8"
                },
                "DBGVECA9": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA9"
                },
                "DBGVECA10": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA10"
                },
                "DBGVECA11": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA11"
                },
                "DBGVECA12": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA12"
                },
                "DBGVECA13": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA13"
                },
                "DBGVECA14": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA14"
                },
                "DBGVECA15": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA15"
                },
                "DBGVECA16": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA16"
                },
                "DBGVECA17": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA17"
                },
                "DBGVECA18": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA18"
                },
                "DBGVECA19": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA19"
                },
                "DBGVECA20": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA20"
                },
                "DBGVECA21": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA21"
                },
                "DBGVECA22": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA22"
                },
                "DBGVECA23": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA23"
                },
                "DBGVECA24": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA24"
                },
                "DBGVECA25": {
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA25"
                },
                "DBGVECA26": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA26"
                },
                "DBGVECA27": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA27"
                },
                "DBGVECA28": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA28"
                },
                "DBGVECA29": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA29"
                },
                "DBGVECA30": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA30"
                },
                "DBGVECA31": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA31"
                },
                "DBGVECA32": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA32"
                },
                "DBGVECA33": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA33"
                },
                "DBGVECA34": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA34"
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                "DBGVECA35": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA35"
                },
                "DBGVECA36": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA36"
                },
                "DBGVECA37": {
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA37"
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                "DBGVECA38": {
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA38"
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                "DBGVECA39": {
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DBGVECA39"
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                "DBGVECA40": {
                    "delay": [
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                    "wire": "PCIE_DBGVECA40"
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                "DBGVECA41": {
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                    "wire": "PCIE_DBGVECA41"
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                "DBGVECA42": {
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                        "0.000"
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                    "wire": "PCIE_DBGVECA42"
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                "DBGVECA43": {
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                "DBGVECA44": {
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                "DBGVECA45": {
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                    "wire": "PCIE_DBGVECA45"
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                "DBGVECA46": {
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                    "wire": "PCIE_DBGVECA46"
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                "DBGVECA47": {
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                    "wire": "PCIE_DBGVECA47"
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                "DBGVECA48": {
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA48"
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                "DBGVECA49": {
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                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA49"
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                "DBGVECA50": {
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                    "wire": "PCIE_DBGVECA50"
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                "DBGVECA51": {
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA51"
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                "DBGVECA52": {
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA52"
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                "DBGVECA53": {
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA53"
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                "DBGVECA54": {
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA54"
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                "DBGVECA55": {
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECA55"
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                "DBGVECA56": {
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                "DBGVECA57": {
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                "DBGVECA58": {
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                    "wire": "PCIE_DBGVECA58"
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                "DBGVECA59": {
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                    "wire": "PCIE_DBGVECA59"
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                "DBGVECA60": {
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                    "wire": "PCIE_DBGVECA60"
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                "DBGVECA61": {
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                    "wire": "PCIE_DBGVECA61"
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                "DBGVECA62": {
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                "DBGVECA63": {
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                "DBGVECB4": {
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                "DBGVECB13": {
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                "DBGVECB14": {
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                "DBGVECB15": {
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB15"
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                "DBGVECB16": {
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                "DBGVECB17": {
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                "DBGVECB18": {
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                        "0.000",
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB18"
                },
                "DBGVECB19": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB19"
                },
                "DBGVECB20": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB20"
                },
                "DBGVECB21": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB21"
                },
                "DBGVECB22": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB22"
                },
                "DBGVECB23": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB23"
                },
                "DBGVECB24": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB24"
                },
                "DBGVECB25": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB25"
                },
                "DBGVECB26": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB26"
                },
                "DBGVECB27": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB27"
                },
                "DBGVECB28": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB28"
                },
                "DBGVECB29": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB29"
                },
                "DBGVECB30": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB30"
                },
                "DBGVECB31": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB31"
                },
                "DBGVECB32": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB32"
                },
                "DBGVECB33": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB33"
                },
                "DBGVECB34": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB34"
                },
                "DBGVECB35": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB35"
                },
                "DBGVECB36": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB36"
                },
                "DBGVECB37": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB37"
                },
                "DBGVECB38": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB38"
                },
                "DBGVECB39": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB39"
                },
                "DBGVECB40": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB40"
                },
                "DBGVECB41": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB41"
                },
                "DBGVECB42": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB42"
                },
                "DBGVECB43": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB43"
                },
                "DBGVECB44": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB44"
                },
                "DBGVECB45": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB45"
                },
                "DBGVECB46": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB46"
                },
                "DBGVECB47": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB47"
                },
                "DBGVECB48": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB48"
                },
                "DBGVECB49": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB49"
                },
                "DBGVECB50": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB50"
                },
                "DBGVECB51": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB51"
                },
                "DBGVECB52": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB52"
                },
                "DBGVECB53": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB53"
                },
                "DBGVECB54": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB54"
                },
                "DBGVECB55": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB55"
                },
                "DBGVECB56": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB56"
                },
                "DBGVECB57": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB57"
                },
                "DBGVECB58": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB58"
                },
                "DBGVECB59": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB59"
                },
                "DBGVECB60": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB60"
                },
                "DBGVECB61": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB61"
                },
                "DBGVECB62": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB62"
                },
                "DBGVECB63": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECB63"
                },
                "DBGVECC0": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECC0"
                },
                "DBGVECC1": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECC1"
                },
                "DBGVECC2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECC2"
                },
                "DBGVECC3": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECC3"
                },
                "DBGVECC4": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECC4"
                },
                "DBGVECC5": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECC5"
                },
                "DBGVECC6": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECC6"
                },
                "DBGVECC7": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECC7"
                },
                "DBGVECC8": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECC8"
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                "DBGVECC9": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECC9"
                },
                "DBGVECC10": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECC10"
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                "DBGVECC11": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DBGVECC11"
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                "DLRSTN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DLRSTN"
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                "DRPADDR0": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPADDR0"
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                "DRPADDR1": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPADDR1"
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                "DRPADDR2": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPADDR2"
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                "DRPADDR3": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPADDR3"
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                "DRPADDR4": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPADDR4"
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                "DRPADDR5": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPADDR5"
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                "DRPADDR6": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPADDR6"
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                "DRPADDR7": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DRPADDR7"
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                "DRPADDR8": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DRPADDR8"
                },
                "DRPCLK": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DRPCLK"
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                "DRPDI0": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DRPDI0"
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                "DRPDI1": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPDI1"
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                "DRPDI2": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPDI2"
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                "DRPDI3": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPDI3"
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                "DRPDI4": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPDI4"
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                "DRPDI5": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPDI5"
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                "DRPDI6": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPDI6"
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                "DRPDI7": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPDI7"
                },
                "DRPDI8": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPDI8"
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                "DRPDI9": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPDI9"
                },
                "DRPDI10": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPDI10"
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                "DRPDI11": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DRPDI11"
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                "DRPDI12": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_DRPDI12"
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                "DRPDI13": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DRPDI13"
                },
                "DRPDI14": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DRPDI14"
                },
                "DRPDI15": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DRPDI15"
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                "DRPDO0": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DRPDO0"
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                "DRPDO1": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DRPDO1"
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                "DRPDO2": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DRPDO2"
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                "DRPDO3": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DRPDO3"
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                "DRPDO4": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DRPDO4"
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                "DRPDO5": {
                    "delay": [
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                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DRPDO5"
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                "DRPDO6": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DRPDO6"
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                "DRPDO7": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DRPDO7"
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                "DRPDO8": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DRPDO8"
                },
                "DRPDO9": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DRPDO9"
                },
                "DRPDO10": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DRPDO10"
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                "DRPDO11": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_DRPDO11"
                },
                "DRPDO12": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DRPDO12"
                },
                "DRPDO13": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DRPDO13"
                },
                "DRPDO14": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DRPDO14"
                },
                "DRPDO15": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DRPDO15"
                },
                "DRPEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DRPEN"
                },
                "DRPRDY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_DRPRDY"
                },
                "DRPWE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_DRPWE"
                },
                "EDTBYPASS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTBYPASS"
                },
                "EDTCHANNELSIN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTCHANNELSIN1"
                },
                "EDTCHANNELSIN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTCHANNELSIN2"
                },
                "EDTCHANNELSIN3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTCHANNELSIN3"
                },
                "EDTCHANNELSIN4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTCHANNELSIN4"
                },
                "EDTCHANNELSIN5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTCHANNELSIN5"
                },
                "EDTCHANNELSIN6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTCHANNELSIN6"
                },
                "EDTCHANNELSIN7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTCHANNELSIN7"
                },
                "EDTCHANNELSIN8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTCHANNELSIN8"
                },
                "EDTCHANNELSOUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_EDTCHANNELSOUT1"
                },
                "EDTCHANNELSOUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_EDTCHANNELSOUT2"
                },
                "EDTCHANNELSOUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_EDTCHANNELSOUT3"
                },
                "EDTCHANNELSOUT4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_EDTCHANNELSOUT4"
                },
                "EDTCHANNELSOUT5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_EDTCHANNELSOUT5"
                },
                "EDTCHANNELSOUT6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_EDTCHANNELSOUT6"
                },
                "EDTCHANNELSOUT7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_EDTCHANNELSOUT7"
                },
                "EDTCHANNELSOUT8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_EDTCHANNELSOUT8"
                },
                "EDTCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTCLK"
                },
                "EDTCONFIGURATION": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTCONFIGURATION"
                },
                "EDTSINGLEBYPASSCHAIN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTSINGLEBYPASSCHAIN"
                },
                "EDTUPDATE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_EDTUPDATE"
                },
                "FUNCLVLRSTN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_FUNCLVLRSTN"
                },
                "LL2BADDLLPERR": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2BADDLLPERR"
                },
                "LL2BADTLPERR": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2BADTLPERR"
                },
                "LL2LINKSTATUS0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2LINKSTATUS0"
                },
                "LL2LINKSTATUS1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2LINKSTATUS1"
                },
                "LL2LINKSTATUS2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2LINKSTATUS2"
                },
                "LL2LINKSTATUS3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2LINKSTATUS3"
                },
                "LL2LINKSTATUS4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2LINKSTATUS4"
                },
                "LL2PROTOCOLERR": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2PROTOCOLERR"
                },
                "LL2RECEIVERERR": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2RECEIVERERR"
                },
                "LL2REPLAYROERR": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2REPLAYROERR"
                },
                "LL2REPLAYTOERR": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2REPLAYTOERR"
                },
                "LL2SENDASREQL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_LL2SENDASREQL1"
                },
                "LL2SENDENTERL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_LL2SENDENTERL1"
                },
                "LL2SENDENTERL23": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_LL2SENDENTERL23"
                },
                "LL2SENDPMACK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_LL2SENDPMACK"
                },
                "LL2SUSPENDNOW": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_LL2SUSPENDNOW"
                },
                "LL2SUSPENDOK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2SUSPENDOK"
                },
                "LL2TFCINIT1SEQ": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2TFCINIT1SEQ"
                },
                "LL2TFCINIT2SEQ": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2TFCINIT2SEQ"
                },
                "LL2TLPRCV": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_LL2TLPRCV"
                },
                "LL2TXIDLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LL2TXIDLE"
                },
                "LNKCLKEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_LNKCLKEN"
                },
                "MIMRXRADDR0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR0"
                },
                "MIMRXRADDR1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR1"
                },
                "MIMRXRADDR2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR2"
                },
                "MIMRXRADDR3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR3"
                },
                "MIMRXRADDR4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR4"
                },
                "MIMRXRADDR5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR5"
                },
                "MIMRXRADDR6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR6"
                },
                "MIMRXRADDR7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR7"
                },
                "MIMRXRADDR8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR8"
                },
                "MIMRXRADDR9": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR9"
                },
                "MIMRXRADDR10": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR10"
                },
                "MIMRXRADDR11": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR11"
                },
                "MIMRXRADDR12": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMRXRADDR12"
                },
                "MIMRXRDATA0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA0"
                },
                "MIMRXRDATA1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA1"
                },
                "MIMRXRDATA2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA2"
                },
                "MIMRXRDATA3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA3"
                },
                "MIMRXRDATA4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA4"
                },
                "MIMRXRDATA5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA5"
                },
                "MIMRXRDATA6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA6"
                },
                "MIMRXRDATA7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA7"
                },
                "MIMRXRDATA8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA8"
                },
                "MIMRXRDATA9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA9"
                },
                "MIMRXRDATA10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA10"
                },
                "MIMRXRDATA11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA11"
                },
                "MIMRXRDATA12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA12"
                },
                "MIMRXRDATA13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA13"
                },
                "MIMRXRDATA14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA14"
                },
                "MIMRXRDATA15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA15"
                },
                "MIMRXRDATA16": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA16"
                },
                "MIMRXRDATA17": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA17"
                },
                "MIMRXRDATA18": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA18"
                },
                "MIMRXRDATA19": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA19"
                },
                "MIMRXRDATA20": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA20"
                },
                "MIMRXRDATA21": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA21"
                },
                "MIMRXRDATA22": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA22"
                },
                "MIMRXRDATA23": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA23"
                },
                "MIMRXRDATA24": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA24"
                },
                "MIMRXRDATA25": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA25"
                },
                "MIMRXRDATA26": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA26"
                },
                "MIMRXRDATA27": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA27"
                },
                "MIMRXRDATA28": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA28"
                },
                "MIMRXRDATA29": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_MIMRXRDATA29"
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                "MIMRXRDATA30": {
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                    "res": "1375.0",
                    "wire": "PCIE_MIMTXWDATA62"
                },
                "MIMTXWDATA63": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMTXWDATA63"
                },
                "MIMTXWDATA64": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMTXWDATA64"
                },
                "MIMTXWDATA65": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMTXWDATA65"
                },
                "MIMTXWDATA66": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMTXWDATA66"
                },
                "MIMTXWDATA67": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMTXWDATA67"
                },
                "MIMTXWDATA68": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMTXWDATA68"
                },
                "MIMTXWEN": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_MIMTXWEN"
                },
                "PIPECLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPECLK"
                },
                "PIPERX0CHANISALIGNED": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0CHANISALIGNED"
                },
                "PIPERX0CHARISK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0CHARISK0"
                },
                "PIPERX0CHARISK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0CHARISK1"
                },
                "PIPERX0DATA0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA0"
                },
                "PIPERX0DATA1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA1"
                },
                "PIPERX0DATA2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA2"
                },
                "PIPERX0DATA3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA3"
                },
                "PIPERX0DATA4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA4"
                },
                "PIPERX0DATA5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA5"
                },
                "PIPERX0DATA6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA6"
                },
                "PIPERX0DATA7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA7"
                },
                "PIPERX0DATA8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA8"
                },
                "PIPERX0DATA9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA9"
                },
                "PIPERX0DATA10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA10"
                },
                "PIPERX0DATA11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA11"
                },
                "PIPERX0DATA12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA12"
                },
                "PIPERX0DATA13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA13"
                },
                "PIPERX0DATA14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA14"
                },
                "PIPERX0DATA15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0DATA15"
                },
                "PIPERX0ELECIDLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0ELECIDLE"
                },
                "PIPERX0PHYSTATUS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0PHYSTATUS"
                },
                "PIPERX0POLARITY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPERX0POLARITY"
                },
                "PIPERX0STATUS0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0STATUS0"
                },
                "PIPERX0STATUS1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0STATUS1"
                },
                "PIPERX0STATUS2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0STATUS2"
                },
                "PIPERX0VALID": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX0VALID"
                },
                "PIPERX1CHANISALIGNED": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1CHANISALIGNED"
                },
                "PIPERX1CHARISK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1CHARISK0"
                },
                "PIPERX1CHARISK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1CHARISK1"
                },
                "PIPERX1DATA0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA0"
                },
                "PIPERX1DATA1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA1"
                },
                "PIPERX1DATA2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA2"
                },
                "PIPERX1DATA3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA3"
                },
                "PIPERX1DATA4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA4"
                },
                "PIPERX1DATA5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA5"
                },
                "PIPERX1DATA6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA6"
                },
                "PIPERX1DATA7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA7"
                },
                "PIPERX1DATA8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA8"
                },
                "PIPERX1DATA9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA9"
                },
                "PIPERX1DATA10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA10"
                },
                "PIPERX1DATA11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA11"
                },
                "PIPERX1DATA12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA12"
                },
                "PIPERX1DATA13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA13"
                },
                "PIPERX1DATA14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA14"
                },
                "PIPERX1DATA15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1DATA15"
                },
                "PIPERX1ELECIDLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1ELECIDLE"
                },
                "PIPERX1PHYSTATUS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1PHYSTATUS"
                },
                "PIPERX1POLARITY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPERX1POLARITY"
                },
                "PIPERX1STATUS0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1STATUS0"
                },
                "PIPERX1STATUS1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1STATUS1"
                },
                "PIPERX1STATUS2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1STATUS2"
                },
                "PIPERX1VALID": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX1VALID"
                },
                "PIPERX2CHANISALIGNED": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2CHANISALIGNED"
                },
                "PIPERX2CHARISK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2CHARISK0"
                },
                "PIPERX2CHARISK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2CHARISK1"
                },
                "PIPERX2DATA0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA0"
                },
                "PIPERX2DATA1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA1"
                },
                "PIPERX2DATA2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA2"
                },
                "PIPERX2DATA3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA3"
                },
                "PIPERX2DATA4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA4"
                },
                "PIPERX2DATA5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA5"
                },
                "PIPERX2DATA6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA6"
                },
                "PIPERX2DATA7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA7"
                },
                "PIPERX2DATA8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA8"
                },
                "PIPERX2DATA9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA9"
                },
                "PIPERX2DATA10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA10"
                },
                "PIPERX2DATA11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA11"
                },
                "PIPERX2DATA12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA12"
                },
                "PIPERX2DATA13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA13"
                },
                "PIPERX2DATA14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA14"
                },
                "PIPERX2DATA15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2DATA15"
                },
                "PIPERX2ELECIDLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2ELECIDLE"
                },
                "PIPERX2PHYSTATUS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2PHYSTATUS"
                },
                "PIPERX2POLARITY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPERX2POLARITY"
                },
                "PIPERX2STATUS0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2STATUS0"
                },
                "PIPERX2STATUS1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2STATUS1"
                },
                "PIPERX2STATUS2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2STATUS2"
                },
                "PIPERX2VALID": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX2VALID"
                },
                "PIPERX3CHANISALIGNED": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3CHANISALIGNED"
                },
                "PIPERX3CHARISK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3CHARISK0"
                },
                "PIPERX3CHARISK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3CHARISK1"
                },
                "PIPERX3DATA0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA0"
                },
                "PIPERX3DATA1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA1"
                },
                "PIPERX3DATA2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA2"
                },
                "PIPERX3DATA3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA3"
                },
                "PIPERX3DATA4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA4"
                },
                "PIPERX3DATA5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA5"
                },
                "PIPERX3DATA6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA6"
                },
                "PIPERX3DATA7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA7"
                },
                "PIPERX3DATA8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA8"
                },
                "PIPERX3DATA9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA9"
                },
                "PIPERX3DATA10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA10"
                },
                "PIPERX3DATA11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA11"
                },
                "PIPERX3DATA12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA12"
                },
                "PIPERX3DATA13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA13"
                },
                "PIPERX3DATA14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA14"
                },
                "PIPERX3DATA15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3DATA15"
                },
                "PIPERX3ELECIDLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3ELECIDLE"
                },
                "PIPERX3PHYSTATUS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3PHYSTATUS"
                },
                "PIPERX3POLARITY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPERX3POLARITY"
                },
                "PIPERX3STATUS0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3STATUS0"
                },
                "PIPERX3STATUS1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3STATUS1"
                },
                "PIPERX3STATUS2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3STATUS2"
                },
                "PIPERX3VALID": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX3VALID"
                },
                "PIPERX4CHANISALIGNED": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4CHANISALIGNED"
                },
                "PIPERX4CHARISK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4CHARISK0"
                },
                "PIPERX4CHARISK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4CHARISK1"
                },
                "PIPERX4DATA0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA0"
                },
                "PIPERX4DATA1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA1"
                },
                "PIPERX4DATA2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA2"
                },
                "PIPERX4DATA3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA3"
                },
                "PIPERX4DATA4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA4"
                },
                "PIPERX4DATA5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA5"
                },
                "PIPERX4DATA6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA6"
                },
                "PIPERX4DATA7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA7"
                },
                "PIPERX4DATA8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA8"
                },
                "PIPERX4DATA9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA9"
                },
                "PIPERX4DATA10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA10"
                },
                "PIPERX4DATA11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA11"
                },
                "PIPERX4DATA12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA12"
                },
                "PIPERX4DATA13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA13"
                },
                "PIPERX4DATA14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA14"
                },
                "PIPERX4DATA15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4DATA15"
                },
                "PIPERX4ELECIDLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4ELECIDLE"
                },
                "PIPERX4PHYSTATUS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4PHYSTATUS"
                },
                "PIPERX4POLARITY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPERX4POLARITY"
                },
                "PIPERX4STATUS0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4STATUS0"
                },
                "PIPERX4STATUS1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4STATUS1"
                },
                "PIPERX4STATUS2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4STATUS2"
                },
                "PIPERX4VALID": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX4VALID"
                },
                "PIPERX5CHANISALIGNED": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5CHANISALIGNED"
                },
                "PIPERX5CHARISK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5CHARISK0"
                },
                "PIPERX5CHARISK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5CHARISK1"
                },
                "PIPERX5DATA0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA0"
                },
                "PIPERX5DATA1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA1"
                },
                "PIPERX5DATA2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA2"
                },
                "PIPERX5DATA3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA3"
                },
                "PIPERX5DATA4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA4"
                },
                "PIPERX5DATA5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA5"
                },
                "PIPERX5DATA6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA6"
                },
                "PIPERX5DATA7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA7"
                },
                "PIPERX5DATA8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA8"
                },
                "PIPERX5DATA9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA9"
                },
                "PIPERX5DATA10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA10"
                },
                "PIPERX5DATA11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA11"
                },
                "PIPERX5DATA12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA12"
                },
                "PIPERX5DATA13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA13"
                },
                "PIPERX5DATA14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA14"
                },
                "PIPERX5DATA15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5DATA15"
                },
                "PIPERX5ELECIDLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5ELECIDLE"
                },
                "PIPERX5PHYSTATUS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5PHYSTATUS"
                },
                "PIPERX5POLARITY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPERX5POLARITY"
                },
                "PIPERX5STATUS0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5STATUS0"
                },
                "PIPERX5STATUS1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5STATUS1"
                },
                "PIPERX5STATUS2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5STATUS2"
                },
                "PIPERX5VALID": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX5VALID"
                },
                "PIPERX6CHANISALIGNED": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6CHANISALIGNED"
                },
                "PIPERX6CHARISK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6CHARISK0"
                },
                "PIPERX6CHARISK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6CHARISK1"
                },
                "PIPERX6DATA0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA0"
                },
                "PIPERX6DATA1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA1"
                },
                "PIPERX6DATA2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA2"
                },
                "PIPERX6DATA3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA3"
                },
                "PIPERX6DATA4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA4"
                },
                "PIPERX6DATA5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA5"
                },
                "PIPERX6DATA6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA6"
                },
                "PIPERX6DATA7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA7"
                },
                "PIPERX6DATA8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA8"
                },
                "PIPERX6DATA9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA9"
                },
                "PIPERX6DATA10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA10"
                },
                "PIPERX6DATA11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA11"
                },
                "PIPERX6DATA12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA12"
                },
                "PIPERX6DATA13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA13"
                },
                "PIPERX6DATA14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA14"
                },
                "PIPERX6DATA15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6DATA15"
                },
                "PIPERX6ELECIDLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6ELECIDLE"
                },
                "PIPERX6PHYSTATUS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6PHYSTATUS"
                },
                "PIPERX6POLARITY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPERX6POLARITY"
                },
                "PIPERX6STATUS0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6STATUS0"
                },
                "PIPERX6STATUS1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6STATUS1"
                },
                "PIPERX6STATUS2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6STATUS2"
                },
                "PIPERX6VALID": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX6VALID"
                },
                "PIPERX7CHANISALIGNED": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7CHANISALIGNED"
                },
                "PIPERX7CHARISK0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7CHARISK0"
                },
                "PIPERX7CHARISK1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7CHARISK1"
                },
                "PIPERX7DATA0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA0"
                },
                "PIPERX7DATA1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA1"
                },
                "PIPERX7DATA2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA2"
                },
                "PIPERX7DATA3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA3"
                },
                "PIPERX7DATA4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA4"
                },
                "PIPERX7DATA5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA5"
                },
                "PIPERX7DATA6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA6"
                },
                "PIPERX7DATA7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA7"
                },
                "PIPERX7DATA8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA8"
                },
                "PIPERX7DATA9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA9"
                },
                "PIPERX7DATA10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA10"
                },
                "PIPERX7DATA11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA11"
                },
                "PIPERX7DATA12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA12"
                },
                "PIPERX7DATA13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA13"
                },
                "PIPERX7DATA14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA14"
                },
                "PIPERX7DATA15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7DATA15"
                },
                "PIPERX7ELECIDLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7ELECIDLE"
                },
                "PIPERX7PHYSTATUS": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7PHYSTATUS"
                },
                "PIPERX7POLARITY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPERX7POLARITY"
                },
                "PIPERX7STATUS0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7STATUS0"
                },
                "PIPERX7STATUS1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7STATUS1"
                },
                "PIPERX7STATUS2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7STATUS2"
                },
                "PIPERX7VALID": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PIPERX7VALID"
                },
                "PIPETX0CHARISK0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0CHARISK0"
                },
                "PIPETX0CHARISK1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0CHARISK1"
                },
                "PIPETX0COMPLIANCE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0COMPLIANCE"
                },
                "PIPETX0DATA0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA0"
                },
                "PIPETX0DATA1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA1"
                },
                "PIPETX0DATA2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA2"
                },
                "PIPETX0DATA3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA3"
                },
                "PIPETX0DATA4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA4"
                },
                "PIPETX0DATA5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA5"
                },
                "PIPETX0DATA6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA6"
                },
                "PIPETX0DATA7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA7"
                },
                "PIPETX0DATA8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA8"
                },
                "PIPETX0DATA9": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA9"
                },
                "PIPETX0DATA10": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA10"
                },
                "PIPETX0DATA11": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA11"
                },
                "PIPETX0DATA12": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA12"
                },
                "PIPETX0DATA13": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA13"
                },
                "PIPETX0DATA14": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA14"
                },
                "PIPETX0DATA15": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0DATA15"
                },
                "PIPETX0ELECIDLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0ELECIDLE"
                },
                "PIPETX0POWERDOWN0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0POWERDOWN0"
                },
                "PIPETX0POWERDOWN1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX0POWERDOWN1"
                },
                "PIPETX1CHARISK0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1CHARISK0"
                },
                "PIPETX1CHARISK1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1CHARISK1"
                },
                "PIPETX1COMPLIANCE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1COMPLIANCE"
                },
                "PIPETX1DATA0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA0"
                },
                "PIPETX1DATA1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA1"
                },
                "PIPETX1DATA2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA2"
                },
                "PIPETX1DATA3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA3"
                },
                "PIPETX1DATA4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA4"
                },
                "PIPETX1DATA5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA5"
                },
                "PIPETX1DATA6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA6"
                },
                "PIPETX1DATA7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA7"
                },
                "PIPETX1DATA8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA8"
                },
                "PIPETX1DATA9": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA9"
                },
                "PIPETX1DATA10": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA10"
                },
                "PIPETX1DATA11": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA11"
                },
                "PIPETX1DATA12": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA12"
                },
                "PIPETX1DATA13": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA13"
                },
                "PIPETX1DATA14": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA14"
                },
                "PIPETX1DATA15": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1DATA15"
                },
                "PIPETX1ELECIDLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1ELECIDLE"
                },
                "PIPETX1POWERDOWN0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1POWERDOWN0"
                },
                "PIPETX1POWERDOWN1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX1POWERDOWN1"
                },
                "PIPETX2CHARISK0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX2CHARISK0"
                },
                "PIPETX2CHARISK1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX2CHARISK1"
                },
                "PIPETX2COMPLIANCE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX2COMPLIANCE"
                },
                "PIPETX2DATA0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX2DATA0"
                },
                "PIPETX2DATA1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX2DATA1"
                },
                "PIPETX2DATA2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX2DATA2"
                },
                "PIPETX2DATA3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX2DATA3"
                },
                "PIPETX2DATA4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX2DATA4"
                },
                "PIPETX2DATA5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX2DATA5"
                },
                "PIPETX2DATA6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX2DATA6"
                },
                "PIPETX2DATA7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX2DATA7"
                },
                "PIPETX2DATA8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "1375.0",
                    "wire": "PCIE_PIPETX2DATA8"
                },
                "PIPETX2DATA9": {
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                    "wire": "PCIE_PIPETX6DATA10"
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                "PIPETX6DATA11": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PIPETX6DATA11"
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                "PIPETX6DATA12": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PIPETX6DATA12"
                },
                "PIPETX6DATA13": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PIPETX6DATA13"
                },
                "PIPETX6DATA14": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PIPETX6DATA14"
                },
                "PIPETX6DATA15": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PIPETX6DATA15"
                },
                "PIPETX6ELECIDLE": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX6ELECIDLE"
                },
                "PIPETX6POWERDOWN0": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX6POWERDOWN0"
                },
                "PIPETX6POWERDOWN1": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX6POWERDOWN1"
                },
                "PIPETX7CHARISK0": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7CHARISK0"
                },
                "PIPETX7CHARISK1": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7CHARISK1"
                },
                "PIPETX7COMPLIANCE": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7COMPLIANCE"
                },
                "PIPETX7DATA0": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA0"
                },
                "PIPETX7DATA1": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA1"
                },
                "PIPETX7DATA2": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA2"
                },
                "PIPETX7DATA3": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA3"
                },
                "PIPETX7DATA4": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA4"
                },
                "PIPETX7DATA5": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA5"
                },
                "PIPETX7DATA6": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA6"
                },
                "PIPETX7DATA7": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA7"
                },
                "PIPETX7DATA8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA8"
                },
                "PIPETX7DATA9": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA9"
                },
                "PIPETX7DATA10": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA10"
                },
                "PIPETX7DATA11": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA11"
                },
                "PIPETX7DATA12": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA12"
                },
                "PIPETX7DATA13": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA13"
                },
                "PIPETX7DATA14": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA14"
                },
                "PIPETX7DATA15": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7DATA15"
                },
                "PIPETX7ELECIDLE": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7ELECIDLE"
                },
                "PIPETX7POWERDOWN0": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7POWERDOWN0"
                },
                "PIPETX7POWERDOWN1": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETX7POWERDOWN1"
                },
                "PIPETXDEEMPH": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETXDEEMPH"
                },
                "PIPETXMARGIN0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETXMARGIN0"
                },
                "PIPETXMARGIN1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETXMARGIN1"
                },
                "PIPETXMARGIN2": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETXMARGIN2"
                },
                "PIPETXRATE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETXRATE"
                },
                "PIPETXRCVRDET": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETXRCVRDET"
                },
                "PIPETXRESET": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PIPETXRESET"
                },
                "PL2DIRECTEDLSTATE0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PL2DIRECTEDLSTATE0"
                },
                "PL2DIRECTEDLSTATE1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PL2DIRECTEDLSTATE1"
                },
                "PL2DIRECTEDLSTATE2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PL2DIRECTEDLSTATE2"
                },
                "PL2DIRECTEDLSTATE3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PL2DIRECTEDLSTATE3"
                },
                "PL2DIRECTEDLSTATE4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PL2DIRECTEDLSTATE4"
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                "PL2L0REQ": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PL2L0REQ"
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                "PL2LINKUP": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PL2LINKUP"
                },
                "PL2RECEIVERERR": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PL2RECEIVERERR"
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                "PL2RECOVERY": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PL2RECOVERY"
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                "PL2RXELECIDLE": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PL2RXELECIDLE"
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                "PL2RXPMSTATE0": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PL2RXPMSTATE0"
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                "PL2RXPMSTATE1": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PL2RXPMSTATE1"
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                "PL2SUSPENDOK": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PL2SUSPENDOK"
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                "PLDBGMODE0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PLDBGMODE0"
                },
                "PLDBGMODE1": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PLDBGMODE1"
                },
                "PLDBGMODE2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PLDBGMODE2"
                },
                "PLDBGVEC0": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDBGVEC0"
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                "PLDBGVEC1": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDBGVEC1"
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                "PLDBGVEC2": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDBGVEC2"
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                "PLDBGVEC3": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDBGVEC3"
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                "PLDBGVEC4": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDBGVEC4"
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                "PLDBGVEC5": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDBGVEC5"
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                "PLDBGVEC6": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDBGVEC6"
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                "PLDBGVEC7": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDBGVEC7"
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                "PLDBGVEC8": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDBGVEC8"
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                "PLDBGVEC9": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDBGVEC9"
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                "PLDBGVEC10": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDBGVEC10"
                },
                "PLDBGVEC11": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDBGVEC11"
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                "PLDIRECTEDCHANGEDONE": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLDIRECTEDCHANGEDONE"
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                "PLDIRECTEDLINKAUTON": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PLDIRECTEDLINKAUTON"
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                "PLDIRECTEDLINKCHANGE0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PLDIRECTEDLINKCHANGE0"
                },
                "PLDIRECTEDLINKCHANGE1": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PLDIRECTEDLINKCHANGE1"
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                "PLDIRECTEDLINKSPEED": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PLDIRECTEDLINKSPEED"
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                "PLDIRECTEDLINKWIDTH0": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PLDIRECTEDLINKWIDTH0"
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                "PLDIRECTEDLINKWIDTH1": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PLDIRECTEDLINKWIDTH1"
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                "PLDIRECTEDLTSSMNEW0": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PLDIRECTEDLTSSMNEW0"
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                "PLDIRECTEDLTSSMNEW1": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PLDIRECTEDLTSSMNEW1"
                },
                "PLDIRECTEDLTSSMNEW2": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PLDIRECTEDLTSSMNEW2"
                },
                "PLDIRECTEDLTSSMNEW3": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PLDIRECTEDLTSSMNEW3"
                },
                "PLDIRECTEDLTSSMNEW4": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PLDIRECTEDLTSSMNEW4"
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                "PLDIRECTEDLTSSMNEW5": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PLDIRECTEDLTSSMNEW5"
                },
                "PLDIRECTEDLTSSMNEWVLD": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PLDIRECTEDLTSSMNEWVLD"
                },
                "PLDIRECTEDLTSSMSTALL": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "PCIE_PLDIRECTEDLTSSMSTALL"
                },
                "PLDOWNSTREAMDEEMPHSOURCE": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_PLDOWNSTREAMDEEMPHSOURCE"
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                "PLINITIALLINKWIDTH0": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLINITIALLINKWIDTH0"
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                "PLINITIALLINKWIDTH1": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLINITIALLINKWIDTH1"
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                "PLINITIALLINKWIDTH2": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLINITIALLINKWIDTH2"
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                "PLLANEREVERSALMODE0": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLLANEREVERSALMODE0"
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                "PLLANEREVERSALMODE1": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLLANEREVERSALMODE1"
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                "PLLINKGEN2CAP": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLLINKGEN2CAP"
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                "PLLINKPARTNERGEN2SUPPORTED": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLLINKPARTNERGEN2SUPPORTED"
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                "PLLINKUPCFGCAP": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLLINKUPCFGCAP"
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                "PLLTSSMSTATE0": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLLTSSMSTATE0"
                },
                "PLLTSSMSTATE1": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_PLLTSSMSTATE1"
                },
                "PLLTSSMSTATE2": {
                    "delay": [
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                    "wire": "PCIE_TRNTD89"
                },
                "TRNTD90": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD90"
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                "TRNTD91": {
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                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD91"
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                "TRNTD92": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD92"
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                "TRNTD93": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD93"
                },
                "TRNTD94": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD94"
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                "TRNTD95": {
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                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD95"
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                "TRNTD96": {
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                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD96"
                },
                "TRNTD97": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD97"
                },
                "TRNTD98": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD98"
                },
                "TRNTD99": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD99"
                },
                "TRNTD100": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD100"
                },
                "TRNTD101": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD101"
                },
                "TRNTD102": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD102"
                },
                "TRNTD103": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD103"
                },
                "TRNTD104": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD104"
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                "TRNTD105": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD105"
                },
                "TRNTD106": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD106"
                },
                "TRNTD107": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD107"
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                "TRNTD108": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD108"
                },
                "TRNTD109": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD109"
                },
                "TRNTD110": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD110"
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                "TRNTD111": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD111"
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                "TRNTD112": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD112"
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                "TRNTD113": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD113"
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                "TRNTD114": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD114"
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                "TRNTD115": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD115"
                },
                "TRNTD116": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD116"
                },
                "TRNTD117": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD117"
                },
                "TRNTD118": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD118"
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                "TRNTD119": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD119"
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                "TRNTD120": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD120"
                },
                "TRNTD121": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD121"
                },
                "TRNTD122": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD122"
                },
                "TRNTD123": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD123"
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                "TRNTD124": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD124"
                },
                "TRNTD125": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD125"
                },
                "TRNTD126": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD126"
                },
                "TRNTD127": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTD127"
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                "TRNTDLLPDATA0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA0"
                },
                "TRNTDLLPDATA1": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA1"
                },
                "TRNTDLLPDATA2": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA2"
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                "TRNTDLLPDATA3": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA3"
                },
                "TRNTDLLPDATA4": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA4"
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                "TRNTDLLPDATA5": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA5"
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                "TRNTDLLPDATA6": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA6"
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                "TRNTDLLPDATA7": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA7"
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                "TRNTDLLPDATA8": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA8"
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                "TRNTDLLPDATA9": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA9"
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                "TRNTDLLPDATA10": {
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA10"
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                "TRNTDLLPDATA11": {
                    "cap": "0.000",
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                        "0.000",
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA11"
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                "TRNTDLLPDATA12": {
                    "cap": "0.000",
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                        "0.000",
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA12"
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                "TRNTDLLPDATA13": {
                    "cap": "0.000",
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA13"
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                "TRNTDLLPDATA14": {
                    "cap": "0.000",
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA14"
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                "TRNTDLLPDATA15": {
                    "cap": "0.000",
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                        "0.000"
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                "TRNTDLLPDATA16": {
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA16"
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                "TRNTDLLPDATA17": {
                    "cap": "0.000",
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA17"
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                "TRNTDLLPDATA18": {
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA18"
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                "TRNTDLLPDATA19": {
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA19"
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                "TRNTDLLPDATA20": {
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA20"
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                "TRNTDLLPDATA21": {
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                        "0.000"
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                "TRNTDLLPDATA22": {
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA22"
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                "TRNTDLLPDATA23": {
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                        "0.000"
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                "TRNTDLLPDATA24": {
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                        "0.000"
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                "TRNTDLLPDATA25": {
                    "cap": "0.000",
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA25"
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                "TRNTDLLPDATA26": {
                    "cap": "0.000",
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                        "0.000"
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                "TRNTDLLPDATA27": {
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA27"
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                "TRNTDLLPDATA28": {
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA28"
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                "TRNTDLLPDATA29": {
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA29"
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                "TRNTDLLPDATA30": {
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA30"
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                "TRNTDLLPDATA31": {
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                        "0.000"
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                    "wire": "PCIE_TRNTDLLPDATA31"
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                "TRNTDLLPDSTRDY": {
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                    "res": "1375.0",
                    "wire": "PCIE_TRNTDLLPDSTRDY"
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                "TRNTDLLPSRCRDY": {
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTDLLPSRCRDY"
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                "TRNTDSTRDY0": {
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                    "res": "1375.0",
                    "wire": "PCIE_TRNTDSTRDY0"
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                "TRNTDSTRDY1": {
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                    "res": "1375.0",
                    "wire": "PCIE_TRNTDSTRDY1"
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                "TRNTDSTRDY2": {
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                    "res": "1375.0",
                    "wire": "PCIE_TRNTDSTRDY2"
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                "TRNTDSTRDY3": {
                    "delay": [
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                    "res": "1375.0",
                    "wire": "PCIE_TRNTDSTRDY3"
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                "TRNTECRCGEN": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTECRCGEN"
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                "TRNTEOF": {
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                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTEOF"
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                "TRNTERRDROP": {
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                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_TRNTERRDROP"
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                "TRNTERRFWD": {
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTERRFWD"
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                "TRNTREM0": {
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                        "0.000"
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                    "wire": "PCIE_TRNTREM0"
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                "TRNTREM1": {
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                        "0.000"
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                    "wire": "PCIE_TRNTREM1"
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                "TRNTSOF": {
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                    "delay": [
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                        "0.000"
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                    "wire": "PCIE_TRNTSOF"
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                "TRNTSRCDSC": {
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                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTSRCDSC"
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                "TRNTSRCRDY": {
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                        "0.000"
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                    "wire": "PCIE_TRNTSRCRDY"
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                "TRNTSTR": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_TRNTSTR"
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                "USERCLK": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_USERCLK"
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                "USERCLK2": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "PCIE_USERCLK2"
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                "USERCLKPREBUF": {
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                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_USERCLKPREBUF"
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                "USERCLKPREBUFEN": {
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                    "delay": [
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                        "0.000",
                        "0.000"
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                    "wire": "PCIE_USERCLKPREBUFEN"
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                "USERRSTN": {
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                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_USERRSTN"
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                    "res": "1375.0",
                    "wire": "PCIE_XILUNCONNOUT0"
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                "XILUNCONNOUT1": {
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                    "res": "1375.0",
                    "wire": "PCIE_XILUNCONNOUT1"
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                "XILUNCONNOUT2": {
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                    "res": "1375.0",
                    "wire": "PCIE_XILUNCONNOUT2"
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                "XILUNCONNOUT3": {
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                        "0.000"
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                    "res": "1375.0",
                    "wire": "PCIE_XILUNCONNOUT3"
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                "XILUNCONNOUT4": {
                    "delay": [
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                        "0.000"
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        "PCIE_CFGMGMTWRENN": null,
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        "PCIE_CFGPMRCVASREQL1N": null,
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        "PCIE_CFGPMTURNOFFOKN": null,
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        "PCIE_CFGROOTCONTROLSYSERRCORRERREN": null,
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        "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE": null,
        "PCIE_CFGSUBSYSID0": null,
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        "PCIE_CFGSUBSYSVENDID14": null,
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        "PCIE_CFGTRANSACTIONTYPE": null,
        "PCIE_CFGTRNPENDINGN": null,
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        "PCIE_CFGVCTCVCMAP2": null,
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        "PCIE_CFGVENDID0": null,
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        "PCIE_CLK0_L_1": {
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            "res": "0.000"
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        "PCIE_CLK0_L_2": {
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        "PCIE_CLK0_L_3": {
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        "PCIE_CLK0_L_4": {
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        "PCIE_CLK0_L_5": {
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            "res": "0.000"
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        "PCIE_CLK0_L_6": {
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        "PCIE_CLK0_L_7": {
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            "res": "0.000"
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        "PCIE_CLK0_L_8": {
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            "res": "0.000"
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        "PCIE_CLK0_L_9": {
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        "PCIE_CLK0_L_10": {
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        "PCIE_CLK0_L_11": {
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        "PCIE_CLK0_L_12": {
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            "res": "0.000"
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        "PCIE_CLK0_L_13": {
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            "res": "0.000"
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        "PCIE_CLK0_L_14": {
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            "res": "0.000"
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        "PCIE_CLK0_L_15": {
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        "PCIE_CLK0_L_16": {
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        "PCIE_CLK0_L_17": {
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        "PCIE_CLK0_L_18": {
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        "PCIE_CLK0_L_19": {
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        "PCIE_CLK0_R_0": {
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            "res": "0.000"
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        "PCIE_CLK0_R_1": {
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            "res": "0.000"
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        "PCIE_CLK0_R_2": {
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        "PCIE_CLK0_R_3": {
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        "PCIE_CLK0_R_4": {
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        "PCIE_CLK0_R_5": {
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        "PCIE_CLK0_R_6": {
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        "PCIE_CLK0_R_7": {
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        "PCIE_CLK0_R_8": {
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            "res": "0.000"
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        "PCIE_CLK0_R_9": {
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        "PCIE_CLK0_R_10": {
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        "PCIE_CLK0_R_11": {
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        "PCIE_CLK0_R_12": {
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        "PCIE_CLK0_R_13": {
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            "res": "0.000"
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        "PCIE_CLK0_R_14": {
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        "PCIE_CLK0_R_15": {
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        "PCIE_CLK0_R_16": {
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        "PCIE_CLK0_R_17": {
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        "PCIE_CLK0_R_18": {
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        "PCIE_CLK0_R_19": {
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        "PCIE_CLK1_L_0": {
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        "PCIE_CLK1_L_1": {
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        "PCIE_CLK1_L_2": {
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        "PCIE_CLK1_L_3": {
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        "PCIE_CLK1_L_4": {
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        "PCIE_CLK1_L_5": {
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        "PCIE_CLK1_L_6": {
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        "PCIE_CLK1_L_7": {
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        "PCIE_CLK1_L_8": {
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        "PCIE_CLK1_L_9": {
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