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"IMUX3" ], [ "INT_INTERFACE_BRAM_IMUX4", "IMUX4" ], [ "INT_INTERFACE_BRAM_IMUX5", "IMUX5" ], [ "INT_INTERFACE_BRAM_IMUX6", "IMUX6" ], [ "INT_INTERFACE_BRAM_IMUX7", "IMUX7" ], [ "INT_INTERFACE_BRAM_IMUX8", "IMUX8" ], [ "INT_INTERFACE_BRAM_IMUX9", "IMUX9" ], [ "INT_INTERFACE_BRAM_IMUX10", "IMUX10" ], [ "INT_INTERFACE_BRAM_IMUX11", "IMUX11" ], [ "INT_INTERFACE_BRAM_IMUX12", "IMUX12" ], [ "INT_INTERFACE_BRAM_IMUX13", "IMUX13" ], [ "INT_INTERFACE_BRAM_IMUX14", "IMUX14" ], [ "INT_INTERFACE_BRAM_IMUX15", "IMUX15" ], [ "INT_INTERFACE_BRAM_IMUX16", "IMUX16" ], [ "INT_INTERFACE_BRAM_IMUX17", "IMUX17" ], [ "INT_INTERFACE_BRAM_IMUX18", "IMUX18" ], [ "INT_INTERFACE_BRAM_IMUX19", "IMUX19" ], [ "INT_INTERFACE_BRAM_IMUX20", "IMUX20" ], [ "INT_INTERFACE_BRAM_IMUX21", "IMUX21" ], [ "INT_INTERFACE_BRAM_IMUX22", "IMUX22" ], [ "INT_INTERFACE_BRAM_IMUX23", "IMUX23" ], [ "INT_INTERFACE_BRAM_IMUX24", "IMUX24" ], [ "INT_INTERFACE_BRAM_IMUX25", "IMUX25" ], [ "INT_INTERFACE_BRAM_IMUX26", "IMUX26" ], [ "INT_INTERFACE_BRAM_IMUX27", "IMUX27" ], [ "INT_INTERFACE_BRAM_IMUX28", "IMUX28" ], [ "INT_INTERFACE_BRAM_IMUX29", "IMUX29" ], [ "INT_INTERFACE_BRAM_IMUX30", "IMUX30" ], [ "INT_INTERFACE_BRAM_IMUX31", "IMUX31" ], [ "INT_INTERFACE_BRAM_IMUX32", "IMUX32" ], [ "INT_INTERFACE_BRAM_IMUX33", "IMUX33" ], [ "INT_INTERFACE_BRAM_IMUX34", "IMUX34" ], [ "INT_INTERFACE_BRAM_IMUX35", "IMUX35" ], [ "INT_INTERFACE_BRAM_IMUX36", "IMUX36" ], [ "INT_INTERFACE_BRAM_IMUX37", "IMUX37" ], [ "INT_INTERFACE_BRAM_IMUX38", "IMUX38" ], [ "INT_INTERFACE_BRAM_IMUX39", "IMUX39" ], [ "INT_INTERFACE_BRAM_IMUX40", "IMUX40" ], [ "INT_INTERFACE_BRAM_IMUX41", "IMUX41" ], [ "INT_INTERFACE_BRAM_IMUX42", "IMUX42" ], [ "INT_INTERFACE_BRAM_IMUX43", "IMUX43" ], [ "INT_INTERFACE_BRAM_IMUX44", "IMUX44" ], [ "INT_INTERFACE_BRAM_IMUX45", "IMUX45" ], [ "INT_INTERFACE_BRAM_IMUX46", "IMUX46" ], [ "INT_INTERFACE_BRAM_IMUX47", "IMUX47" ], [ "INT_INTERFACE_BYP0", "BYP0" ], [ "INT_INTERFACE_BYP1", "BYP1" ], [ "INT_INTERFACE_BYP2", "BYP2" ], [ "INT_INTERFACE_BYP3", "BYP3" ], [ "INT_INTERFACE_BYP4", "BYP4" ], [ "INT_INTERFACE_BYP5", "BYP5" ], [ "INT_INTERFACE_BYP6", "BYP6" ], [ "INT_INTERFACE_BYP7", "BYP7" ], [ "INT_INTERFACE_CLK0", "CLK0" ], [ "INT_INTERFACE_CLK1", "CLK1" ], [ "INT_INTERFACE_CTRL0", "CTRL0" ], [ "INT_INTERFACE_CTRL1", "CTRL1" ], [ "INT_INTERFACE_EE2A0", "EE2A0" ], [ "INT_INTERFACE_EE2A1", "EE2A1" ], [ "INT_INTERFACE_EE2A2", "EE2A2" ], [ "INT_INTERFACE_EE2A3", "EE2A3" ], [ "INT_INTERFACE_EE2BEG0", "EE2BEG0" ], [ "INT_INTERFACE_EE2BEG1", "EE2BEG1" ], [ "INT_INTERFACE_EE2BEG2", "EE2BEG2" ], [ "INT_INTERFACE_EE2BEG3", "EE2BEG3" ], [ "INT_INTERFACE_EE4A0", "EE4A0" ], [ "INT_INTERFACE_EE4A1", "EE4A1" ], [ "INT_INTERFACE_EE4A2", "EE4A2" ], [ "INT_INTERFACE_EE4A3", "EE4A3" ], [ "INT_INTERFACE_EE4B0", "EE4B0" ], [ "INT_INTERFACE_EE4B1", "EE4B1" ], [ "INT_INTERFACE_EE4B2", "EE4B2" ], [ "INT_INTERFACE_EE4B3", "EE4B3" ], [ "INT_INTERFACE_EE4BEG0", "EE4BEG0" ], [ "INT_INTERFACE_EE4BEG1", "EE4BEG1" ], [ "INT_INTERFACE_EE4BEG2", "EE4BEG2" ], [ "INT_INTERFACE_EE4BEG3", "EE4BEG3" ], [ "INT_INTERFACE_EE4C0", "EE4C0" ], [ "INT_INTERFACE_EE4C1", "EE4C1" ], [ "INT_INTERFACE_EE4C2", "EE4C2" ], [ "INT_INTERFACE_EE4C3", "EE4C3" ], [ "INT_INTERFACE_EL1BEG0", "EL1BEG0" ], [ "INT_INTERFACE_EL1BEG1", "EL1BEG1" ], [ "INT_INTERFACE_EL1BEG2", "EL1BEG2" ], [ "INT_INTERFACE_EL1BEG3", "EL1BEG3" ], [ "INT_INTERFACE_ER1BEG0", "ER1BEG0" ], [ "INT_INTERFACE_ER1BEG1", "ER1BEG1" ], [ "INT_INTERFACE_ER1BEG2", "ER1BEG2" ], [ "INT_INTERFACE_ER1BEG3", "ER1BEG3" ], [ "INT_INTERFACE_FAN0", "FAN0" ], [ "INT_INTERFACE_FAN1", "FAN1" ], [ "INT_INTERFACE_FAN2", "FAN2" ], [ "INT_INTERFACE_FAN3", "FAN3" ], [ "INT_INTERFACE_FAN4", "FAN4" ], [ "INT_INTERFACE_FAN5", "FAN5" ], [ "INT_INTERFACE_FAN6", "FAN6" ], [ "INT_INTERFACE_FAN7", "FAN7" ], [ "INT_INTERFACE_LH1", "LH1" ], [ "INT_INTERFACE_LH2", "LH2" ], [ "INT_INTERFACE_LH3", "LH3" ], [ "INT_INTERFACE_LH4", "LH4" ], [ "INT_INTERFACE_LH5", "LH5" ], [ "INT_INTERFACE_LH6", "LH6" ], [ "INT_INTERFACE_LH7", "LH7" ], [ "INT_INTERFACE_LH8", "LH8" ], [ "INT_INTERFACE_LH9", "LH9" ], [ "INT_INTERFACE_LH10", "LH10" ], [ "INT_INTERFACE_LH11", "LH11" ], [ "INT_INTERFACE_LH12", "LH12" ], [ "INT_INTERFACE_LOGIC_OUTS0", "LOGIC_OUTS0" ], [ "INT_INTERFACE_LOGIC_OUTS1", "LOGIC_OUTS1" ], [ "INT_INTERFACE_LOGIC_OUTS2", "LOGIC_OUTS2" ], [ "INT_INTERFACE_LOGIC_OUTS3", "LOGIC_OUTS3" ], [ "INT_INTERFACE_LOGIC_OUTS4", "LOGIC_OUTS4" ], [ "INT_INTERFACE_LOGIC_OUTS5", "LOGIC_OUTS5" ], [ "INT_INTERFACE_LOGIC_OUTS6", "LOGIC_OUTS6" ], [ "INT_INTERFACE_LOGIC_OUTS7", "LOGIC_OUTS7" ], [ "INT_INTERFACE_LOGIC_OUTS8", "LOGIC_OUTS8" ], [ "INT_INTERFACE_LOGIC_OUTS9", "LOGIC_OUTS9" ], [ "INT_INTERFACE_LOGIC_OUTS10", "LOGIC_OUTS10" ], [ "INT_INTERFACE_LOGIC_OUTS11", "LOGIC_OUTS11" ], [ "INT_INTERFACE_LOGIC_OUTS12", "LOGIC_OUTS12" ], [ "INT_INTERFACE_LOGIC_OUTS13", "LOGIC_OUTS13" ], [ "INT_INTERFACE_LOGIC_OUTS14", "LOGIC_OUTS14" ], [ "INT_INTERFACE_LOGIC_OUTS15", "LOGIC_OUTS15" ], [ "INT_INTERFACE_LOGIC_OUTS16", "LOGIC_OUTS16" ], [ "INT_INTERFACE_LOGIC_OUTS17", "LOGIC_OUTS17" ], [ "INT_INTERFACE_LOGIC_OUTS18", "LOGIC_OUTS18" ], [ "INT_INTERFACE_LOGIC_OUTS19", "LOGIC_OUTS19" ], [ "INT_INTERFACE_LOGIC_OUTS20", "LOGIC_OUTS20" ], [ "INT_INTERFACE_LOGIC_OUTS21", "LOGIC_OUTS21" ], [ "INT_INTERFACE_LOGIC_OUTS22", "LOGIC_OUTS22" ], [ "INT_INTERFACE_LOGIC_OUTS23", "LOGIC_OUTS23" ], [ "INT_INTERFACE_MONITOR_N", "MONITOR_N" ], [ "INT_INTERFACE_MONITOR_P", "MONITOR_P" ], [ "INT_INTERFACE_NE2A0", "NE2A0" ], [ "INT_INTERFACE_NE2A1", "NE2A1" ], [ "INT_INTERFACE_NE2A2", "NE2A2" ], [ "INT_INTERFACE_NE2A3", "NE2A3" ], [ "INT_INTERFACE_NE4BEG0", "NE6BEG0" ], [ "INT_INTERFACE_NE4BEG1", "NE6BEG1" ], [ "INT_INTERFACE_NE4BEG2", "NE6BEG2" ], [ "INT_INTERFACE_NE4BEG3", "NE6BEG3" ], [ "INT_INTERFACE_NE4C0", "NE6E0" ], [ "INT_INTERFACE_NE4C1", "NE6E1" ], [ "INT_INTERFACE_NE4C2", "NE6E2" ], [ "INT_INTERFACE_NE4C3", "NE6E3" ], [ "INT_INTERFACE_NW2A0", "NW2END0" ], [ "INT_INTERFACE_NW2A1", "NW2END1" ], [ "INT_INTERFACE_NW2A2", "NW2END2" ], [ "INT_INTERFACE_NW2A3", "NW2END3" ], [ "INT_INTERFACE_NW4A0", "NW6A0" ], [ "INT_INTERFACE_NW4A1", "NW6A1" ], [ "INT_INTERFACE_NW4A2", "NW6A2" ], [ "INT_INTERFACE_NW4A3", "NW6A3" ], [ "INT_INTERFACE_NW4END0", "NW6END0" ], [ "INT_INTERFACE_NW4END1", "NW6END1" ], [ "INT_INTERFACE_NW4END2", "NW6END2" ], [ "INT_INTERFACE_NW4END3", "NW6END3" ], [ "INT_INTERFACE_SE2A0", "SE2A0" ], [ "INT_INTERFACE_SE2A1", "SE2A1" ], [ "INT_INTERFACE_SE2A2", "SE2A2" ], [ "INT_INTERFACE_SE2A3", "SE2A3" ], [ "INT_INTERFACE_SE4BEG0", "SE6BEG0" ], [ "INT_INTERFACE_SE4BEG1", "SE6BEG1" ], [ "INT_INTERFACE_SE4BEG2", "SE6BEG2" ], [ "INT_INTERFACE_SE4BEG3", "SE6BEG3" ], [ "INT_INTERFACE_SE4C0", "SE6E0" ], [ "INT_INTERFACE_SE4C1", "SE6E1" ], [ "INT_INTERFACE_SE4C2", "SE6E2" ], [ "INT_INTERFACE_SE4C3", "SE6E3" ], [ "INT_INTERFACE_SW2A0", "SW2END0" ], [ "INT_INTERFACE_SW2A1", "SW2END1" ], [ "INT_INTERFACE_SW2A2", "SW2END2" ], [ "INT_INTERFACE_SW2A3", "SW2END3" ], [ "INT_INTERFACE_SW4A0", "SW6A0" ], [ "INT_INTERFACE_SW4A1", "SW6A1" ], [ "INT_INTERFACE_SW4A2", "SW6A2" ], [ "INT_INTERFACE_SW4A3", "SW6A3" ], [ "INT_INTERFACE_SW4END0", "SW6END0" ], [ "INT_INTERFACE_SW4END1", "SW6END1" ], [ "INT_INTERFACE_SW4END2", "SW6END2" ], [ "INT_INTERFACE_SW4END3", "SW6END3" ], [ "INT_INTERFACE_WL1END0", "WL1END0" ], [ "INT_INTERFACE_WL1END1", "WL1END1" ], [ "INT_INTERFACE_WL1END2", "WL1END2" ], [ "INT_INTERFACE_WL1END3", "WL1END3" ], [ "INT_INTERFACE_WR1END0", "WR1END0" ], [ "INT_INTERFACE_WR1END1", "WR1END1" ], [ "INT_INTERFACE_WR1END2", "WR1END2" ], [ "INT_INTERFACE_WR1END3", "WR1END3" ], [ "INT_INTERFACE_WW2A0", "WW2A0" ], [ "INT_INTERFACE_WW2A1", "WW2A1" ], [ "INT_INTERFACE_WW2A2", "WW2A2" ], [ "INT_INTERFACE_WW2A3", "WW2A3" ], [ "INT_INTERFACE_WW2END0", "WW2END0" ], [ "INT_INTERFACE_WW2END1", "WW2END1" ], [ "INT_INTERFACE_WW2END2", "WW2END2" ], [ "INT_INTERFACE_WW2END3", "WW2END3" ], [ "INT_INTERFACE_WW4A0", "WW4A0" ], [ "INT_INTERFACE_WW4A1", "WW4A1" ], [ "INT_INTERFACE_WW4A2", "WW4A2" ], [ "INT_INTERFACE_WW4A3", "WW4A3" ], [ "INT_INTERFACE_WW4B0", "WW4B0" ], [ "INT_INTERFACE_WW4B1", "WW4B1" ], [ "INT_INTERFACE_WW4B2", "WW4B2" ], [ "INT_INTERFACE_WW4B3", "WW4B3" ], [ "INT_INTERFACE_WW4C0", "WW4C0" ], [ "INT_INTERFACE_WW4C1", "WW4C1" ], [ "INT_INTERFACE_WW4C2", "WW4C2" ], [ "INT_INTERFACE_WW4C3", "WW4C3" ], [ "INT_INTERFACE_WW4END0", "WW4END0" ], [ "INT_INTERFACE_WW4END1", "WW4END1" ], [ "INT_INTERFACE_WW4END2", "WW4END2" ], [ "INT_INTERFACE_WW4END3", "WW4END3" ] ] }, { "grid_deltas": [ 0, -5 ], "tile_types": [ "BRAM_L", "BRAM_L" ], "wire_pairs": [ [ "BRAM_CASCINTOP_ADDRARDADDRU0", "BRAM_CASCOUT_ADDRARDADDRU0" ], [ "BRAM_CASCINTOP_ADDRARDADDRU1", "BRAM_CASCOUT_ADDRARDADDRU1" ], [ "BRAM_CASCINTOP_ADDRARDADDRU2", "BRAM_CASCOUT_ADDRARDADDRU2" ], [ "BRAM_CASCINTOP_ADDRARDADDRU3", "BRAM_CASCOUT_ADDRARDADDRU3" ], [ "BRAM_CASCINTOP_ADDRARDADDRU4", "BRAM_CASCOUT_ADDRARDADDRU4" ], [ "BRAM_CASCINTOP_ADDRARDADDRU5", "BRAM_CASCOUT_ADDRARDADDRU5" ], [ "BRAM_CASCINTOP_ADDRARDADDRU6", "BRAM_CASCOUT_ADDRARDADDRU6" ], [ "BRAM_CASCINTOP_ADDRARDADDRU7", "BRAM_CASCOUT_ADDRARDADDRU7" ], [ "BRAM_CASCINTOP_ADDRARDADDRU8", "BRAM_CASCOUT_ADDRARDADDRU8" ], [ "BRAM_CASCINTOP_ADDRARDADDRU9", "BRAM_CASCOUT_ADDRARDADDRU9" ], [ "BRAM_CASCINTOP_ADDRARDADDRU10", "BRAM_CASCOUT_ADDRARDADDRU10" ], [ "BRAM_CASCINTOP_ADDRARDADDRU11", "BRAM_CASCOUT_ADDRARDADDRU11" ], [ "BRAM_CASCINTOP_ADDRARDADDRU12", "BRAM_CASCOUT_ADDRARDADDRU12" ], [ "BRAM_CASCINTOP_ADDRARDADDRU13", "BRAM_CASCOUT_ADDRARDADDRU13" ], [ "BRAM_CASCINTOP_ADDRARDADDRU14", "BRAM_CASCOUT_ADDRARDADDRU14" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU0", "BRAM_CASCOUT_ADDRBWRADDRU0" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU1", "BRAM_CASCOUT_ADDRBWRADDRU1" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU2", "BRAM_CASCOUT_ADDRBWRADDRU2" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU3", "BRAM_CASCOUT_ADDRBWRADDRU3" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU4", "BRAM_CASCOUT_ADDRBWRADDRU4" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU5", "BRAM_CASCOUT_ADDRBWRADDRU5" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU6", "BRAM_CASCOUT_ADDRBWRADDRU6" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU7", "BRAM_CASCOUT_ADDRBWRADDRU7" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU8", "BRAM_CASCOUT_ADDRBWRADDRU8" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU9", "BRAM_CASCOUT_ADDRBWRADDRU9" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU10", "BRAM_CASCOUT_ADDRBWRADDRU10" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU11", "BRAM_CASCOUT_ADDRBWRADDRU11" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU12", "BRAM_CASCOUT_ADDRBWRADDRU12" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU13", "BRAM_CASCOUT_ADDRBWRADDRU13" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU14", "BRAM_CASCOUT_ADDRBWRADDRU14" ], [ "BRAM_PMVBRAM_O", "BRAM_PMVBRAM_O_1" ], [ "BRAM_PMVBRAM_ODIV2", "BRAM_PMVBRAM_ODIV2_1" ], [ "BRAM_PMVBRAM_O_1", "BRAM_PMVBRAM_O_2" ] ] }, { "grid_deltas": [ 0, 5 ], "tile_types": [ "BRAM_L", "BRAM_L" ], "wire_pairs": [ [ "BRAM_CASCINBOT_ADDRARDADDRU0", "BRAM_CASCOUT_ADDRARDADDRU0" ], [ "BRAM_CASCINBOT_ADDRARDADDRU1", "BRAM_CASCOUT_ADDRARDADDRU1" ], [ "BRAM_CASCINBOT_ADDRARDADDRU2", "BRAM_CASCOUT_ADDRARDADDRU2" ], [ "BRAM_CASCINBOT_ADDRARDADDRU3", "BRAM_CASCOUT_ADDRARDADDRU3" ], [ "BRAM_CASCINBOT_ADDRARDADDRU4", "BRAM_CASCOUT_ADDRARDADDRU4" ], [ "BRAM_CASCINBOT_ADDRARDADDRU5", "BRAM_CASCOUT_ADDRARDADDRU5" ], [ "BRAM_CASCINBOT_ADDRARDADDRU6", "BRAM_CASCOUT_ADDRARDADDRU6" ], [ "BRAM_CASCINBOT_ADDRARDADDRU7", "BRAM_CASCOUT_ADDRARDADDRU7" ], [ "BRAM_CASCINBOT_ADDRARDADDRU8", "BRAM_CASCOUT_ADDRARDADDRU8" ], [ "BRAM_CASCINBOT_ADDRARDADDRU9", "BRAM_CASCOUT_ADDRARDADDRU9" ], [ "BRAM_CASCINBOT_ADDRARDADDRU10", "BRAM_CASCOUT_ADDRARDADDRU10" ], [ "BRAM_CASCINBOT_ADDRARDADDRU11", "BRAM_CASCOUT_ADDRARDADDRU11" ], [ "BRAM_CASCINBOT_ADDRARDADDRU12", "BRAM_CASCOUT_ADDRARDADDRU12" ], [ "BRAM_CASCINBOT_ADDRARDADDRU13", "BRAM_CASCOUT_ADDRARDADDRU13" ], [ "BRAM_CASCINBOT_ADDRARDADDRU14", "BRAM_CASCOUT_ADDRARDADDRU14" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU0", "BRAM_CASCOUT_ADDRBWRADDRU0" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU1", "BRAM_CASCOUT_ADDRBWRADDRU1" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU2", "BRAM_CASCOUT_ADDRBWRADDRU2" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU3", "BRAM_CASCOUT_ADDRBWRADDRU3" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU4", "BRAM_CASCOUT_ADDRBWRADDRU4" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU5", "BRAM_CASCOUT_ADDRBWRADDRU5" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU6", "BRAM_CASCOUT_ADDRBWRADDRU6" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU7", "BRAM_CASCOUT_ADDRBWRADDRU7" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU8", "BRAM_CASCOUT_ADDRBWRADDRU8" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU9", "BRAM_CASCOUT_ADDRBWRADDRU9" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU10", "BRAM_CASCOUT_ADDRBWRADDRU10" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU11", "BRAM_CASCOUT_ADDRBWRADDRU11" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU12", "BRAM_CASCOUT_ADDRBWRADDRU12" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU13", "BRAM_CASCOUT_ADDRBWRADDRU13" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU14", "BRAM_CASCOUT_ADDRBWRADDRU14" ], [ "BRAM_FIFO36_CASCADEINA", "BRAM_FIFO36_CASCADEOUTA_1" ], [ "BRAM_FIFO36_CASCADEINB", "BRAM_FIFO36_CASCADEOUTB_1" ] ] }, { "grid_deltas": [ 0, -5 ], "tile_types": [ "BRAM_L", "BRKH_BRAM" ], "wire_pairs": [ [ "BRAM_CASCINTOP_ADDRARDADDRU0", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" ], [ "BRAM_CASCINTOP_ADDRARDADDRU1", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" ], [ "BRAM_CASCINTOP_ADDRARDADDRU2", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2" ], [ "BRAM_CASCINTOP_ADDRARDADDRU3", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" ], [ "BRAM_CASCINTOP_ADDRARDADDRU4", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" ], [ "BRAM_CASCINTOP_ADDRARDADDRU5", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" ], [ "BRAM_CASCINTOP_ADDRARDADDRU6", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" ], [ "BRAM_CASCINTOP_ADDRARDADDRU7", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" ], [ "BRAM_CASCINTOP_ADDRARDADDRU8", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" ], [ "BRAM_CASCINTOP_ADDRARDADDRU9", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" ], [ "BRAM_CASCINTOP_ADDRARDADDRU10", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" ], [ "BRAM_CASCINTOP_ADDRARDADDRU11", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" ], [ "BRAM_CASCINTOP_ADDRARDADDRU12", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" ], [ "BRAM_CASCINTOP_ADDRARDADDRU13", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" ], [ "BRAM_CASCINTOP_ADDRARDADDRU14", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU0", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU1", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU2", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU3", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU4", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU5", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU6", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU7", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU8", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU9", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU10", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU11", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU12", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU13", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU14", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ "BRAM_CASCOUT_ADDRARDADDRU0", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ "BRAM_CASCOUT_ADDRARDADDRU1", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" ], [ "BRAM_CASCOUT_ADDRARDADDRU2", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" ], [ "BRAM_CASCOUT_ADDRARDADDRU3", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" ], [ "BRAM_CASCOUT_ADDRARDADDRU4", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" ], [ "BRAM_CASCOUT_ADDRARDADDRU5", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" ], [ "BRAM_CASCOUT_ADDRARDADDRU6", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" ], [ "BRAM_CASCOUT_ADDRARDADDRU7", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" ], [ "BRAM_CASCOUT_ADDRARDADDRU8", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" ], [ "BRAM_CASCOUT_ADDRARDADDRU9", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" ], [ 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"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ "BRAM_FIFO36_CASCADEINA", "BRKH_BRAM_CASCADEA_L" ], [ "BRAM_FIFO36_CASCADEINB", "BRKH_BRAM_CASCADEB_L" ] ] }, { "grid_deltas": [ -1, -4 ], "tile_types": [ "BRAM_L", "CLBLM_R" ], "wire_pairs": [ [ "BRAM_EE2A0_4", "CLBLM_EE2A0" ], [ "BRAM_EE2A1_4", "CLBLM_EE2A1" ], [ "BRAM_EE2A2_4", "CLBLM_EE2A2" ], [ "BRAM_EE2A3_4", "CLBLM_EE2A3" ], [ "BRAM_EE2BEG0_4", "CLBLM_EE2BEG0" ], [ "BRAM_EE2BEG1_4", "CLBLM_EE2BEG1" ], [ "BRAM_EE2BEG2_4", "CLBLM_EE2BEG2" ], [ "BRAM_EE2BEG3_4", "CLBLM_EE2BEG3" ], [ "BRAM_EE4A0_4", "CLBLM_EE4A0" ], [ "BRAM_EE4A1_4", "CLBLM_EE4A1" ], [ "BRAM_EE4A2_4", "CLBLM_EE4A2" ], [ "BRAM_EE4A3_4", "CLBLM_EE4A3" ], [ "BRAM_EE4B0_4", "CLBLM_EE4B0" ], [ "BRAM_EE4B1_4", "CLBLM_EE4B1" ], [ "BRAM_EE4B2_4", "CLBLM_EE4B2" ], [ "BRAM_EE4B3_4", "CLBLM_EE4B3" ], [ "BRAM_EE4BEG0_4", "CLBLM_EE4BEG0" ], [ "BRAM_EE4BEG1_4", "CLBLM_EE4BEG1" ], [ "BRAM_EE4BEG2_4", "CLBLM_EE4BEG2" ], [ "BRAM_EE4BEG3_4", "CLBLM_EE4BEG3" ], [ "BRAM_EE4C0_4", "CLBLM_EE4C0" ], [ "BRAM_EE4C1_4", "CLBLM_EE4C1" ], [ "BRAM_EE4C2_4", "CLBLM_EE4C2" ], [ "BRAM_EE4C3_4", "CLBLM_EE4C3" ], [ "BRAM_EL1BEG0_4", "CLBLM_EL1BEG0" ], [ "BRAM_EL1BEG1_4", "CLBLM_EL1BEG1" ], [ "BRAM_EL1BEG2_4", "CLBLM_EL1BEG2" ], [ "BRAM_EL1BEG3_4", "CLBLM_EL1BEG3" ], [ "BRAM_ER1BEG0_4", "CLBLM_ER1BEG0" ], [ "BRAM_ER1BEG1_4", "CLBLM_ER1BEG1" ], [ "BRAM_ER1BEG2_4", "CLBLM_ER1BEG2" ], [ "BRAM_ER1BEG3_4", "CLBLM_ER1BEG3" ], [ "BRAM_LH1_4", "CLBLM_LH1" ], [ "BRAM_LH2_4", "CLBLM_LH2" ], [ "BRAM_LH3_4", "CLBLM_LH3" ], [ "BRAM_LH4_4", "CLBLM_LH4" ], [ "BRAM_LH5_4", "CLBLM_LH5" ], [ "BRAM_LH6_4", "CLBLM_LH6" ], [ "BRAM_LH7_4", "CLBLM_LH7" ], [ "BRAM_LH8_4", "CLBLM_LH8" ], [ "BRAM_LH9_4", "CLBLM_LH9" ], [ "BRAM_LH10_4", "CLBLM_LH10" ], [ "BRAM_LH11_4", "CLBLM_LH11" ], [ "BRAM_LH12_4", "CLBLM_LH12" ], [ "BRAM_MONITOR_N_4", "CLBLM_MONITOR_N" ], [ "BRAM_MONITOR_P_4", "CLBLM_MONITOR_P" ], [ "BRAM_NE2A0_4", "CLBLM_NE2A0" ], [ "BRAM_NE2A1_4", "CLBLM_NE2A1" ], [ "BRAM_NE2A2_4", "CLBLM_NE2A2" ], [ "BRAM_NE2A3_4", "CLBLM_NE2A3" ], [ "BRAM_NE4BEG0_4", "CLBLM_NE4BEG0" ], [ "BRAM_NE4BEG1_4", "CLBLM_NE4BEG1" ], [ "BRAM_NE4BEG2_4", "CLBLM_NE4BEG2" ], [ "BRAM_NE4BEG3_4", "CLBLM_NE4BEG3" ], [ "BRAM_NE4C0_4", "CLBLM_NE4C0" ], [ "BRAM_NE4C1_4", "CLBLM_NE4C1" ], [ "BRAM_NE4C2_4", "CLBLM_NE4C2" ], [ "BRAM_NE4C3_4", "CLBLM_NE4C3" ], [ "BRAM_NW2A0_4", "CLBLM_NW2A0" ], [ "BRAM_NW2A1_4", "CLBLM_NW2A1" ], [ "BRAM_NW2A2_4", "CLBLM_NW2A2" ], [ "BRAM_NW2A3_4", "CLBLM_NW2A3" ], [ "BRAM_NW4A0_4", "CLBLM_NW4A0" ], [ "BRAM_NW4A1_4", "CLBLM_NW4A1" ], [ "BRAM_NW4A2_4", "CLBLM_NW4A2" ], [ "BRAM_NW4A3_4", "CLBLM_NW4A3" ], [ "BRAM_NW4END0_4", "CLBLM_NW4END0" ], [ "BRAM_NW4END1_4", "CLBLM_NW4END1" ], [ "BRAM_NW4END2_4", "CLBLM_NW4END2" ], [ "BRAM_NW4END3_4", "CLBLM_NW4END3" ], [ "BRAM_SE2A0_4", "CLBLM_SE2A0" ], [ "BRAM_SE2A1_4", "CLBLM_SE2A1" ], [ "BRAM_SE2A2_4", "CLBLM_SE2A2" ], [ "BRAM_SE2A3_4", "CLBLM_SE2A3" ], [ "BRAM_SE4BEG0_4", "CLBLM_SE4BEG0" ], [ "BRAM_SE4BEG1_4", "CLBLM_SE4BEG1" ], [ "BRAM_SE4BEG2_4", "CLBLM_SE4BEG2" ], [ "BRAM_SE4BEG3_4", "CLBLM_SE4BEG3" ], [ "BRAM_SE4C0_4", "CLBLM_SE4C0" ], [ "BRAM_SE4C1_4", "CLBLM_SE4C1" ], [ "BRAM_SE4C2_4", "CLBLM_SE4C2" ], [ "BRAM_SE4C3_4", "CLBLM_SE4C3" ], [ "BRAM_SW2A0_4", "CLBLM_SW2A0" ], [ "BRAM_SW2A1_4", "CLBLM_SW2A1" ], [ "BRAM_SW2A2_4", "CLBLM_SW2A2" ], [ "BRAM_SW2A3_4", "CLBLM_SW2A3" ], [ "BRAM_SW4A0_4", "CLBLM_SW4A0" ], [ "BRAM_SW4A1_4", "CLBLM_SW4A1" ], [ "BRAM_SW4A2_4", "CLBLM_SW4A2" ], [ "BRAM_SW4A3_4", "CLBLM_SW4A3" ], [ "BRAM_SW4END0_4", "CLBLM_SW4END0" ], [ "BRAM_SW4END1_4", "CLBLM_SW4END1" ], [ "BRAM_SW4END2_4", "CLBLM_SW4END2" ], [ "BRAM_SW4END3_4", "CLBLM_SW4END3" ], [ "BRAM_WL1END0_4", "CLBLM_WL1END0" ], [ "BRAM_WL1END1_4", "CLBLM_WL1END1" ], [ "BRAM_WL1END2_4", "CLBLM_WL1END2" ], [ "BRAM_WL1END3_4", "CLBLM_WL1END3" ], [ "BRAM_WR1END0_4", "CLBLM_WR1END0" ], [ "BRAM_WR1END1_4", "CLBLM_WR1END1" ], [ "BRAM_WR1END2_4", "CLBLM_WR1END2" ], [ "BRAM_WR1END3_4", "CLBLM_WR1END3" ], [ "BRAM_WW2A0_4", "CLBLM_WW2A0" ], [ "BRAM_WW2A1_4", "CLBLM_WW2A1" ], [ "BRAM_WW2A2_4", "CLBLM_WW2A2" ], [ "BRAM_WW2A3_4", "CLBLM_WW2A3" ], [ "BRAM_WW2END0_4", "CLBLM_WW2END0" ], [ "BRAM_WW2END1_4", "CLBLM_WW2END1" ], [ "BRAM_WW2END2_4", "CLBLM_WW2END2" ], [ "BRAM_WW2END3_4", "CLBLM_WW2END3" ], [ "BRAM_WW4A0_4", "CLBLM_WW4A0" ], [ "BRAM_WW4A1_4", "CLBLM_WW4A1" ], [ "BRAM_WW4A2_4", "CLBLM_WW4A2" ], [ "BRAM_WW4A3_4", "CLBLM_WW4A3" ], [ "BRAM_WW4B0_4", "CLBLM_WW4B0" ], [ "BRAM_WW4B1_4", "CLBLM_WW4B1" ], [ "BRAM_WW4B2_4", "CLBLM_WW4B2" ], [ "BRAM_WW4B3_4", "CLBLM_WW4B3" ], [ "BRAM_WW4C0_4", "CLBLM_WW4C0" ], [ "BRAM_WW4C1_4", "CLBLM_WW4C1" ], [ "BRAM_WW4C2_4", "CLBLM_WW4C2" ], [ "BRAM_WW4C3_4", "CLBLM_WW4C3" ], [ "BRAM_WW4END0_4", "CLBLM_WW4END0" ], [ "BRAM_WW4END1_4", "CLBLM_WW4END1" ], [ "BRAM_WW4END2_4", "CLBLM_WW4END2" ], [ "BRAM_WW4END3_4", "CLBLM_WW4END3" ] ] }, { "grid_deltas": [ -1, -3 ], "tile_types": [ "BRAM_L", "CLBLM_R" ], "wire_pairs": [ [ "BRAM_EE2A0_3", "CLBLM_EE2A0" ], [ "BRAM_EE2A1_3", "CLBLM_EE2A1" ], [ "BRAM_EE2A2_3", "CLBLM_EE2A2" ], [ "BRAM_EE2A3_3", "CLBLM_EE2A3" ], [ "BRAM_EE2BEG0_3", "CLBLM_EE2BEG0" ], [ "BRAM_EE2BEG1_3", "CLBLM_EE2BEG1" ], [ "BRAM_EE2BEG2_3", "CLBLM_EE2BEG2" ], [ "BRAM_EE2BEG3_3", "CLBLM_EE2BEG3" ], [ "BRAM_EE4A0_3", "CLBLM_EE4A0" ], [ "BRAM_EE4A1_3", "CLBLM_EE4A1" ], [ "BRAM_EE4A2_3", "CLBLM_EE4A2" ], [ "BRAM_EE4A3_3", "CLBLM_EE4A3" ], [ "BRAM_EE4B0_3", "CLBLM_EE4B0" ], [ "BRAM_EE4B1_3", "CLBLM_EE4B1" ], [ "BRAM_EE4B2_3", "CLBLM_EE4B2" ], [ "BRAM_EE4B3_3", "CLBLM_EE4B3" ], [ "BRAM_EE4BEG0_3", "CLBLM_EE4BEG0" ], [ "BRAM_EE4BEG1_3", "CLBLM_EE4BEG1" ], [ "BRAM_EE4BEG2_3", "CLBLM_EE4BEG2" ], [ "BRAM_EE4BEG3_3", "CLBLM_EE4BEG3" ], [ "BRAM_EE4C0_3", "CLBLM_EE4C0" ], [ "BRAM_EE4C1_3", "CLBLM_EE4C1" ], [ "BRAM_EE4C2_3", "CLBLM_EE4C2" ], [ "BRAM_EE4C3_3", "CLBLM_EE4C3" ], [ "BRAM_EL1BEG0_3", "CLBLM_EL1BEG0" ], [ "BRAM_EL1BEG1_3", "CLBLM_EL1BEG1" ], [ "BRAM_EL1BEG2_3", "CLBLM_EL1BEG2" ], [ "BRAM_EL1BEG3_3", "CLBLM_EL1BEG3" ], [ "BRAM_ER1BEG0_3", "CLBLM_ER1BEG0" ], [ "BRAM_ER1BEG1_3", "CLBLM_ER1BEG1" ], [ "BRAM_ER1BEG2_3", "CLBLM_ER1BEG2" ], [ "BRAM_ER1BEG3_3", "CLBLM_ER1BEG3" ], [ "BRAM_LH1_3", "CLBLM_LH1" ], [ "BRAM_LH2_3", "CLBLM_LH2" ], [ "BRAM_LH3_3", "CLBLM_LH3" ], [ "BRAM_LH4_3", "CLBLM_LH4" ], [ "BRAM_LH5_3", "CLBLM_LH5" ], [ "BRAM_LH6_3", "CLBLM_LH6" ], [ "BRAM_LH7_3", "CLBLM_LH7" ], [ "BRAM_LH8_3", "CLBLM_LH8" ], [ "BRAM_LH9_3", "CLBLM_LH9" ], [ "BRAM_LH10_3", "CLBLM_LH10" ], [ "BRAM_LH11_3", "CLBLM_LH11" ], [ "BRAM_LH12_3", "CLBLM_LH12" ], [ "BRAM_MONITOR_N_3", "CLBLM_MONITOR_N" ], [ "BRAM_MONITOR_P_3", "CLBLM_MONITOR_P" ], [ "BRAM_NE2A0_3", "CLBLM_NE2A0" ], [ "BRAM_NE2A1_3", "CLBLM_NE2A1" ], [ "BRAM_NE2A2_3", "CLBLM_NE2A2" ], [ "BRAM_NE2A3_3", "CLBLM_NE2A3" ], [ "BRAM_NE4BEG0_3", "CLBLM_NE4BEG0" ], [ "BRAM_NE4BEG1_3", "CLBLM_NE4BEG1" ], [ "BRAM_NE4BEG2_3", "CLBLM_NE4BEG2" ], [ "BRAM_NE4BEG3_3", "CLBLM_NE4BEG3" ], [ "BRAM_NE4C0_3", "CLBLM_NE4C0" ], [ "BRAM_NE4C1_3", "CLBLM_NE4C1" ], [ "BRAM_NE4C2_3", "CLBLM_NE4C2" ], [ "BRAM_NE4C3_3", "CLBLM_NE4C3" ], [ "BRAM_NW2A0_3", "CLBLM_NW2A0" ], [ "BRAM_NW2A1_3", "CLBLM_NW2A1" ], [ "BRAM_NW2A2_3", "CLBLM_NW2A2" ], [ "BRAM_NW2A3_3", "CLBLM_NW2A3" ], [ "BRAM_NW4A0_3", "CLBLM_NW4A0" ], [ "BRAM_NW4A1_3", "CLBLM_NW4A1" ], [ "BRAM_NW4A2_3", "CLBLM_NW4A2" ], [ "BRAM_NW4A3_3", "CLBLM_NW4A3" ], [ "BRAM_NW4END0_3", "CLBLM_NW4END0" ], [ "BRAM_NW4END1_3", "CLBLM_NW4END1" ], [ "BRAM_NW4END2_3", "CLBLM_NW4END2" ], [ "BRAM_NW4END3_3", "CLBLM_NW4END3" ], [ "BRAM_SE2A0_3", "CLBLM_SE2A0" ], [ "BRAM_SE2A1_3", "CLBLM_SE2A1" ], [ "BRAM_SE2A2_3", "CLBLM_SE2A2" ], [ "BRAM_SE2A3_3", "CLBLM_SE2A3" ], [ "BRAM_SE4BEG0_3", "CLBLM_SE4BEG0" ], [ "BRAM_SE4BEG1_3", "CLBLM_SE4BEG1" ], [ "BRAM_SE4BEG2_3", "CLBLM_SE4BEG2" ], [ "BRAM_SE4BEG3_3", "CLBLM_SE4BEG3" ], [ "BRAM_SE4C0_3", "CLBLM_SE4C0" ], [ "BRAM_SE4C1_3", "CLBLM_SE4C1" ], [ "BRAM_SE4C2_3", "CLBLM_SE4C2" ], [ "BRAM_SE4C3_3", "CLBLM_SE4C3" ], [ "BRAM_SW2A0_3", "CLBLM_SW2A0" ], [ "BRAM_SW2A1_3", "CLBLM_SW2A1" ], [ "BRAM_SW2A2_3", "CLBLM_SW2A2" ], [ "BRAM_SW2A3_3", "CLBLM_SW2A3" ], [ "BRAM_SW4A0_3", "CLBLM_SW4A0" ], [ "BRAM_SW4A1_3", "CLBLM_SW4A1" ], [ "BRAM_SW4A2_3", "CLBLM_SW4A2" ], [ "BRAM_SW4A3_3", "CLBLM_SW4A3" ], [ "BRAM_SW4END0_3", "CLBLM_SW4END0" ], [ "BRAM_SW4END1_3", "CLBLM_SW4END1" ], [ "BRAM_SW4END2_3", "CLBLM_SW4END2" ], [ "BRAM_SW4END3_3", "CLBLM_SW4END3" ], [ "BRAM_WL1END0_3", "CLBLM_WL1END0" ], [ "BRAM_WL1END1_3", "CLBLM_WL1END1" ], [ "BRAM_WL1END2_3", "CLBLM_WL1END2" ], [ "BRAM_WL1END3_3", "CLBLM_WL1END3" ], [ "BRAM_WR1END0_3", "CLBLM_WR1END0" ], [ "BRAM_WR1END1_3", "CLBLM_WR1END1" ], [ "BRAM_WR1END2_3", "CLBLM_WR1END2" ], [ "BRAM_WR1END3_3", "CLBLM_WR1END3" ], [ "BRAM_WW2A0_3", "CLBLM_WW2A0" ], [ "BRAM_WW2A1_3", "CLBLM_WW2A1" ], [ "BRAM_WW2A2_3", "CLBLM_WW2A2" ], [ "BRAM_WW2A3_3", "CLBLM_WW2A3" ], [ "BRAM_WW2END0_3", "CLBLM_WW2END0" ], [ "BRAM_WW2END1_3", "CLBLM_WW2END1" ], [ "BRAM_WW2END2_3", "CLBLM_WW2END2" ], [ "BRAM_WW2END3_3", "CLBLM_WW2END3" ], [ "BRAM_WW4A0_3", "CLBLM_WW4A0" ], [ "BRAM_WW4A1_3", "CLBLM_WW4A1" ], [ "BRAM_WW4A2_3", "CLBLM_WW4A2" ], [ "BRAM_WW4A3_3", "CLBLM_WW4A3" ], [ "BRAM_WW4B0_3", "CLBLM_WW4B0" ], [ "BRAM_WW4B1_3", "CLBLM_WW4B1" ], [ "BRAM_WW4B2_3", "CLBLM_WW4B2" ], [ "BRAM_WW4B3_3", "CLBLM_WW4B3" ], [ "BRAM_WW4C0_3", "CLBLM_WW4C0" ], [ "BRAM_WW4C1_3", "CLBLM_WW4C1" ], [ "BRAM_WW4C2_3", "CLBLM_WW4C2" ], [ "BRAM_WW4C3_3", "CLBLM_WW4C3" ], [ "BRAM_WW4END0_3", "CLBLM_WW4END0" ], [ "BRAM_WW4END1_3", "CLBLM_WW4END1" ], [ "BRAM_WW4END2_3", "CLBLM_WW4END2" ], [ "BRAM_WW4END3_3", "CLBLM_WW4END3" ] ] }, { "grid_deltas": [ -1, -2 ], "tile_types": [ "BRAM_L", "CLBLM_R" ], "wire_pairs": [ [ "BRAM_EE2A0_2", "CLBLM_EE2A0" ], [ "BRAM_EE2A1_2", "CLBLM_EE2A1" ], [ "BRAM_EE2A2_2", "CLBLM_EE2A2" ], [ "BRAM_EE2A3_2", "CLBLM_EE2A3" ], [ "BRAM_EE2BEG0_2", "CLBLM_EE2BEG0" ], [ "BRAM_EE2BEG1_2", "CLBLM_EE2BEG1" ], [ "BRAM_EE2BEG2_2", "CLBLM_EE2BEG2" ], [ "BRAM_EE2BEG3_2", "CLBLM_EE2BEG3" ], [ "BRAM_EE4A0_2", "CLBLM_EE4A0" ], [ "BRAM_EE4A1_2", "CLBLM_EE4A1" ], [ "BRAM_EE4A2_2", "CLBLM_EE4A2" ], [ "BRAM_EE4A3_2", "CLBLM_EE4A3" ], [ "BRAM_EE4B0_2", "CLBLM_EE4B0" ], [ "BRAM_EE4B1_2", "CLBLM_EE4B1" ], [ "BRAM_EE4B2_2", "CLBLM_EE4B2" ], [ "BRAM_EE4B3_2", "CLBLM_EE4B3" ], [ "BRAM_EE4BEG0_2", "CLBLM_EE4BEG0" ], [ "BRAM_EE4BEG1_2", "CLBLM_EE4BEG1" ], [ "BRAM_EE4BEG2_2", "CLBLM_EE4BEG2" ], [ "BRAM_EE4BEG3_2", "CLBLM_EE4BEG3" ], [ "BRAM_EE4C0_2", "CLBLM_EE4C0" ], [ "BRAM_EE4C1_2", "CLBLM_EE4C1" ], [ "BRAM_EE4C2_2", "CLBLM_EE4C2" ], [ "BRAM_EE4C3_2", "CLBLM_EE4C3" ], [ "BRAM_EL1BEG0_2", "CLBLM_EL1BEG0" ], [ "BRAM_EL1BEG1_2", "CLBLM_EL1BEG1" ], [ "BRAM_EL1BEG2_2", "CLBLM_EL1BEG2" ], [ "BRAM_EL1BEG3_2", "CLBLM_EL1BEG3" ], [ "BRAM_ER1BEG0_2", "CLBLM_ER1BEG0" ], [ "BRAM_ER1BEG1_2", "CLBLM_ER1BEG1" ], [ "BRAM_ER1BEG2_2", "CLBLM_ER1BEG2" ], [ "BRAM_ER1BEG3_2", "CLBLM_ER1BEG3" ], [ "BRAM_LH1_2", "CLBLM_LH1" ], [ "BRAM_LH2_2", "CLBLM_LH2" ], [ "BRAM_LH3_2", "CLBLM_LH3" ], [ "BRAM_LH4_2", "CLBLM_LH4" ], [ "BRAM_LH5_2", "CLBLM_LH5" ], [ "BRAM_LH6_2", "CLBLM_LH6" ], [ "BRAM_LH7_2", "CLBLM_LH7" ], [ "BRAM_LH8_2", "CLBLM_LH8" ], [ "BRAM_LH9_2", "CLBLM_LH9" ], [ "BRAM_LH10_2", "CLBLM_LH10" ], [ "BRAM_LH11_2", "CLBLM_LH11" ], [ "BRAM_LH12_2", "CLBLM_LH12" ], [ "BRAM_MONITOR_N_2", "CLBLM_MONITOR_N" ], [ "BRAM_MONITOR_P_2", "CLBLM_MONITOR_P" ], [ "BRAM_NE2A0_2", "CLBLM_NE2A0" ], [ "BRAM_NE2A1_2", "CLBLM_NE2A1" ], [ "BRAM_NE2A2_2", "CLBLM_NE2A2" ], [ "BRAM_NE2A3_2", "CLBLM_NE2A3" ], [ "BRAM_NE4BEG0_2", "CLBLM_NE4BEG0" ], [ "BRAM_NE4BEG1_2", "CLBLM_NE4BEG1" ], [ "BRAM_NE4BEG2_2", "CLBLM_NE4BEG2" ], [ "BRAM_NE4BEG3_2", "CLBLM_NE4BEG3" ], [ "BRAM_NE4C0_2", "CLBLM_NE4C0" ], [ "BRAM_NE4C1_2", "CLBLM_NE4C1" ], [ "BRAM_NE4C2_2", "CLBLM_NE4C2" ], [ "BRAM_NE4C3_2", "CLBLM_NE4C3" ], [ "BRAM_NW2A0_2", "CLBLM_NW2A0" ], [ "BRAM_NW2A1_2", "CLBLM_NW2A1" ], [ "BRAM_NW2A2_2", "CLBLM_NW2A2" ], [ "BRAM_NW2A3_2", "CLBLM_NW2A3" ], [ "BRAM_NW4A0_2", "CLBLM_NW4A0" ], [ "BRAM_NW4A1_2", "CLBLM_NW4A1" ], [ "BRAM_NW4A2_2", "CLBLM_NW4A2" ], [ "BRAM_NW4A3_2", "CLBLM_NW4A3" ], [ "BRAM_NW4END0_2", "CLBLM_NW4END0" ], [ "BRAM_NW4END1_2", "CLBLM_NW4END1" ], [ "BRAM_NW4END2_2", "CLBLM_NW4END2" ], [ "BRAM_NW4END3_2", "CLBLM_NW4END3" ], [ "BRAM_SE2A0_2", "CLBLM_SE2A0" ], [ "BRAM_SE2A1_2", "CLBLM_SE2A1" ], [ "BRAM_SE2A2_2", "CLBLM_SE2A2" ], [ "BRAM_SE2A3_2", "CLBLM_SE2A3" ], [ "BRAM_SE4BEG0_2", "CLBLM_SE4BEG0" ], [ "BRAM_SE4BEG1_2", "CLBLM_SE4BEG1" ], [ "BRAM_SE4BEG2_2", "CLBLM_SE4BEG2" ], [ "BRAM_SE4BEG3_2", "CLBLM_SE4BEG3" ], [ "BRAM_SE4C0_2", "CLBLM_SE4C0" ], [ "BRAM_SE4C1_2", "CLBLM_SE4C1" ], [ "BRAM_SE4C2_2", "CLBLM_SE4C2" ], [ "BRAM_SE4C3_2", "CLBLM_SE4C3" ], [ "BRAM_SW2A0_2", "CLBLM_SW2A0" ], [ "BRAM_SW2A1_2", "CLBLM_SW2A1" ], [ "BRAM_SW2A2_2", "CLBLM_SW2A2" ], [ "BRAM_SW2A3_2", "CLBLM_SW2A3" ], [ "BRAM_SW4A0_2", "CLBLM_SW4A0" ], [ "BRAM_SW4A1_2", "CLBLM_SW4A1" ], [ "BRAM_SW4A2_2", "CLBLM_SW4A2" ], [ "BRAM_SW4A3_2", "CLBLM_SW4A3" ], [ "BRAM_SW4END0_2", "CLBLM_SW4END0" ], [ "BRAM_SW4END1_2", "CLBLM_SW4END1" ], [ "BRAM_SW4END2_2", "CLBLM_SW4END2" ], [ "BRAM_SW4END3_2", "CLBLM_SW4END3" ], [ "BRAM_WL1END0_2", "CLBLM_WL1END0" ], [ "BRAM_WL1END1_2", "CLBLM_WL1END1" ], [ "BRAM_WL1END2_2", "CLBLM_WL1END2" ], [ "BRAM_WL1END3_2", "CLBLM_WL1END3" ], [ "BRAM_WR1END0_2", "CLBLM_WR1END0" ], [ "BRAM_WR1END1_2", "CLBLM_WR1END1" ], [ "BRAM_WR1END2_2", "CLBLM_WR1END2" ], [ "BRAM_WR1END3_2", "CLBLM_WR1END3" ], [ "BRAM_WW2A0_2", "CLBLM_WW2A0" ], [ "BRAM_WW2A1_2", "CLBLM_WW2A1" ], [ "BRAM_WW2A2_2", "CLBLM_WW2A2" ], [ "BRAM_WW2A3_2", "CLBLM_WW2A3" ], [ "BRAM_WW2END0_2", "CLBLM_WW2END0" ], [ "BRAM_WW2END1_2", "CLBLM_WW2END1" ], [ "BRAM_WW2END2_2", "CLBLM_WW2END2" ], [ "BRAM_WW2END3_2", "CLBLM_WW2END3" ], [ "BRAM_WW4A0_2", "CLBLM_WW4A0" ], [ "BRAM_WW4A1_2", "CLBLM_WW4A1" ], [ "BRAM_WW4A2_2", "CLBLM_WW4A2" ], [ "BRAM_WW4A3_2", "CLBLM_WW4A3" ], [ "BRAM_WW4B0_2", "CLBLM_WW4B0" ], [ "BRAM_WW4B1_2", "CLBLM_WW4B1" ], [ "BRAM_WW4B2_2", "CLBLM_WW4B2" ], [ "BRAM_WW4B3_2", "CLBLM_WW4B3" ], [ "BRAM_WW4C0_2", "CLBLM_WW4C0" ], [ "BRAM_WW4C1_2", "CLBLM_WW4C1" ], [ "BRAM_WW4C2_2", "CLBLM_WW4C2" ], [ "BRAM_WW4C3_2", "CLBLM_WW4C3" ], [ "BRAM_WW4END0_2", "CLBLM_WW4END0" ], [ "BRAM_WW4END1_2", "CLBLM_WW4END1" ], [ "BRAM_WW4END2_2", "CLBLM_WW4END2" ], [ "BRAM_WW4END3_2", "CLBLM_WW4END3" ] ] }, { "grid_deltas": [ -1, -1 ], "tile_types": [ "BRAM_L", "CLBLM_R" ], "wire_pairs": [ [ "BRAM_EE2A0_1", "CLBLM_EE2A0" ], [ "BRAM_EE2A1_1", "CLBLM_EE2A1" ], [ "BRAM_EE2A2_1", "CLBLM_EE2A2" ], [ "BRAM_EE2A3_1", "CLBLM_EE2A3" ], [ "BRAM_EE2BEG0_1", "CLBLM_EE2BEG0" ], [ "BRAM_EE2BEG1_1", "CLBLM_EE2BEG1" ], [ "BRAM_EE2BEG2_1", "CLBLM_EE2BEG2" ], [ "BRAM_EE2BEG3_1", "CLBLM_EE2BEG3" ], [ "BRAM_EE4A0_1", "CLBLM_EE4A0" ], [ "BRAM_EE4A1_1", "CLBLM_EE4A1" ], [ "BRAM_EE4A2_1", "CLBLM_EE4A2" ], [ "BRAM_EE4A3_1", "CLBLM_EE4A3" ], [ "BRAM_EE4B0_1", "CLBLM_EE4B0" ], [ "BRAM_EE4B1_1", "CLBLM_EE4B1" ], [ "BRAM_EE4B2_1", "CLBLM_EE4B2" ], [ "BRAM_EE4B3_1", "CLBLM_EE4B3" ], [ "BRAM_EE4BEG0_1", "CLBLM_EE4BEG0" ], [ "BRAM_EE4BEG1_1", "CLBLM_EE4BEG1" ], [ "BRAM_EE4BEG2_1", "CLBLM_EE4BEG2" ], [ "BRAM_EE4BEG3_1", "CLBLM_EE4BEG3" ], [ "BRAM_EE4C0_1", "CLBLM_EE4C0" ], [ "BRAM_EE4C1_1", "CLBLM_EE4C1" ], [ "BRAM_EE4C2_1", "CLBLM_EE4C2" ], [ "BRAM_EE4C3_1", "CLBLM_EE4C3" ], [ "BRAM_EL1BEG0_1", "CLBLM_EL1BEG0" ], [ "BRAM_EL1BEG1_1", "CLBLM_EL1BEG1" ], [ "BRAM_EL1BEG2_1", "CLBLM_EL1BEG2" ], [ "BRAM_EL1BEG3_1", "CLBLM_EL1BEG3" ], [ "BRAM_ER1BEG0_1", "CLBLM_ER1BEG0" ], [ "BRAM_ER1BEG1_1", "CLBLM_ER1BEG1" ], [ "BRAM_ER1BEG2_1", "CLBLM_ER1BEG2" ], [ "BRAM_ER1BEG3_1", "CLBLM_ER1BEG3" ], [ "BRAM_LH1_1", "CLBLM_LH1" ], [ "BRAM_LH2_1", "CLBLM_LH2" ], [ "BRAM_LH3_1", "CLBLM_LH3" ], [ "BRAM_LH4_1", "CLBLM_LH4" ], [ "BRAM_LH5_1", "CLBLM_LH5" ], [ "BRAM_LH6_1", "CLBLM_LH6" ], [ "BRAM_LH7_1", "CLBLM_LH7" ], [ "BRAM_LH8_1", "CLBLM_LH8" ], [ "BRAM_LH9_1", "CLBLM_LH9" ], [ "BRAM_LH10_1", "CLBLM_LH10" ], [ "BRAM_LH11_1", "CLBLM_LH11" ], [ "BRAM_LH12_1", "CLBLM_LH12" ], [ "BRAM_MONITOR_N_1", "CLBLM_MONITOR_N" ], [ "BRAM_MONITOR_P_1", "CLBLM_MONITOR_P" ], [ "BRAM_NE2A0_1", "CLBLM_NE2A0" ], [ "BRAM_NE2A1_1", "CLBLM_NE2A1" ], [ "BRAM_NE2A2_1", "CLBLM_NE2A2" ], [ "BRAM_NE2A3_1", "CLBLM_NE2A3" ], [ "BRAM_NE4BEG0_1", "CLBLM_NE4BEG0" ], [ "BRAM_NE4BEG1_1", "CLBLM_NE4BEG1" ], [ "BRAM_NE4BEG2_1", "CLBLM_NE4BEG2" ], [ "BRAM_NE4BEG3_1", "CLBLM_NE4BEG3" ], [ "BRAM_NE4C0_1", "CLBLM_NE4C0" ], [ "BRAM_NE4C1_1", "CLBLM_NE4C1" ], [ "BRAM_NE4C2_1", "CLBLM_NE4C2" ], [ "BRAM_NE4C3_1", "CLBLM_NE4C3" ], [ "BRAM_NW2A0_1", "CLBLM_NW2A0" ], [ "BRAM_NW2A1_1", "CLBLM_NW2A1" ], [ "BRAM_NW2A2_1", "CLBLM_NW2A2" ], [ "BRAM_NW2A3_1", "CLBLM_NW2A3" ], [ "BRAM_NW4A0_1", "CLBLM_NW4A0" ], [ "BRAM_NW4A1_1", "CLBLM_NW4A1" ], [ "BRAM_NW4A2_1", "CLBLM_NW4A2" ], [ "BRAM_NW4A3_1", "CLBLM_NW4A3" ], [ "BRAM_NW4END0_1", "CLBLM_NW4END0" ], [ "BRAM_NW4END1_1", "CLBLM_NW4END1" ], [ "BRAM_NW4END2_1", "CLBLM_NW4END2" ], [ "BRAM_NW4END3_1", "CLBLM_NW4END3" ], [ "BRAM_SE2A0_1", "CLBLM_SE2A0" ], [ "BRAM_SE2A1_1", "CLBLM_SE2A1" ], [ "BRAM_SE2A2_1", "CLBLM_SE2A2" ], [ "BRAM_SE2A3_1", "CLBLM_SE2A3" ], [ "BRAM_SE4BEG0_1", "CLBLM_SE4BEG0" ], [ "BRAM_SE4BEG1_1", "CLBLM_SE4BEG1" ], [ "BRAM_SE4BEG2_1", "CLBLM_SE4BEG2" ], [ "BRAM_SE4BEG3_1", "CLBLM_SE4BEG3" ], [ "BRAM_SE4C0_1", "CLBLM_SE4C0" ], [ "BRAM_SE4C1_1", "CLBLM_SE4C1" ], [ "BRAM_SE4C2_1", "CLBLM_SE4C2" ], [ "BRAM_SE4C3_1", "CLBLM_SE4C3" ], [ "BRAM_SW2A0_1", "CLBLM_SW2A0" ], [ "BRAM_SW2A1_1", "CLBLM_SW2A1" ], [ "BRAM_SW2A2_1", "CLBLM_SW2A2" ], [ "BRAM_SW2A3_1", "CLBLM_SW2A3" ], [ "BRAM_SW4A0_1", "CLBLM_SW4A0" ], [ "BRAM_SW4A1_1", "CLBLM_SW4A1" ], [ "BRAM_SW4A2_1", "CLBLM_SW4A2" ], [ "BRAM_SW4A3_1", "CLBLM_SW4A3" ], [ "BRAM_SW4END0_1", "CLBLM_SW4END0" ], [ "BRAM_SW4END1_1", "CLBLM_SW4END1" ], [ "BRAM_SW4END2_1", "CLBLM_SW4END2" ], [ "BRAM_SW4END3_1", "CLBLM_SW4END3" ], [ "BRAM_WL1END0_1", "CLBLM_WL1END0" ], [ "BRAM_WL1END1_1", "CLBLM_WL1END1" ], [ "BRAM_WL1END2_1", "CLBLM_WL1END2" ], [ "BRAM_WL1END3_1", "CLBLM_WL1END3" ], [ "BRAM_WR1END0_1", "CLBLM_WR1END0" ], [ "BRAM_WR1END1_1", "CLBLM_WR1END1" ], [ "BRAM_WR1END2_1", "CLBLM_WR1END2" ], [ "BRAM_WR1END3_1", "CLBLM_WR1END3" ], [ "BRAM_WW2A0_1", "CLBLM_WW2A0" ], [ "BRAM_WW2A1_1", "CLBLM_WW2A1" ], [ "BRAM_WW2A2_1", "CLBLM_WW2A2" ], [ "BRAM_WW2A3_1", "CLBLM_WW2A3" ], [ "BRAM_WW2END0_1", "CLBLM_WW2END0" ], [ "BRAM_WW2END1_1", "CLBLM_WW2END1" ], [ "BRAM_WW2END2_1", "CLBLM_WW2END2" ], [ "BRAM_WW2END3_1", "CLBLM_WW2END3" ], [ "BRAM_WW4A0_1", "CLBLM_WW4A0" ], [ "BRAM_WW4A1_1", "CLBLM_WW4A1" ], [ "BRAM_WW4A2_1", "CLBLM_WW4A2" ], [ "BRAM_WW4A3_1", "CLBLM_WW4A3" ], [ "BRAM_WW4B0_1", "CLBLM_WW4B0" ], [ "BRAM_WW4B1_1", "CLBLM_WW4B1" ], [ "BRAM_WW4B2_1", "CLBLM_WW4B2" ], [ "BRAM_WW4B3_1", "CLBLM_WW4B3" ], [ "BRAM_WW4C0_1", "CLBLM_WW4C0" ], [ "BRAM_WW4C1_1", "CLBLM_WW4C1" ], [ "BRAM_WW4C2_1", "CLBLM_WW4C2" ], [ "BRAM_WW4C3_1", "CLBLM_WW4C3" ], [ "BRAM_WW4END0_1", "CLBLM_WW4END0" ], [ "BRAM_WW4END1_1", "CLBLM_WW4END1" ], [ "BRAM_WW4END2_1", "CLBLM_WW4END2" ], [ "BRAM_WW4END3_1", "CLBLM_WW4END3" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "BRAM_L", "CLBLM_R" ], "wire_pairs": [ [ "BRAM_EE2A0_0", "CLBLM_EE2A0" ], [ "BRAM_EE2A1_0", "CLBLM_EE2A1" ], [ "BRAM_EE2A2_0", "CLBLM_EE2A2" ], [ "BRAM_EE2A3_0", "CLBLM_EE2A3" ], [ "BRAM_EE2BEG0_0", "CLBLM_EE2BEG0" ], [ "BRAM_EE2BEG1_0", "CLBLM_EE2BEG1" ], [ "BRAM_EE2BEG2_0", "CLBLM_EE2BEG2" ], [ "BRAM_EE2BEG3_0", "CLBLM_EE2BEG3" ], [ "BRAM_EE4A0_0", "CLBLM_EE4A0" ], [ "BRAM_EE4A1_0", "CLBLM_EE4A1" ], [ "BRAM_EE4A2_0", "CLBLM_EE4A2" ], [ "BRAM_EE4A3_0", "CLBLM_EE4A3" ], [ "BRAM_EE4B0_0", "CLBLM_EE4B0" ], [ "BRAM_EE4B1_0", "CLBLM_EE4B1" ], [ "BRAM_EE4B2_0", "CLBLM_EE4B2" ], [ "BRAM_EE4B3_0", "CLBLM_EE4B3" ], [ "BRAM_EE4BEG0_0", "CLBLM_EE4BEG0" ], [ "BRAM_EE4BEG1_0", "CLBLM_EE4BEG1" ], [ "BRAM_EE4BEG2_0", "CLBLM_EE4BEG2" ], [ "BRAM_EE4BEG3_0", "CLBLM_EE4BEG3" ], [ "BRAM_EE4C0_0", "CLBLM_EE4C0" ], [ "BRAM_EE4C1_0", "CLBLM_EE4C1" ], [ "BRAM_EE4C2_0", "CLBLM_EE4C2" ], [ "BRAM_EE4C3_0", "CLBLM_EE4C3" ], [ "BRAM_EL1BEG0_0", "CLBLM_EL1BEG0" ], [ "BRAM_EL1BEG1_0", "CLBLM_EL1BEG1" ], [ "BRAM_EL1BEG2_0", "CLBLM_EL1BEG2" ], [ "BRAM_EL1BEG3_0", "CLBLM_EL1BEG3" ], [ "BRAM_ER1BEG0_0", "CLBLM_ER1BEG0" ], [ "BRAM_ER1BEG1_0", "CLBLM_ER1BEG1" ], [ "BRAM_ER1BEG2_0", "CLBLM_ER1BEG2" ], [ "BRAM_ER1BEG3_0", "CLBLM_ER1BEG3" ], [ "BRAM_LH1_0", "CLBLM_LH1" ], [ "BRAM_LH2_0", "CLBLM_LH2" ], [ "BRAM_LH3_0", "CLBLM_LH3" ], [ "BRAM_LH4_0", "CLBLM_LH4" ], [ "BRAM_LH5_0", "CLBLM_LH5" ], [ "BRAM_LH6_0", "CLBLM_LH6" ], [ "BRAM_LH7_0", "CLBLM_LH7" ], [ "BRAM_LH8_0", "CLBLM_LH8" ], [ "BRAM_LH9_0", "CLBLM_LH9" ], [ "BRAM_LH10_0", "CLBLM_LH10" ], [ "BRAM_LH11_0", "CLBLM_LH11" ], [ "BRAM_LH12_0", "CLBLM_LH12" ], [ "BRAM_MONITOR_N_0", "CLBLM_MONITOR_N" ], [ "BRAM_MONITOR_P_0", "CLBLM_MONITOR_P" ], [ "BRAM_NE2A0_0", "CLBLM_NE2A0" ], [ "BRAM_NE2A1_0", "CLBLM_NE2A1" ], [ "BRAM_NE2A2_0", "CLBLM_NE2A2" ], [ "BRAM_NE2A3_0", "CLBLM_NE2A3" ], [ "BRAM_NE4BEG0_0", "CLBLM_NE4BEG0" ], [ "BRAM_NE4BEG1_0", "CLBLM_NE4BEG1" ], [ "BRAM_NE4BEG2_0", "CLBLM_NE4BEG2" ], [ "BRAM_NE4BEG3_0", "CLBLM_NE4BEG3" ], [ "BRAM_NE4C0_0", "CLBLM_NE4C0" ], [ "BRAM_NE4C1_0", "CLBLM_NE4C1" ], [ "BRAM_NE4C2_0", "CLBLM_NE4C2" ], [ "BRAM_NE4C3_0", "CLBLM_NE4C3" ], [ "BRAM_NW2A0_0", "CLBLM_NW2A0" ], [ "BRAM_NW2A1_0", "CLBLM_NW2A1" ], [ "BRAM_NW2A2_0", "CLBLM_NW2A2" ], [ "BRAM_NW2A3_0", "CLBLM_NW2A3" ], [ "BRAM_NW4A0_0", "CLBLM_NW4A0" ], [ "BRAM_NW4A1_0", "CLBLM_NW4A1" ], [ "BRAM_NW4A2_0", "CLBLM_NW4A2" ], [ "BRAM_NW4A3_0", "CLBLM_NW4A3" ], [ "BRAM_NW4END0_0", "CLBLM_NW4END0" ], [ "BRAM_NW4END1_0", "CLBLM_NW4END1" ], [ "BRAM_NW4END2_0", "CLBLM_NW4END2" ], [ "BRAM_NW4END3_0", "CLBLM_NW4END3" ], [ "BRAM_SE2A0_0", "CLBLM_SE2A0" ], [ "BRAM_SE2A1_0", "CLBLM_SE2A1" ], [ "BRAM_SE2A2_0", "CLBLM_SE2A2" ], [ "BRAM_SE2A3_0", "CLBLM_SE2A3" ], [ "BRAM_SE4BEG0_0", "CLBLM_SE4BEG0" ], [ "BRAM_SE4BEG1_0", "CLBLM_SE4BEG1" ], [ "BRAM_SE4BEG2_0", "CLBLM_SE4BEG2" ], [ "BRAM_SE4BEG3_0", "CLBLM_SE4BEG3" ], [ "BRAM_SE4C0_0", "CLBLM_SE4C0" ], [ "BRAM_SE4C1_0", "CLBLM_SE4C1" ], [ "BRAM_SE4C2_0", "CLBLM_SE4C2" ], [ "BRAM_SE4C3_0", "CLBLM_SE4C3" ], [ "BRAM_SW2A0_0", "CLBLM_SW2A0" ], [ "BRAM_SW2A1_0", "CLBLM_SW2A1" ], [ "BRAM_SW2A2_0", "CLBLM_SW2A2" ], [ "BRAM_SW2A3_0", "CLBLM_SW2A3" ], [ "BRAM_SW4A0_0", "CLBLM_SW4A0" ], [ "BRAM_SW4A1_0", "CLBLM_SW4A1" ], [ "BRAM_SW4A2_0", "CLBLM_SW4A2" ], [ "BRAM_SW4A3_0", "CLBLM_SW4A3" ], [ "BRAM_SW4END0_0", "CLBLM_SW4END0" ], [ "BRAM_SW4END1_0", "CLBLM_SW4END1" ], [ "BRAM_SW4END2_0", "CLBLM_SW4END2" ], [ "BRAM_SW4END3_0", "CLBLM_SW4END3" ], [ "BRAM_WL1END0_0", "CLBLM_WL1END0" ], [ "BRAM_WL1END1_0", "CLBLM_WL1END1" ], [ "BRAM_WL1END2_0", "CLBLM_WL1END2" ], [ "BRAM_WL1END3_0", "CLBLM_WL1END3" ], [ "BRAM_WR1END0_0", "CLBLM_WR1END0" ], [ "BRAM_WR1END1_0", "CLBLM_WR1END1" ], [ "BRAM_WR1END2_0", "CLBLM_WR1END2" ], [ "BRAM_WR1END3_0", "CLBLM_WR1END3" ], [ "BRAM_WW2A0_0", "CLBLM_WW2A0" ], [ "BRAM_WW2A1_0", "CLBLM_WW2A1" ], [ "BRAM_WW2A2_0", "CLBLM_WW2A2" ], [ "BRAM_WW2A3_0", "CLBLM_WW2A3" ], [ "BRAM_WW2END0_0", "CLBLM_WW2END0" ], [ "BRAM_WW2END1_0", "CLBLM_WW2END1" ], [ "BRAM_WW2END2_0", "CLBLM_WW2END2" ], [ "BRAM_WW2END3_0", "CLBLM_WW2END3" ], [ "BRAM_WW4A0_0", "CLBLM_WW4A0" ], [ "BRAM_WW4A1_0", "CLBLM_WW4A1" ], [ "BRAM_WW4A2_0", "CLBLM_WW4A2" ], [ "BRAM_WW4A3_0", "CLBLM_WW4A3" ], [ "BRAM_WW4B0_0", "CLBLM_WW4B0" ], [ "BRAM_WW4B1_0", "CLBLM_WW4B1" ], [ "BRAM_WW4B2_0", "CLBLM_WW4B2" ], [ "BRAM_WW4B3_0", "CLBLM_WW4B3" ], [ "BRAM_WW4C0_0", "CLBLM_WW4C0" ], [ "BRAM_WW4C1_0", "CLBLM_WW4C1" ], [ "BRAM_WW4C2_0", "CLBLM_WW4C2" ], [ "BRAM_WW4C3_0", "CLBLM_WW4C3" ], [ "BRAM_WW4END0_0", "CLBLM_WW4END0" ], [ "BRAM_WW4END1_0", "CLBLM_WW4END1" ], [ "BRAM_WW4END2_0", "CLBLM_WW4END2" ], [ "BRAM_WW4END3_0", "CLBLM_WW4END3" ] ] }, { "grid_deltas": [ 0, -5 ], "tile_types": [ "BRAM_L", "HCLK_BRAM" ], "wire_pairs": [ [ "BRAM_CASCINTOP_ADDRARDADDRU0", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" ], [ "BRAM_CASCINTOP_ADDRARDADDRU1", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" ], [ "BRAM_CASCINTOP_ADDRARDADDRU2", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" ], [ "BRAM_CASCINTOP_ADDRARDADDRU3", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" ], [ "BRAM_CASCINTOP_ADDRARDADDRU4", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" ], [ "BRAM_CASCINTOP_ADDRARDADDRU5", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" ], [ "BRAM_CASCINTOP_ADDRARDADDRU6", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" ], [ "BRAM_CASCINTOP_ADDRARDADDRU7", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" ], [ "BRAM_CASCINTOP_ADDRARDADDRU8", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" ], [ "BRAM_CASCINTOP_ADDRARDADDRU9", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" ], [ "BRAM_CASCINTOP_ADDRARDADDRU10", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" ], [ "BRAM_CASCINTOP_ADDRARDADDRU11", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" ], [ "BRAM_CASCINTOP_ADDRARDADDRU12", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" ], [ "BRAM_CASCINTOP_ADDRARDADDRU13", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" ], [ "BRAM_CASCINTOP_ADDRARDADDRU14", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU0", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU1", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU2", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU3", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU4", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU5", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU6", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU7", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU8", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU9", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU10", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU11", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU12", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU13", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU14", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ "BRAM_CASCOUT_ADDRARDADDRU0", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ "BRAM_CASCOUT_ADDRARDADDRU1", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" ], [ "BRAM_CASCOUT_ADDRARDADDRU2", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" ], [ "BRAM_CASCOUT_ADDRARDADDRU3", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" ], [ "BRAM_CASCOUT_ADDRARDADDRU4", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" ], [ "BRAM_CASCOUT_ADDRARDADDRU5", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" ], [ "BRAM_CASCOUT_ADDRARDADDRU6", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" ], [ "BRAM_CASCOUT_ADDRARDADDRU7", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" ], [ "BRAM_CASCOUT_ADDRARDADDRU8", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" ], [ "BRAM_CASCOUT_ADDRARDADDRU9", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" ], [ "BRAM_CASCOUT_ADDRARDADDRU10", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" ], [ "BRAM_CASCOUT_ADDRARDADDRU11", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" ], [ "BRAM_CASCOUT_ADDRARDADDRU12", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" ], [ "BRAM_CASCOUT_ADDRARDADDRU13", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" ], [ "BRAM_CASCOUT_ADDRARDADDRU14", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" ], [ "BRAM_CASCOUT_ADDRBWRADDRU0", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" ], [ "BRAM_CASCOUT_ADDRBWRADDRU1", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" ], [ "BRAM_CASCOUT_ADDRBWRADDRU2", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" ], [ "BRAM_CASCOUT_ADDRBWRADDRU3", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" ], [ "BRAM_CASCOUT_ADDRBWRADDRU4", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" ], [ "BRAM_CASCOUT_ADDRBWRADDRU5", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" ], [ "BRAM_CASCOUT_ADDRBWRADDRU6", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" ], [ "BRAM_CASCOUT_ADDRBWRADDRU7", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" ], [ "BRAM_CASCOUT_ADDRBWRADDRU8", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" ], [ "BRAM_CASCOUT_ADDRBWRADDRU9", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" ], [ "BRAM_CASCOUT_ADDRBWRADDRU10", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" ], [ "BRAM_CASCOUT_ADDRBWRADDRU11", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" ], [ "BRAM_CASCOUT_ADDRBWRADDRU12", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" ], [ "BRAM_CASCOUT_ADDRBWRADDRU13", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" ], [ "BRAM_CASCOUT_ADDRBWRADDRU14", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" ], [ "BRAM_FIFO36_CASCADEOUTA_1", "HCLK_BRAM_CASCADEA_L" ], [ "BRAM_FIFO36_CASCADEOUTB_1", "HCLK_BRAM_CASCADEB_L" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "BRAM_L", "HCLK_BRAM" ], "wire_pairs": [ [ "BRAM_CASCINBOT_ADDRARDADDRU0", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ "BRAM_CASCINBOT_ADDRARDADDRU1", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" ], [ "BRAM_CASCINBOT_ADDRARDADDRU2", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" ], [ "BRAM_CASCINBOT_ADDRARDADDRU3", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" ], [ "BRAM_CASCINBOT_ADDRARDADDRU4", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" ], [ "BRAM_CASCINBOT_ADDRARDADDRU5", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" ], [ "BRAM_CASCINBOT_ADDRARDADDRU6", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" ], [ "BRAM_CASCINBOT_ADDRARDADDRU7", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" ], [ "BRAM_CASCINBOT_ADDRARDADDRU8", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" ], [ "BRAM_CASCINBOT_ADDRARDADDRU9", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" ], [ "BRAM_CASCINBOT_ADDRARDADDRU10", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" ], [ "BRAM_CASCINBOT_ADDRARDADDRU11", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" ], [ "BRAM_CASCINBOT_ADDRARDADDRU12", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" ], [ "BRAM_CASCINBOT_ADDRARDADDRU13", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" ], [ "BRAM_CASCINBOT_ADDRARDADDRU14", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU0", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU1", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU2", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU3", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU4", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU5", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU6", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU7", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU8", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU9", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU10", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU11", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU12", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU13", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU14", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" ], [ "BRAM_CASCOUT_ADDRARDADDRU0", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" ], [ "BRAM_CASCOUT_ADDRARDADDRU1", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" ], [ "BRAM_CASCOUT_ADDRARDADDRU2", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" ], [ "BRAM_CASCOUT_ADDRARDADDRU3", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" ], [ "BRAM_CASCOUT_ADDRARDADDRU4", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" ], [ "BRAM_CASCOUT_ADDRARDADDRU5", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" ], [ "BRAM_CASCOUT_ADDRARDADDRU6", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" ], [ "BRAM_CASCOUT_ADDRARDADDRU7", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" ], [ "BRAM_CASCOUT_ADDRARDADDRU8", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" ], [ "BRAM_CASCOUT_ADDRARDADDRU9", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" ], [ "BRAM_CASCOUT_ADDRARDADDRU10", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" ], [ "BRAM_CASCOUT_ADDRARDADDRU11", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" ], [ "BRAM_CASCOUT_ADDRARDADDRU12", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" ], [ "BRAM_CASCOUT_ADDRARDADDRU13", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" ], [ "BRAM_CASCOUT_ADDRARDADDRU14", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" ], [ "BRAM_CASCOUT_ADDRBWRADDRU0", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" ], [ "BRAM_CASCOUT_ADDRBWRADDRU1", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" ], [ "BRAM_CASCOUT_ADDRBWRADDRU2", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" ], [ "BRAM_CASCOUT_ADDRBWRADDRU3", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" ], [ "BRAM_CASCOUT_ADDRBWRADDRU4", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" ], [ "BRAM_CASCOUT_ADDRBWRADDRU5", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" ], [ "BRAM_CASCOUT_ADDRBWRADDRU6", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" ], [ "BRAM_CASCOUT_ADDRBWRADDRU7", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" ], [ "BRAM_CASCOUT_ADDRBWRADDRU8", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" ], [ "BRAM_CASCOUT_ADDRBWRADDRU9", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" ], [ "BRAM_CASCOUT_ADDRBWRADDRU10", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" ], [ "BRAM_CASCOUT_ADDRBWRADDRU11", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ "BRAM_CASCOUT_ADDRBWRADDRU12", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" ], [ "BRAM_CASCOUT_ADDRBWRADDRU13", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" ], [ "BRAM_CASCOUT_ADDRBWRADDRU14", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ "BRAM_FIFO36_CASCADEINA", "HCLK_BRAM_CASCADEA_L" ], [ "BRAM_FIFO36_CASCADEINB", "HCLK_BRAM_CASCADEB_L" ], [ "BRAM_PMVBRAM_O", "HCLK_BRAM_PMVBRAM_O" ], [ "BRAM_PMVBRAM_ODIV2", "HCLK_BRAM_PMVBRAM_ODIV2" ], [ "BRAM_PMVBRAM_ODIV4", "HCLK_BRAM_PMVBRAM_ODIV4" ], [ "BRAM_PMVBRAM_SELECT1", "HCLK_BRAM_PMVBRAM_SELECT1" ], [ "BRAM_PMVBRAM_SELECT2", "HCLK_BRAM_PMVBRAM_SELECT2" ], [ "BRAM_PMVBRAM_SELECT3", "HCLK_BRAM_PMVBRAM_SELECT3" ], [ "BRAM_PMVBRAM_SELECT4", "HCLK_BRAM_PMVBRAM_SELECT4" ] ] }, { "grid_deltas": [ -1, -4 ], "tile_types": [ "BRAM_L", "VBRK" ], "wire_pairs": [ [ "BRAM_EE2A0_4", "VBRK_EE2A0" ], [ "BRAM_EE2A1_4", "VBRK_EE2A1" ], [ "BRAM_EE2A2_4", "VBRK_EE2A2" ], [ "BRAM_EE2A3_4", "VBRK_EE2A3" ], [ "BRAM_EE2BEG0_4", "VBRK_EE2BEG0" ], [ "BRAM_EE2BEG1_4", "VBRK_EE2BEG1" ], [ "BRAM_EE2BEG2_4", "VBRK_EE2BEG2" ], [ "BRAM_EE2BEG3_4", "VBRK_EE2BEG3" ], [ "BRAM_EE4A0_4", "VBRK_EE4A0" ], [ "BRAM_EE4A1_4", "VBRK_EE4A1" ], [ "BRAM_EE4A2_4", "VBRK_EE4A2" ], [ "BRAM_EE4A3_4", "VBRK_EE4A3" ], [ "BRAM_EE4B0_4", "VBRK_EE4B0" ], [ "BRAM_EE4B1_4", "VBRK_EE4B1" ], [ "BRAM_EE4B2_4", "VBRK_EE4B2" ], [ "BRAM_EE4B3_4", "VBRK_EE4B3" ], [ "BRAM_EE4BEG0_4", "VBRK_EE4BEG0" ], [ "BRAM_EE4BEG1_4", "VBRK_EE4BEG1" ], [ "BRAM_EE4BEG2_4", "VBRK_EE4BEG2" ], [ "BRAM_EE4BEG3_4", "VBRK_EE4BEG3" ], [ "BRAM_EE4C0_4", "VBRK_EE4C0" ], [ "BRAM_EE4C1_4", "VBRK_EE4C1" ], [ "BRAM_EE4C2_4", "VBRK_EE4C2" ], [ "BRAM_EE4C3_4", "VBRK_EE4C3" ], [ "BRAM_EL1BEG0_4", "VBRK_EL1BEG0" ], [ "BRAM_EL1BEG1_4", "VBRK_EL1BEG1" ], [ "BRAM_EL1BEG2_4", "VBRK_EL1BEG2" ], [ "BRAM_EL1BEG3_4", "VBRK_EL1BEG3" ], [ "BRAM_ER1BEG0_4", "VBRK_ER1BEG0" ], [ "BRAM_ER1BEG1_4", "VBRK_ER1BEG1" ], [ "BRAM_ER1BEG2_4", "VBRK_ER1BEG2" ], [ "BRAM_ER1BEG3_4", "VBRK_ER1BEG3" ], [ "BRAM_LH1_4", "VBRK_LH1" ], [ "BRAM_LH2_4", "VBRK_LH2" ], [ "BRAM_LH3_4", "VBRK_LH3" ], [ "BRAM_LH4_4", "VBRK_LH4" ], [ "BRAM_LH5_4", "VBRK_LH5" ], [ "BRAM_LH6_4", "VBRK_LH6" ], [ "BRAM_LH7_4", "VBRK_LH7" ], [ "BRAM_LH8_4", "VBRK_LH8" ], [ "BRAM_LH9_4", "VBRK_LH9" ], [ "BRAM_LH10_4", "VBRK_LH10" ], [ "BRAM_LH11_4", "VBRK_LH11" ], [ "BRAM_LH12_4", "VBRK_LH12" ], [ "BRAM_MONITOR_N_4", "VBRK_MONITOR_N" ], [ "BRAM_MONITOR_P_4", "VBRK_MONITOR_P" ], [ "BRAM_NE2A0_4", "VBRK_NE2A0" ], [ "BRAM_NE2A1_4", "VBRK_NE2A1" ], [ "BRAM_NE2A2_4", "VBRK_NE2A2" ], [ "BRAM_NE2A3_4", "VBRK_NE2A3" ], [ "BRAM_NE4BEG0_4", "VBRK_NE4BEG0" ], [ "BRAM_NE4BEG1_4", "VBRK_NE4BEG1" ], [ "BRAM_NE4BEG2_4", "VBRK_NE4BEG2" ], [ "BRAM_NE4BEG3_4", "VBRK_NE4BEG3" ], [ "BRAM_NE4C0_4", "VBRK_NE4C0" ], [ "BRAM_NE4C1_4", "VBRK_NE4C1" ], [ "BRAM_NE4C2_4", "VBRK_NE4C2" ], [ "BRAM_NE4C3_4", "VBRK_NE4C3" ], [ "BRAM_NW2A0_4", "VBRK_NW2A0" ], [ "BRAM_NW2A1_4", "VBRK_NW2A1" ], [ "BRAM_NW2A2_4", "VBRK_NW2A2" ], [ "BRAM_NW2A3_4", "VBRK_NW2A3" ], [ "BRAM_NW4A0_4", "VBRK_NW4A0" ], [ "BRAM_NW4A1_4", "VBRK_NW4A1" ], [ "BRAM_NW4A2_4", "VBRK_NW4A2" ], [ "BRAM_NW4A3_4", "VBRK_NW4A3" ], [ "BRAM_NW4END0_4", "VBRK_NW4END0" ], [ "BRAM_NW4END1_4", "VBRK_NW4END1" ], [ "BRAM_NW4END2_4", "VBRK_NW4END2" ], [ "BRAM_NW4END3_4", "VBRK_NW4END3" ], [ "BRAM_SE2A0_4", "VBRK_SE2A0" ], [ "BRAM_SE2A1_4", "VBRK_SE2A1" ], [ "BRAM_SE2A2_4", "VBRK_SE2A2" ], [ "BRAM_SE2A3_4", "VBRK_SE2A3" ], [ "BRAM_SE4BEG0_4", "VBRK_SE4BEG0" ], [ "BRAM_SE4BEG1_4", "VBRK_SE4BEG1" ], [ "BRAM_SE4BEG2_4", "VBRK_SE4BEG2" ], [ "BRAM_SE4BEG3_4", "VBRK_SE4BEG3" ], [ "BRAM_SE4C0_4", "VBRK_SE4C0" ], [ "BRAM_SE4C1_4", "VBRK_SE4C1" ], [ "BRAM_SE4C2_4", "VBRK_SE4C2" ], [ "BRAM_SE4C3_4", "VBRK_SE4C3" ], [ "BRAM_SW2A0_4", "VBRK_SW2A0" ], [ "BRAM_SW2A1_4", "VBRK_SW2A1" ], [ "BRAM_SW2A2_4", "VBRK_SW2A2" ], [ "BRAM_SW2A3_4", "VBRK_SW2A3" ], [ "BRAM_SW4A0_4", "VBRK_SW4A0" ], [ "BRAM_SW4A1_4", "VBRK_SW4A1" ], [ "BRAM_SW4A2_4", "VBRK_SW4A2" ], [ "BRAM_SW4A3_4", "VBRK_SW4A3" ], [ "BRAM_SW4END0_4", "VBRK_SW4END0" ], [ "BRAM_SW4END1_4", "VBRK_SW4END1" ], [ "BRAM_SW4END2_4", "VBRK_SW4END2" ], [ "BRAM_SW4END3_4", "VBRK_SW4END3" ], [ "BRAM_WL1END0_4", "VBRK_WL1END0" ], [ "BRAM_WL1END1_4", "VBRK_WL1END1" ], [ "BRAM_WL1END2_4", "VBRK_WL1END2" ], [ "BRAM_WL1END3_4", "VBRK_WL1END3" ], [ "BRAM_WR1END0_4", "VBRK_WR1END0" ], [ "BRAM_WR1END1_4", "VBRK_WR1END1" ], [ "BRAM_WR1END2_4", "VBRK_WR1END2" ], [ "BRAM_WR1END3_4", "VBRK_WR1END3" ], [ "BRAM_WW2A0_4", "VBRK_WW2A0" ], [ "BRAM_WW2A1_4", "VBRK_WW2A1" ], [ "BRAM_WW2A2_4", "VBRK_WW2A2" ], [ "BRAM_WW2A3_4", "VBRK_WW2A3" ], [ "BRAM_WW2END0_4", "VBRK_WW2END0" ], [ "BRAM_WW2END1_4", "VBRK_WW2END1" ], [ "BRAM_WW2END2_4", "VBRK_WW2END2" ], [ "BRAM_WW2END3_4", "VBRK_WW2END3" ], [ "BRAM_WW4A0_4", "VBRK_WW4A0" ], [ "BRAM_WW4A1_4", "VBRK_WW4A1" ], [ "BRAM_WW4A2_4", "VBRK_WW4A2" ], [ "BRAM_WW4A3_4", "VBRK_WW4A3" ], [ "BRAM_WW4B0_4", "VBRK_WW4B0" ], [ "BRAM_WW4B1_4", "VBRK_WW4B1" ], [ "BRAM_WW4B2_4", "VBRK_WW4B2" ], [ "BRAM_WW4B3_4", "VBRK_WW4B3" ], [ "BRAM_WW4C0_4", "VBRK_WW4C0" ], [ "BRAM_WW4C1_4", "VBRK_WW4C1" ], [ "BRAM_WW4C2_4", "VBRK_WW4C2" ], [ "BRAM_WW4C3_4", "VBRK_WW4C3" ], [ "BRAM_WW4END0_4", "VBRK_WW4END0" ], [ "BRAM_WW4END1_4", "VBRK_WW4END1" ], [ "BRAM_WW4END2_4", "VBRK_WW4END2" ], [ "BRAM_WW4END3_4", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, -3 ], "tile_types": [ "BRAM_L", "VBRK" ], "wire_pairs": [ [ "BRAM_EE2A0_3", "VBRK_EE2A0" ], [ "BRAM_EE2A1_3", "VBRK_EE2A1" ], [ "BRAM_EE2A2_3", "VBRK_EE2A2" ], [ "BRAM_EE2A3_3", "VBRK_EE2A3" ], [ "BRAM_EE2BEG0_3", "VBRK_EE2BEG0" ], [ "BRAM_EE2BEG1_3", "VBRK_EE2BEG1" ], [ "BRAM_EE2BEG2_3", "VBRK_EE2BEG2" ], [ "BRAM_EE2BEG3_3", "VBRK_EE2BEG3" ], [ "BRAM_EE4A0_3", "VBRK_EE4A0" ], [ "BRAM_EE4A1_3", "VBRK_EE4A1" ], [ "BRAM_EE4A2_3", "VBRK_EE4A2" ], [ "BRAM_EE4A3_3", "VBRK_EE4A3" ], [ "BRAM_EE4B0_3", "VBRK_EE4B0" ], [ "BRAM_EE4B1_3", "VBRK_EE4B1" ], [ "BRAM_EE4B2_3", "VBRK_EE4B2" ], [ "BRAM_EE4B3_3", "VBRK_EE4B3" ], [ "BRAM_EE4BEG0_3", "VBRK_EE4BEG0" ], [ "BRAM_EE4BEG1_3", "VBRK_EE4BEG1" ], [ "BRAM_EE4BEG2_3", "VBRK_EE4BEG2" ], [ "BRAM_EE4BEG3_3", "VBRK_EE4BEG3" ], [ "BRAM_EE4C0_3", "VBRK_EE4C0" ], [ "BRAM_EE4C1_3", "VBRK_EE4C1" ], [ "BRAM_EE4C2_3", "VBRK_EE4C2" ], [ "BRAM_EE4C3_3", "VBRK_EE4C3" ], [ "BRAM_EL1BEG0_3", "VBRK_EL1BEG0" ], [ "BRAM_EL1BEG1_3", "VBRK_EL1BEG1" ], [ "BRAM_EL1BEG2_3", "VBRK_EL1BEG2" ], [ "BRAM_EL1BEG3_3", "VBRK_EL1BEG3" ], [ "BRAM_ER1BEG0_3", "VBRK_ER1BEG0" ], [ "BRAM_ER1BEG1_3", "VBRK_ER1BEG1" ], [ "BRAM_ER1BEG2_3", "VBRK_ER1BEG2" ], [ "BRAM_ER1BEG3_3", "VBRK_ER1BEG3" ], [ "BRAM_LH1_3", "VBRK_LH1" ], [ "BRAM_LH2_3", "VBRK_LH2" ], [ "BRAM_LH3_3", "VBRK_LH3" ], [ "BRAM_LH4_3", "VBRK_LH4" ], [ "BRAM_LH5_3", "VBRK_LH5" ], [ "BRAM_LH6_3", "VBRK_LH6" ], [ "BRAM_LH7_3", "VBRK_LH7" ], [ "BRAM_LH8_3", "VBRK_LH8" ], [ "BRAM_LH9_3", "VBRK_LH9" ], [ "BRAM_LH10_3", "VBRK_LH10" ], [ "BRAM_LH11_3", "VBRK_LH11" ], [ "BRAM_LH12_3", "VBRK_LH12" ], [ "BRAM_MONITOR_N_3", "VBRK_MONITOR_N" ], [ "BRAM_MONITOR_P_3", "VBRK_MONITOR_P" ], [ "BRAM_NE2A0_3", "VBRK_NE2A0" ], [ "BRAM_NE2A1_3", "VBRK_NE2A1" ], [ "BRAM_NE2A2_3", "VBRK_NE2A2" ], [ "BRAM_NE2A3_3", "VBRK_NE2A3" ], [ "BRAM_NE4BEG0_3", "VBRK_NE4BEG0" ], [ "BRAM_NE4BEG1_3", "VBRK_NE4BEG1" ], [ "BRAM_NE4BEG2_3", "VBRK_NE4BEG2" ], [ "BRAM_NE4BEG3_3", "VBRK_NE4BEG3" ], [ "BRAM_NE4C0_3", "VBRK_NE4C0" ], [ "BRAM_NE4C1_3", "VBRK_NE4C1" ], [ "BRAM_NE4C2_3", "VBRK_NE4C2" ], [ "BRAM_NE4C3_3", "VBRK_NE4C3" ], [ "BRAM_NW2A0_3", "VBRK_NW2A0" ], [ "BRAM_NW2A1_3", "VBRK_NW2A1" ], [ "BRAM_NW2A2_3", "VBRK_NW2A2" ], [ "BRAM_NW2A3_3", "VBRK_NW2A3" ], [ "BRAM_NW4A0_3", "VBRK_NW4A0" ], [ "BRAM_NW4A1_3", "VBRK_NW4A1" ], [ "BRAM_NW4A2_3", "VBRK_NW4A2" ], [ "BRAM_NW4A3_3", "VBRK_NW4A3" ], [ "BRAM_NW4END0_3", "VBRK_NW4END0" ], [ "BRAM_NW4END1_3", "VBRK_NW4END1" ], [ "BRAM_NW4END2_3", "VBRK_NW4END2" ], [ "BRAM_NW4END3_3", "VBRK_NW4END3" ], [ "BRAM_SE2A0_3", "VBRK_SE2A0" ], [ "BRAM_SE2A1_3", "VBRK_SE2A1" ], [ "BRAM_SE2A2_3", "VBRK_SE2A2" ], [ "BRAM_SE2A3_3", "VBRK_SE2A3" ], [ "BRAM_SE4BEG0_3", "VBRK_SE4BEG0" ], [ "BRAM_SE4BEG1_3", "VBRK_SE4BEG1" ], [ "BRAM_SE4BEG2_3", "VBRK_SE4BEG2" ], [ "BRAM_SE4BEG3_3", "VBRK_SE4BEG3" ], [ "BRAM_SE4C0_3", "VBRK_SE4C0" ], [ "BRAM_SE4C1_3", "VBRK_SE4C1" ], [ "BRAM_SE4C2_3", "VBRK_SE4C2" ], [ "BRAM_SE4C3_3", "VBRK_SE4C3" ], [ "BRAM_SW2A0_3", "VBRK_SW2A0" ], [ "BRAM_SW2A1_3", "VBRK_SW2A1" ], [ "BRAM_SW2A2_3", "VBRK_SW2A2" ], [ "BRAM_SW2A3_3", "VBRK_SW2A3" ], [ "BRAM_SW4A0_3", "VBRK_SW4A0" ], [ "BRAM_SW4A1_3", "VBRK_SW4A1" ], [ "BRAM_SW4A2_3", "VBRK_SW4A2" ], [ "BRAM_SW4A3_3", "VBRK_SW4A3" ], [ "BRAM_SW4END0_3", "VBRK_SW4END0" ], [ "BRAM_SW4END1_3", "VBRK_SW4END1" ], [ "BRAM_SW4END2_3", "VBRK_SW4END2" ], [ "BRAM_SW4END3_3", "VBRK_SW4END3" ], [ "BRAM_WL1END0_3", "VBRK_WL1END0" ], [ "BRAM_WL1END1_3", "VBRK_WL1END1" ], [ "BRAM_WL1END2_3", "VBRK_WL1END2" ], [ "BRAM_WL1END3_3", "VBRK_WL1END3" ], [ "BRAM_WR1END0_3", "VBRK_WR1END0" ], [ "BRAM_WR1END1_3", "VBRK_WR1END1" ], [ "BRAM_WR1END2_3", "VBRK_WR1END2" ], [ "BRAM_WR1END3_3", "VBRK_WR1END3" ], [ "BRAM_WW2A0_3", "VBRK_WW2A0" ], [ "BRAM_WW2A1_3", "VBRK_WW2A1" ], [ "BRAM_WW2A2_3", "VBRK_WW2A2" ], [ "BRAM_WW2A3_3", "VBRK_WW2A3" ], [ "BRAM_WW2END0_3", "VBRK_WW2END0" ], [ "BRAM_WW2END1_3", "VBRK_WW2END1" ], [ "BRAM_WW2END2_3", "VBRK_WW2END2" ], [ "BRAM_WW2END3_3", "VBRK_WW2END3" ], [ "BRAM_WW4A0_3", "VBRK_WW4A0" ], [ "BRAM_WW4A1_3", "VBRK_WW4A1" ], [ "BRAM_WW4A2_3", "VBRK_WW4A2" ], [ "BRAM_WW4A3_3", "VBRK_WW4A3" ], [ "BRAM_WW4B0_3", "VBRK_WW4B0" ], [ "BRAM_WW4B1_3", "VBRK_WW4B1" ], [ "BRAM_WW4B2_3", "VBRK_WW4B2" ], [ "BRAM_WW4B3_3", "VBRK_WW4B3" ], [ "BRAM_WW4C0_3", "VBRK_WW4C0" ], [ "BRAM_WW4C1_3", "VBRK_WW4C1" ], [ "BRAM_WW4C2_3", "VBRK_WW4C2" ], [ "BRAM_WW4C3_3", "VBRK_WW4C3" ], [ "BRAM_WW4END0_3", "VBRK_WW4END0" ], [ "BRAM_WW4END1_3", "VBRK_WW4END1" ], [ "BRAM_WW4END2_3", "VBRK_WW4END2" ], [ "BRAM_WW4END3_3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, -2 ], "tile_types": [ "BRAM_L", "VBRK" ], "wire_pairs": [ [ "BRAM_EE2A0_2", "VBRK_EE2A0" ], [ "BRAM_EE2A1_2", "VBRK_EE2A1" ], [ "BRAM_EE2A2_2", "VBRK_EE2A2" ], [ "BRAM_EE2A3_2", "VBRK_EE2A3" ], [ "BRAM_EE2BEG0_2", "VBRK_EE2BEG0" ], [ "BRAM_EE2BEG1_2", "VBRK_EE2BEG1" ], [ "BRAM_EE2BEG2_2", "VBRK_EE2BEG2" ], [ "BRAM_EE2BEG3_2", "VBRK_EE2BEG3" ], [ "BRAM_EE4A0_2", "VBRK_EE4A0" ], [ "BRAM_EE4A1_2", "VBRK_EE4A1" ], [ "BRAM_EE4A2_2", "VBRK_EE4A2" ], [ "BRAM_EE4A3_2", "VBRK_EE4A3" ], [ "BRAM_EE4B0_2", "VBRK_EE4B0" ], [ "BRAM_EE4B1_2", "VBRK_EE4B1" ], [ "BRAM_EE4B2_2", "VBRK_EE4B2" ], [ "BRAM_EE4B3_2", "VBRK_EE4B3" ], [ "BRAM_EE4BEG0_2", "VBRK_EE4BEG0" ], [ "BRAM_EE4BEG1_2", "VBRK_EE4BEG1" ], [ "BRAM_EE4BEG2_2", "VBRK_EE4BEG2" ], [ "BRAM_EE4BEG3_2", "VBRK_EE4BEG3" ], [ "BRAM_EE4C0_2", "VBRK_EE4C0" ], [ "BRAM_EE4C1_2", "VBRK_EE4C1" ], [ "BRAM_EE4C2_2", "VBRK_EE4C2" ], [ "BRAM_EE4C3_2", "VBRK_EE4C3" ], [ "BRAM_EL1BEG0_2", "VBRK_EL1BEG0" ], [ "BRAM_EL1BEG1_2", "VBRK_EL1BEG1" ], [ "BRAM_EL1BEG2_2", "VBRK_EL1BEG2" ], [ "BRAM_EL1BEG3_2", "VBRK_EL1BEG3" ], [ "BRAM_ER1BEG0_2", "VBRK_ER1BEG0" ], [ "BRAM_ER1BEG1_2", "VBRK_ER1BEG1" ], [ "BRAM_ER1BEG2_2", "VBRK_ER1BEG2" ], [ "BRAM_ER1BEG3_2", "VBRK_ER1BEG3" ], [ "BRAM_LH1_2", "VBRK_LH1" ], [ "BRAM_LH2_2", "VBRK_LH2" ], [ "BRAM_LH3_2", "VBRK_LH3" ], [ "BRAM_LH4_2", "VBRK_LH4" ], [ "BRAM_LH5_2", "VBRK_LH5" ], [ "BRAM_LH6_2", "VBRK_LH6" ], [ "BRAM_LH7_2", "VBRK_LH7" ], [ "BRAM_LH8_2", "VBRK_LH8" ], [ "BRAM_LH9_2", "VBRK_LH9" ], [ "BRAM_LH10_2", "VBRK_LH10" ], [ "BRAM_LH11_2", "VBRK_LH11" ], [ "BRAM_LH12_2", "VBRK_LH12" ], [ "BRAM_MONITOR_N_2", "VBRK_MONITOR_N" ], [ "BRAM_MONITOR_P_2", "VBRK_MONITOR_P" ], [ "BRAM_NE2A0_2", "VBRK_NE2A0" ], [ "BRAM_NE2A1_2", "VBRK_NE2A1" ], [ "BRAM_NE2A2_2", "VBRK_NE2A2" ], [ "BRAM_NE2A3_2", "VBRK_NE2A3" ], [ "BRAM_NE4BEG0_2", "VBRK_NE4BEG0" ], [ "BRAM_NE4BEG1_2", "VBRK_NE4BEG1" ], [ "BRAM_NE4BEG2_2", "VBRK_NE4BEG2" ], [ "BRAM_NE4BEG3_2", "VBRK_NE4BEG3" ], [ "BRAM_NE4C0_2", "VBRK_NE4C0" ], [ "BRAM_NE4C1_2", "VBRK_NE4C1" ], [ "BRAM_NE4C2_2", "VBRK_NE4C2" ], [ "BRAM_NE4C3_2", "VBRK_NE4C3" ], [ "BRAM_NW2A0_2", "VBRK_NW2A0" ], [ "BRAM_NW2A1_2", "VBRK_NW2A1" ], [ "BRAM_NW2A2_2", "VBRK_NW2A2" ], [ "BRAM_NW2A3_2", "VBRK_NW2A3" ], [ "BRAM_NW4A0_2", "VBRK_NW4A0" ], [ "BRAM_NW4A1_2", "VBRK_NW4A1" ], [ "BRAM_NW4A2_2", "VBRK_NW4A2" ], [ "BRAM_NW4A3_2", "VBRK_NW4A3" ], [ "BRAM_NW4END0_2", "VBRK_NW4END0" ], [ "BRAM_NW4END1_2", "VBRK_NW4END1" ], [ "BRAM_NW4END2_2", "VBRK_NW4END2" ], [ "BRAM_NW4END3_2", "VBRK_NW4END3" ], [ "BRAM_SE2A0_2", "VBRK_SE2A0" ], [ "BRAM_SE2A1_2", "VBRK_SE2A1" ], [ "BRAM_SE2A2_2", "VBRK_SE2A2" ], [ "BRAM_SE2A3_2", "VBRK_SE2A3" ], [ "BRAM_SE4BEG0_2", "VBRK_SE4BEG0" ], [ "BRAM_SE4BEG1_2", "VBRK_SE4BEG1" ], [ "BRAM_SE4BEG2_2", "VBRK_SE4BEG2" ], [ "BRAM_SE4BEG3_2", "VBRK_SE4BEG3" ], [ "BRAM_SE4C0_2", "VBRK_SE4C0" ], [ "BRAM_SE4C1_2", "VBRK_SE4C1" ], [ "BRAM_SE4C2_2", "VBRK_SE4C2" ], [ "BRAM_SE4C3_2", "VBRK_SE4C3" ], [ "BRAM_SW2A0_2", "VBRK_SW2A0" ], [ "BRAM_SW2A1_2", "VBRK_SW2A1" ], [ "BRAM_SW2A2_2", "VBRK_SW2A2" ], [ "BRAM_SW2A3_2", "VBRK_SW2A3" ], [ "BRAM_SW4A0_2", "VBRK_SW4A0" ], [ "BRAM_SW4A1_2", "VBRK_SW4A1" ], [ "BRAM_SW4A2_2", "VBRK_SW4A2" ], [ "BRAM_SW4A3_2", "VBRK_SW4A3" ], [ "BRAM_SW4END0_2", "VBRK_SW4END0" ], [ "BRAM_SW4END1_2", "VBRK_SW4END1" ], [ "BRAM_SW4END2_2", "VBRK_SW4END2" ], [ "BRAM_SW4END3_2", "VBRK_SW4END3" ], [ "BRAM_WL1END0_2", "VBRK_WL1END0" ], [ "BRAM_WL1END1_2", "VBRK_WL1END1" ], [ "BRAM_WL1END2_2", "VBRK_WL1END2" ], [ "BRAM_WL1END3_2", "VBRK_WL1END3" ], [ "BRAM_WR1END0_2", "VBRK_WR1END0" ], [ "BRAM_WR1END1_2", "VBRK_WR1END1" ], [ "BRAM_WR1END2_2", "VBRK_WR1END2" ], [ "BRAM_WR1END3_2", "VBRK_WR1END3" ], [ "BRAM_WW2A0_2", "VBRK_WW2A0" ], [ "BRAM_WW2A1_2", "VBRK_WW2A1" ], [ "BRAM_WW2A2_2", "VBRK_WW2A2" ], [ "BRAM_WW2A3_2", "VBRK_WW2A3" ], [ "BRAM_WW2END0_2", "VBRK_WW2END0" ], [ "BRAM_WW2END1_2", "VBRK_WW2END1" ], [ "BRAM_WW2END2_2", "VBRK_WW2END2" ], [ "BRAM_WW2END3_2", "VBRK_WW2END3" ], [ "BRAM_WW4A0_2", "VBRK_WW4A0" ], [ "BRAM_WW4A1_2", "VBRK_WW4A1" ], [ "BRAM_WW4A2_2", "VBRK_WW4A2" ], [ "BRAM_WW4A3_2", "VBRK_WW4A3" ], [ "BRAM_WW4B0_2", "VBRK_WW4B0" ], [ "BRAM_WW4B1_2", "VBRK_WW4B1" ], [ "BRAM_WW4B2_2", "VBRK_WW4B2" ], [ "BRAM_WW4B3_2", "VBRK_WW4B3" ], [ "BRAM_WW4C0_2", "VBRK_WW4C0" ], [ "BRAM_WW4C1_2", "VBRK_WW4C1" ], [ "BRAM_WW4C2_2", "VBRK_WW4C2" ], [ "BRAM_WW4C3_2", "VBRK_WW4C3" ], [ "BRAM_WW4END0_2", "VBRK_WW4END0" ], [ "BRAM_WW4END1_2", "VBRK_WW4END1" ], [ "BRAM_WW4END2_2", "VBRK_WW4END2" ], [ "BRAM_WW4END3_2", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, -1 ], "tile_types": [ "BRAM_L", "VBRK" ], "wire_pairs": [ [ "BRAM_EE2A0_1", "VBRK_EE2A0" ], [ "BRAM_EE2A1_1", "VBRK_EE2A1" ], [ "BRAM_EE2A2_1", "VBRK_EE2A2" ], [ "BRAM_EE2A3_1", "VBRK_EE2A3" ], [ "BRAM_EE2BEG0_1", "VBRK_EE2BEG0" ], [ "BRAM_EE2BEG1_1", "VBRK_EE2BEG1" ], [ "BRAM_EE2BEG2_1", "VBRK_EE2BEG2" ], [ "BRAM_EE2BEG3_1", "VBRK_EE2BEG3" ], [ "BRAM_EE4A0_1", "VBRK_EE4A0" ], [ "BRAM_EE4A1_1", "VBRK_EE4A1" ], [ "BRAM_EE4A2_1", "VBRK_EE4A2" ], [ "BRAM_EE4A3_1", "VBRK_EE4A3" ], [ "BRAM_EE4B0_1", "VBRK_EE4B0" ], [ "BRAM_EE4B1_1", "VBRK_EE4B1" ], [ "BRAM_EE4B2_1", "VBRK_EE4B2" ], [ "BRAM_EE4B3_1", "VBRK_EE4B3" ], [ "BRAM_EE4BEG0_1", "VBRK_EE4BEG0" ], [ "BRAM_EE4BEG1_1", "VBRK_EE4BEG1" ], [ "BRAM_EE4BEG2_1", "VBRK_EE4BEG2" ], [ "BRAM_EE4BEG3_1", "VBRK_EE4BEG3" ], [ "BRAM_EE4C0_1", "VBRK_EE4C0" ], [ "BRAM_EE4C1_1", "VBRK_EE4C1" ], [ "BRAM_EE4C2_1", "VBRK_EE4C2" ], [ "BRAM_EE4C3_1", "VBRK_EE4C3" ], [ "BRAM_EL1BEG0_1", "VBRK_EL1BEG0" ], [ "BRAM_EL1BEG1_1", "VBRK_EL1BEG1" ], [ "BRAM_EL1BEG2_1", "VBRK_EL1BEG2" ], [ "BRAM_EL1BEG3_1", "VBRK_EL1BEG3" ], [ "BRAM_ER1BEG0_1", "VBRK_ER1BEG0" ], [ "BRAM_ER1BEG1_1", "VBRK_ER1BEG1" ], [ "BRAM_ER1BEG2_1", "VBRK_ER1BEG2" ], [ "BRAM_ER1BEG3_1", "VBRK_ER1BEG3" ], [ "BRAM_LH1_1", "VBRK_LH1" ], [ "BRAM_LH2_1", "VBRK_LH2" ], [ "BRAM_LH3_1", "VBRK_LH3" ], [ "BRAM_LH4_1", "VBRK_LH4" ], [ "BRAM_LH5_1", "VBRK_LH5" ], [ "BRAM_LH6_1", "VBRK_LH6" ], [ "BRAM_LH7_1", "VBRK_LH7" ], [ "BRAM_LH8_1", "VBRK_LH8" ], [ "BRAM_LH9_1", "VBRK_LH9" ], [ "BRAM_LH10_1", "VBRK_LH10" ], [ "BRAM_LH11_1", "VBRK_LH11" ], [ "BRAM_LH12_1", "VBRK_LH12" ], [ "BRAM_MONITOR_N_1", "VBRK_MONITOR_N" ], [ "BRAM_MONITOR_P_1", "VBRK_MONITOR_P" ], [ "BRAM_NE2A0_1", "VBRK_NE2A0" ], [ "BRAM_NE2A1_1", "VBRK_NE2A1" ], [ "BRAM_NE2A2_1", "VBRK_NE2A2" ], [ "BRAM_NE2A3_1", "VBRK_NE2A3" ], [ "BRAM_NE4BEG0_1", "VBRK_NE4BEG0" ], [ "BRAM_NE4BEG1_1", "VBRK_NE4BEG1" ], [ "BRAM_NE4BEG2_1", "VBRK_NE4BEG2" ], [ "BRAM_NE4BEG3_1", "VBRK_NE4BEG3" ], [ "BRAM_NE4C0_1", "VBRK_NE4C0" ], [ "BRAM_NE4C1_1", "VBRK_NE4C1" ], [ "BRAM_NE4C2_1", "VBRK_NE4C2" ], [ "BRAM_NE4C3_1", "VBRK_NE4C3" ], [ "BRAM_NW2A0_1", "VBRK_NW2A0" ], [ "BRAM_NW2A1_1", "VBRK_NW2A1" ], [ "BRAM_NW2A2_1", "VBRK_NW2A2" ], [ "BRAM_NW2A3_1", "VBRK_NW2A3" ], [ "BRAM_NW4A0_1", "VBRK_NW4A0" ], [ "BRAM_NW4A1_1", "VBRK_NW4A1" ], [ "BRAM_NW4A2_1", "VBRK_NW4A2" ], [ "BRAM_NW4A3_1", "VBRK_NW4A3" ], [ "BRAM_NW4END0_1", "VBRK_NW4END0" ], [ "BRAM_NW4END1_1", "VBRK_NW4END1" ], [ "BRAM_NW4END2_1", "VBRK_NW4END2" ], [ "BRAM_NW4END3_1", "VBRK_NW4END3" ], [ "BRAM_SE2A0_1", "VBRK_SE2A0" ], [ "BRAM_SE2A1_1", "VBRK_SE2A1" ], [ "BRAM_SE2A2_1", "VBRK_SE2A2" ], [ "BRAM_SE2A3_1", "VBRK_SE2A3" ], [ "BRAM_SE4BEG0_1", "VBRK_SE4BEG0" ], [ "BRAM_SE4BEG1_1", "VBRK_SE4BEG1" ], [ "BRAM_SE4BEG2_1", "VBRK_SE4BEG2" ], [ "BRAM_SE4BEG3_1", "VBRK_SE4BEG3" ], [ "BRAM_SE4C0_1", "VBRK_SE4C0" ], [ "BRAM_SE4C1_1", "VBRK_SE4C1" ], [ "BRAM_SE4C2_1", "VBRK_SE4C2" ], [ "BRAM_SE4C3_1", "VBRK_SE4C3" ], [ "BRAM_SW2A0_1", "VBRK_SW2A0" ], [ "BRAM_SW2A1_1", "VBRK_SW2A1" ], [ "BRAM_SW2A2_1", "VBRK_SW2A2" ], [ "BRAM_SW2A3_1", "VBRK_SW2A3" ], [ "BRAM_SW4A0_1", "VBRK_SW4A0" ], [ "BRAM_SW4A1_1", "VBRK_SW4A1" ], [ "BRAM_SW4A2_1", "VBRK_SW4A2" ], [ "BRAM_SW4A3_1", "VBRK_SW4A3" ], [ "BRAM_SW4END0_1", "VBRK_SW4END0" ], [ "BRAM_SW4END1_1", "VBRK_SW4END1" ], [ "BRAM_SW4END2_1", "VBRK_SW4END2" ], [ "BRAM_SW4END3_1", "VBRK_SW4END3" ], [ "BRAM_WL1END0_1", "VBRK_WL1END0" ], [ "BRAM_WL1END1_1", "VBRK_WL1END1" ], [ "BRAM_WL1END2_1", "VBRK_WL1END2" ], [ "BRAM_WL1END3_1", "VBRK_WL1END3" ], [ "BRAM_WR1END0_1", "VBRK_WR1END0" ], [ "BRAM_WR1END1_1", "VBRK_WR1END1" ], [ "BRAM_WR1END2_1", "VBRK_WR1END2" ], [ "BRAM_WR1END3_1", "VBRK_WR1END3" ], [ "BRAM_WW2A0_1", "VBRK_WW2A0" ], [ "BRAM_WW2A1_1", "VBRK_WW2A1" ], [ "BRAM_WW2A2_1", "VBRK_WW2A2" ], [ "BRAM_WW2A3_1", "VBRK_WW2A3" ], [ "BRAM_WW2END0_1", "VBRK_WW2END0" ], [ "BRAM_WW2END1_1", "VBRK_WW2END1" ], [ "BRAM_WW2END2_1", "VBRK_WW2END2" ], [ "BRAM_WW2END3_1", "VBRK_WW2END3" ], [ "BRAM_WW4A0_1", "VBRK_WW4A0" ], [ "BRAM_WW4A1_1", "VBRK_WW4A1" ], [ "BRAM_WW4A2_1", "VBRK_WW4A2" ], [ "BRAM_WW4A3_1", "VBRK_WW4A3" ], [ "BRAM_WW4B0_1", "VBRK_WW4B0" ], [ "BRAM_WW4B1_1", "VBRK_WW4B1" ], [ "BRAM_WW4B2_1", "VBRK_WW4B2" ], [ "BRAM_WW4B3_1", "VBRK_WW4B3" ], [ "BRAM_WW4C0_1", "VBRK_WW4C0" ], [ "BRAM_WW4C1_1", "VBRK_WW4C1" ], [ "BRAM_WW4C2_1", "VBRK_WW4C2" ], [ "BRAM_WW4C3_1", "VBRK_WW4C3" ], [ "BRAM_WW4END0_1", "VBRK_WW4END0" ], [ "BRAM_WW4END1_1", "VBRK_WW4END1" ], [ "BRAM_WW4END2_1", "VBRK_WW4END2" ], [ "BRAM_WW4END3_1", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "BRAM_L", "VBRK" ], "wire_pairs": [ [ "BRAM_EE2A0_0", "VBRK_EE2A0" ], [ "BRAM_EE2A1_0", "VBRK_EE2A1" ], [ "BRAM_EE2A2_0", "VBRK_EE2A2" ], [ "BRAM_EE2A3_0", "VBRK_EE2A3" ], [ "BRAM_EE2BEG0_0", "VBRK_EE2BEG0" ], [ "BRAM_EE2BEG1_0", "VBRK_EE2BEG1" ], [ "BRAM_EE2BEG2_0", "VBRK_EE2BEG2" ], [ "BRAM_EE2BEG3_0", "VBRK_EE2BEG3" ], [ "BRAM_EE4A0_0", "VBRK_EE4A0" ], [ "BRAM_EE4A1_0", "VBRK_EE4A1" ], [ "BRAM_EE4A2_0", "VBRK_EE4A2" ], [ "BRAM_EE4A3_0", "VBRK_EE4A3" ], [ "BRAM_EE4B0_0", "VBRK_EE4B0" ], [ "BRAM_EE4B1_0", "VBRK_EE4B1" ], [ "BRAM_EE4B2_0", "VBRK_EE4B2" ], [ "BRAM_EE4B3_0", "VBRK_EE4B3" ], [ "BRAM_EE4BEG0_0", "VBRK_EE4BEG0" ], [ "BRAM_EE4BEG1_0", "VBRK_EE4BEG1" ], [ "BRAM_EE4BEG2_0", "VBRK_EE4BEG2" ], [ "BRAM_EE4BEG3_0", "VBRK_EE4BEG3" ], [ "BRAM_EE4C0_0", "VBRK_EE4C0" ], [ "BRAM_EE4C1_0", "VBRK_EE4C1" ], [ "BRAM_EE4C2_0", "VBRK_EE4C2" ], [ "BRAM_EE4C3_0", "VBRK_EE4C3" ], [ "BRAM_EL1BEG0_0", "VBRK_EL1BEG0" ], [ "BRAM_EL1BEG1_0", "VBRK_EL1BEG1" ], [ "BRAM_EL1BEG2_0", "VBRK_EL1BEG2" ], [ "BRAM_EL1BEG3_0", "VBRK_EL1BEG3" ], [ "BRAM_ER1BEG0_0", "VBRK_ER1BEG0" ], [ "BRAM_ER1BEG1_0", "VBRK_ER1BEG1" ], [ "BRAM_ER1BEG2_0", "VBRK_ER1BEG2" ], [ "BRAM_ER1BEG3_0", "VBRK_ER1BEG3" ], [ "BRAM_LH1_0", "VBRK_LH1" ], [ "BRAM_LH2_0", "VBRK_LH2" ], [ "BRAM_LH3_0", "VBRK_LH3" ], [ "BRAM_LH4_0", "VBRK_LH4" ], [ "BRAM_LH5_0", "VBRK_LH5" ], [ "BRAM_LH6_0", "VBRK_LH6" ], [ "BRAM_LH7_0", "VBRK_LH7" ], [ "BRAM_LH8_0", "VBRK_LH8" ], [ "BRAM_LH9_0", "VBRK_LH9" ], [ "BRAM_LH10_0", "VBRK_LH10" ], [ "BRAM_LH11_0", "VBRK_LH11" ], [ "BRAM_LH12_0", "VBRK_LH12" ], [ "BRAM_MONITOR_N_0", "VBRK_MONITOR_N" ], [ "BRAM_MONITOR_P_0", "VBRK_MONITOR_P" ], [ "BRAM_NE2A0_0", "VBRK_NE2A0" ], [ "BRAM_NE2A1_0", "VBRK_NE2A1" ], [ "BRAM_NE2A2_0", "VBRK_NE2A2" ], [ "BRAM_NE2A3_0", "VBRK_NE2A3" ], [ "BRAM_NE4BEG0_0", "VBRK_NE4BEG0" ], [ "BRAM_NE4BEG1_0", "VBRK_NE4BEG1" ], [ "BRAM_NE4BEG2_0", "VBRK_NE4BEG2" ], [ "BRAM_NE4BEG3_0", "VBRK_NE4BEG3" ], [ "BRAM_NE4C0_0", "VBRK_NE4C0" ], [ "BRAM_NE4C1_0", "VBRK_NE4C1" ], [ "BRAM_NE4C2_0", "VBRK_NE4C2" ], [ "BRAM_NE4C3_0", "VBRK_NE4C3" ], [ "BRAM_NW2A0_0", "VBRK_NW2A0" ], [ "BRAM_NW2A1_0", "VBRK_NW2A1" ], [ "BRAM_NW2A2_0", "VBRK_NW2A2" ], [ "BRAM_NW2A3_0", "VBRK_NW2A3" ], [ "BRAM_NW4A0_0", "VBRK_NW4A0" ], [ "BRAM_NW4A1_0", "VBRK_NW4A1" ], [ "BRAM_NW4A2_0", "VBRK_NW4A2" ], [ "BRAM_NW4A3_0", "VBRK_NW4A3" ], [ "BRAM_NW4END0_0", "VBRK_NW4END0" ], [ "BRAM_NW4END1_0", "VBRK_NW4END1" ], [ "BRAM_NW4END2_0", "VBRK_NW4END2" ], [ "BRAM_NW4END3_0", "VBRK_NW4END3" ], [ "BRAM_SE2A0_0", "VBRK_SE2A0" ], [ "BRAM_SE2A1_0", "VBRK_SE2A1" ], [ "BRAM_SE2A2_0", "VBRK_SE2A2" ], [ "BRAM_SE2A3_0", "VBRK_SE2A3" ], [ "BRAM_SE4BEG0_0", "VBRK_SE4BEG0" ], [ "BRAM_SE4BEG1_0", "VBRK_SE4BEG1" ], [ "BRAM_SE4BEG2_0", "VBRK_SE4BEG2" ], [ "BRAM_SE4BEG3_0", "VBRK_SE4BEG3" ], [ "BRAM_SE4C0_0", "VBRK_SE4C0" ], [ "BRAM_SE4C1_0", "VBRK_SE4C1" ], [ "BRAM_SE4C2_0", "VBRK_SE4C2" ], [ "BRAM_SE4C3_0", "VBRK_SE4C3" ], [ "BRAM_SW2A0_0", "VBRK_SW2A0" ], [ "BRAM_SW2A1_0", "VBRK_SW2A1" ], [ "BRAM_SW2A2_0", "VBRK_SW2A2" ], [ "BRAM_SW2A3_0", "VBRK_SW2A3" ], [ "BRAM_SW4A0_0", "VBRK_SW4A0" ], [ "BRAM_SW4A1_0", "VBRK_SW4A1" ], [ "BRAM_SW4A2_0", "VBRK_SW4A2" ], [ "BRAM_SW4A3_0", "VBRK_SW4A3" ], [ "BRAM_SW4END0_0", "VBRK_SW4END0" ], [ "BRAM_SW4END1_0", "VBRK_SW4END1" ], [ "BRAM_SW4END2_0", "VBRK_SW4END2" ], [ "BRAM_SW4END3_0", "VBRK_SW4END3" ], [ "BRAM_WL1END0_0", "VBRK_WL1END0" ], [ "BRAM_WL1END1_0", "VBRK_WL1END1" ], [ "BRAM_WL1END2_0", "VBRK_WL1END2" ], [ "BRAM_WL1END3_0", "VBRK_WL1END3" ], [ "BRAM_WR1END0_0", "VBRK_WR1END0" ], [ "BRAM_WR1END1_0", "VBRK_WR1END1" ], [ "BRAM_WR1END2_0", "VBRK_WR1END2" ], [ "BRAM_WR1END3_0", "VBRK_WR1END3" ], [ "BRAM_WW2A0_0", "VBRK_WW2A0" ], [ "BRAM_WW2A1_0", "VBRK_WW2A1" ], [ "BRAM_WW2A2_0", "VBRK_WW2A2" ], [ "BRAM_WW2A3_0", "VBRK_WW2A3" ], [ "BRAM_WW2END0_0", "VBRK_WW2END0" ], [ "BRAM_WW2END1_0", "VBRK_WW2END1" ], [ "BRAM_WW2END2_0", "VBRK_WW2END2" ], [ "BRAM_WW2END3_0", "VBRK_WW2END3" ], [ "BRAM_WW4A0_0", "VBRK_WW4A0" ], [ "BRAM_WW4A1_0", "VBRK_WW4A1" ], [ "BRAM_WW4A2_0", "VBRK_WW4A2" ], [ "BRAM_WW4A3_0", "VBRK_WW4A3" ], [ "BRAM_WW4B0_0", "VBRK_WW4B0" ], [ "BRAM_WW4B1_0", "VBRK_WW4B1" ], [ "BRAM_WW4B2_0", "VBRK_WW4B2" ], [ "BRAM_WW4B3_0", "VBRK_WW4B3" ], [ "BRAM_WW4C0_0", "VBRK_WW4C0" ], [ "BRAM_WW4C1_0", "VBRK_WW4C1" ], [ "BRAM_WW4C2_0", "VBRK_WW4C2" ], [ "BRAM_WW4C3_0", "VBRK_WW4C3" ], [ "BRAM_WW4END0_0", "VBRK_WW4END0" ], [ "BRAM_WW4END1_0", "VBRK_WW4END1" ], [ "BRAM_WW4END2_0", "VBRK_WW4END2" ], [ "BRAM_WW4END3_0", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 0, -5 ], "tile_types": [ "BRAM_R", "BRAM_R" ], "wire_pairs": [ [ "BRAM_CASCINTOP_ADDRARDADDRU0", "BRAM_CASCOUT_ADDRARDADDRU0" ], [ "BRAM_CASCINTOP_ADDRARDADDRU1", "BRAM_CASCOUT_ADDRARDADDRU1" ], [ "BRAM_CASCINTOP_ADDRARDADDRU2", "BRAM_CASCOUT_ADDRARDADDRU2" ], [ "BRAM_CASCINTOP_ADDRARDADDRU3", "BRAM_CASCOUT_ADDRARDADDRU3" ], [ "BRAM_CASCINTOP_ADDRARDADDRU4", "BRAM_CASCOUT_ADDRARDADDRU4" ], [ "BRAM_CASCINTOP_ADDRARDADDRU5", "BRAM_CASCOUT_ADDRARDADDRU5" ], [ "BRAM_CASCINTOP_ADDRARDADDRU6", "BRAM_CASCOUT_ADDRARDADDRU6" ], [ "BRAM_CASCINTOP_ADDRARDADDRU7", "BRAM_CASCOUT_ADDRARDADDRU7" ], [ "BRAM_CASCINTOP_ADDRARDADDRU8", "BRAM_CASCOUT_ADDRARDADDRU8" ], [ "BRAM_CASCINTOP_ADDRARDADDRU9", "BRAM_CASCOUT_ADDRARDADDRU9" ], [ "BRAM_CASCINTOP_ADDRARDADDRU10", "BRAM_CASCOUT_ADDRARDADDRU10" ], [ "BRAM_CASCINTOP_ADDRARDADDRU11", "BRAM_CASCOUT_ADDRARDADDRU11" ], [ "BRAM_CASCINTOP_ADDRARDADDRU12", "BRAM_CASCOUT_ADDRARDADDRU12" ], [ "BRAM_CASCINTOP_ADDRARDADDRU13", "BRAM_CASCOUT_ADDRARDADDRU13" ], [ "BRAM_CASCINTOP_ADDRARDADDRU14", "BRAM_CASCOUT_ADDRARDADDRU14" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU0", "BRAM_CASCOUT_ADDRBWRADDRU0" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU1", "BRAM_CASCOUT_ADDRBWRADDRU1" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU2", "BRAM_CASCOUT_ADDRBWRADDRU2" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU3", "BRAM_CASCOUT_ADDRBWRADDRU3" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU4", "BRAM_CASCOUT_ADDRBWRADDRU4" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU5", "BRAM_CASCOUT_ADDRBWRADDRU5" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU6", "BRAM_CASCOUT_ADDRBWRADDRU6" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU7", "BRAM_CASCOUT_ADDRBWRADDRU7" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU8", "BRAM_CASCOUT_ADDRBWRADDRU8" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU9", "BRAM_CASCOUT_ADDRBWRADDRU9" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU10", "BRAM_CASCOUT_ADDRBWRADDRU10" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU11", "BRAM_CASCOUT_ADDRBWRADDRU11" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU12", "BRAM_CASCOUT_ADDRBWRADDRU12" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU13", "BRAM_CASCOUT_ADDRBWRADDRU13" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU14", "BRAM_CASCOUT_ADDRBWRADDRU14" ], [ "BRAM_PMVBRAM_O", "BRAM_PMVBRAM_O_1" ], [ "BRAM_PMVBRAM_ODIV2", "BRAM_PMVBRAM_ODIV2_1" ], [ "BRAM_PMVBRAM_O_1", "BRAM_PMVBRAM_O_2" ] ] }, { "grid_deltas": [ 0, 5 ], "tile_types": [ "BRAM_R", "BRAM_R" ], "wire_pairs": [ [ "BRAM_CASCINBOT_ADDRARDADDRU0", "BRAM_CASCOUT_ADDRARDADDRU0" ], [ "BRAM_CASCINBOT_ADDRARDADDRU1", "BRAM_CASCOUT_ADDRARDADDRU1" ], [ "BRAM_CASCINBOT_ADDRARDADDRU2", "BRAM_CASCOUT_ADDRARDADDRU2" ], [ "BRAM_CASCINBOT_ADDRARDADDRU3", "BRAM_CASCOUT_ADDRARDADDRU3" ], [ "BRAM_CASCINBOT_ADDRARDADDRU4", "BRAM_CASCOUT_ADDRARDADDRU4" ], [ "BRAM_CASCINBOT_ADDRARDADDRU5", "BRAM_CASCOUT_ADDRARDADDRU5" ], [ "BRAM_CASCINBOT_ADDRARDADDRU6", "BRAM_CASCOUT_ADDRARDADDRU6" ], [ "BRAM_CASCINBOT_ADDRARDADDRU7", "BRAM_CASCOUT_ADDRARDADDRU7" ], [ "BRAM_CASCINBOT_ADDRARDADDRU8", "BRAM_CASCOUT_ADDRARDADDRU8" ], [ "BRAM_CASCINBOT_ADDRARDADDRU9", "BRAM_CASCOUT_ADDRARDADDRU9" ], [ "BRAM_CASCINBOT_ADDRARDADDRU10", "BRAM_CASCOUT_ADDRARDADDRU10" ], [ "BRAM_CASCINBOT_ADDRARDADDRU11", "BRAM_CASCOUT_ADDRARDADDRU11" ], [ "BRAM_CASCINBOT_ADDRARDADDRU12", "BRAM_CASCOUT_ADDRARDADDRU12" ], [ "BRAM_CASCINBOT_ADDRARDADDRU13", "BRAM_CASCOUT_ADDRARDADDRU13" ], [ "BRAM_CASCINBOT_ADDRARDADDRU14", "BRAM_CASCOUT_ADDRARDADDRU14" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU0", "BRAM_CASCOUT_ADDRBWRADDRU0" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU1", "BRAM_CASCOUT_ADDRBWRADDRU1" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU2", "BRAM_CASCOUT_ADDRBWRADDRU2" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU3", "BRAM_CASCOUT_ADDRBWRADDRU3" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU4", "BRAM_CASCOUT_ADDRBWRADDRU4" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU5", "BRAM_CASCOUT_ADDRBWRADDRU5" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU6", "BRAM_CASCOUT_ADDRBWRADDRU6" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU7", "BRAM_CASCOUT_ADDRBWRADDRU7" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU8", "BRAM_CASCOUT_ADDRBWRADDRU8" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU9", "BRAM_CASCOUT_ADDRBWRADDRU9" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU10", "BRAM_CASCOUT_ADDRBWRADDRU10" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU11", "BRAM_CASCOUT_ADDRBWRADDRU11" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU12", "BRAM_CASCOUT_ADDRBWRADDRU12" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU13", "BRAM_CASCOUT_ADDRBWRADDRU13" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU14", "BRAM_CASCOUT_ADDRBWRADDRU14" ], [ "BRAM_FIFO36_CASCADEINA", "BRAM_FIFO36_CASCADEOUTA_1" ], [ "BRAM_FIFO36_CASCADEINB", "BRAM_FIFO36_CASCADEOUTB_1" ] ] }, { "grid_deltas": [ 0, -5 ], "tile_types": [ "BRAM_R", "BRKH_BRAM" ], "wire_pairs": [ [ "BRAM_CASCINTOP_ADDRARDADDRU0", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" ], [ "BRAM_CASCINTOP_ADDRARDADDRU1", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" ], [ "BRAM_CASCINTOP_ADDRARDADDRU2", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2" ], [ "BRAM_CASCINTOP_ADDRARDADDRU3", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" ], [ "BRAM_CASCINTOP_ADDRARDADDRU4", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" ], [ "BRAM_CASCINTOP_ADDRARDADDRU5", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" ], [ "BRAM_CASCINTOP_ADDRARDADDRU6", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" ], [ "BRAM_CASCINTOP_ADDRARDADDRU7", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" ], [ "BRAM_CASCINTOP_ADDRARDADDRU8", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" ], [ "BRAM_CASCINTOP_ADDRARDADDRU9", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" ], [ "BRAM_CASCINTOP_ADDRARDADDRU10", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" ], [ "BRAM_CASCINTOP_ADDRARDADDRU11", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" ], [ "BRAM_CASCINTOP_ADDRARDADDRU12", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" ], [ "BRAM_CASCINTOP_ADDRARDADDRU13", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" ], [ "BRAM_CASCINTOP_ADDRARDADDRU14", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU0", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU1", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU2", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU3", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU4", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU5", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU6", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU7", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU8", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU9", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU10", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU11", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU12", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU13", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU14", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ "BRAM_CASCOUT_ADDRARDADDRU0", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ "BRAM_CASCOUT_ADDRARDADDRU1", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" ], [ "BRAM_CASCOUT_ADDRARDADDRU2", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" ], [ "BRAM_CASCOUT_ADDRARDADDRU3", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" ], [ "BRAM_CASCOUT_ADDRARDADDRU4", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" ], [ "BRAM_CASCOUT_ADDRARDADDRU5", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" ], [ "BRAM_CASCOUT_ADDRARDADDRU6", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" ], [ "BRAM_CASCOUT_ADDRARDADDRU7", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" ], [ "BRAM_CASCOUT_ADDRARDADDRU8", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" ], [ "BRAM_CASCOUT_ADDRARDADDRU9", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" ], [ "BRAM_CASCOUT_ADDRARDADDRU10", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10" ], [ "BRAM_CASCOUT_ADDRARDADDRU11", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" ], [ "BRAM_CASCOUT_ADDRARDADDRU12", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" ], [ "BRAM_CASCOUT_ADDRARDADDRU13", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" ], [ "BRAM_CASCOUT_ADDRARDADDRU14", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" ], [ "BRAM_CASCOUT_ADDRBWRADDRU0", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0" ], [ "BRAM_CASCOUT_ADDRBWRADDRU1", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" ], [ "BRAM_CASCOUT_ADDRBWRADDRU2", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" ], [ "BRAM_CASCOUT_ADDRBWRADDRU3", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" ], [ "BRAM_CASCOUT_ADDRBWRADDRU4", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" ], [ "BRAM_CASCOUT_ADDRBWRADDRU5", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" ], [ "BRAM_CASCOUT_ADDRBWRADDRU6", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6" ], [ "BRAM_CASCOUT_ADDRBWRADDRU7", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" ], [ "BRAM_CASCOUT_ADDRBWRADDRU8", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8" ], [ "BRAM_CASCOUT_ADDRBWRADDRU9", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" ], [ "BRAM_CASCOUT_ADDRBWRADDRU10", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" ], [ "BRAM_CASCOUT_ADDRBWRADDRU11", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11" ], [ "BRAM_CASCOUT_ADDRBWRADDRU12", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12" ], [ "BRAM_CASCOUT_ADDRBWRADDRU13", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13" ], [ "BRAM_CASCOUT_ADDRBWRADDRU14", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" ], [ "BRAM_FIFO36_CASCADEOUTA_1", "BRKH_BRAM_CASCADEA_R" ], [ "BRAM_FIFO36_CASCADEOUTB_1", "BRKH_BRAM_CASCADEB_R" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "BRAM_R", "BRKH_BRAM" ], "wire_pairs": [ [ "BRAM_CASCINBOT_ADDRARDADDRU0", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ "BRAM_CASCINBOT_ADDRARDADDRU1", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1" ], [ "BRAM_CASCINBOT_ADDRARDADDRU2", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2" ], [ "BRAM_CASCINBOT_ADDRARDADDRU3", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3" ], [ "BRAM_CASCINBOT_ADDRARDADDRU4", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4" ], [ "BRAM_CASCINBOT_ADDRARDADDRU5", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5" ], [ "BRAM_CASCINBOT_ADDRARDADDRU6", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6" ], [ "BRAM_CASCINBOT_ADDRARDADDRU7", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7" ], [ "BRAM_CASCINBOT_ADDRARDADDRU8", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8" ], [ "BRAM_CASCINBOT_ADDRARDADDRU9", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9" ], [ "BRAM_CASCINBOT_ADDRARDADDRU10", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10" ], [ "BRAM_CASCINBOT_ADDRARDADDRU11", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11" ], [ "BRAM_CASCINBOT_ADDRARDADDRU12", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12" ], [ "BRAM_CASCINBOT_ADDRARDADDRU13", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13" ], [ "BRAM_CASCINBOT_ADDRARDADDRU14", "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU0", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU1", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU2", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU3", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU4", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU5", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU6", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU7", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU8", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU9", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU10", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU11", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU12", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU13", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU14", "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14" ], [ "BRAM_CASCOUT_ADDRARDADDRU0", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0" ], [ "BRAM_CASCOUT_ADDRARDADDRU1", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1" ], [ "BRAM_CASCOUT_ADDRARDADDRU2", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2" ], [ "BRAM_CASCOUT_ADDRARDADDRU3", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3" ], [ "BRAM_CASCOUT_ADDRARDADDRU4", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4" ], [ "BRAM_CASCOUT_ADDRARDADDRU5", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5" ], [ "BRAM_CASCOUT_ADDRARDADDRU6", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6" ], [ "BRAM_CASCOUT_ADDRARDADDRU7", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7" ], [ "BRAM_CASCOUT_ADDRARDADDRU8", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8" ], [ "BRAM_CASCOUT_ADDRARDADDRU9", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9" ], [ "BRAM_CASCOUT_ADDRARDADDRU10", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10" ], [ "BRAM_CASCOUT_ADDRARDADDRU11", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11" ], [ "BRAM_CASCOUT_ADDRARDADDRU12", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12" ], [ "BRAM_CASCOUT_ADDRARDADDRU13", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13" ], [ "BRAM_CASCOUT_ADDRARDADDRU14", "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14" ], [ "BRAM_CASCOUT_ADDRBWRADDRU0", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0" ], [ "BRAM_CASCOUT_ADDRBWRADDRU1", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1" ], [ "BRAM_CASCOUT_ADDRBWRADDRU2", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2" ], [ "BRAM_CASCOUT_ADDRBWRADDRU3", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3" ], [ "BRAM_CASCOUT_ADDRBWRADDRU4", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4" ], [ "BRAM_CASCOUT_ADDRBWRADDRU5", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5" ], [ "BRAM_CASCOUT_ADDRBWRADDRU6", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6" ], [ "BRAM_CASCOUT_ADDRBWRADDRU7", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7" ], [ "BRAM_CASCOUT_ADDRBWRADDRU8", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8" ], [ "BRAM_CASCOUT_ADDRBWRADDRU9", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9" ], [ "BRAM_CASCOUT_ADDRBWRADDRU10", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10" ], [ "BRAM_CASCOUT_ADDRBWRADDRU11", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ "BRAM_CASCOUT_ADDRBWRADDRU12", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12" ], [ "BRAM_CASCOUT_ADDRBWRADDRU13", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13" ], [ "BRAM_CASCOUT_ADDRBWRADDRU14", "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ "BRAM_FIFO36_CASCADEINA", "BRKH_BRAM_CASCADEA_R" ], [ "BRAM_FIFO36_CASCADEINB", "BRKH_BRAM_CASCADEB_R" ] ] }, { "grid_deltas": [ 0, -5 ], "tile_types": [ "BRAM_R", "HCLK_BRAM" ], "wire_pairs": [ [ "BRAM_CASCINTOP_ADDRARDADDRU0", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" ], [ "BRAM_CASCINTOP_ADDRARDADDRU1", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" ], [ "BRAM_CASCINTOP_ADDRARDADDRU2", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" ], [ "BRAM_CASCINTOP_ADDRARDADDRU3", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" ], [ "BRAM_CASCINTOP_ADDRARDADDRU4", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" ], [ "BRAM_CASCINTOP_ADDRARDADDRU5", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" ], [ "BRAM_CASCINTOP_ADDRARDADDRU6", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" ], [ "BRAM_CASCINTOP_ADDRARDADDRU7", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" ], [ "BRAM_CASCINTOP_ADDRARDADDRU8", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" ], [ "BRAM_CASCINTOP_ADDRARDADDRU9", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" ], [ "BRAM_CASCINTOP_ADDRARDADDRU10", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" ], [ "BRAM_CASCINTOP_ADDRARDADDRU11", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" ], [ "BRAM_CASCINTOP_ADDRARDADDRU12", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" ], [ "BRAM_CASCINTOP_ADDRARDADDRU13", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" ], [ "BRAM_CASCINTOP_ADDRARDADDRU14", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU0", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU1", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU2", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU3", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU4", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU5", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU6", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU7", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU8", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU9", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU10", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU11", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU12", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU13", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" ], [ "BRAM_CASCINTOP_ADDRBWRADDRU14", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ "BRAM_CASCOUT_ADDRARDADDRU0", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ "BRAM_CASCOUT_ADDRARDADDRU1", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" ], [ "BRAM_CASCOUT_ADDRARDADDRU2", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" ], [ "BRAM_CASCOUT_ADDRARDADDRU3", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" ], [ "BRAM_CASCOUT_ADDRARDADDRU4", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" ], [ "BRAM_CASCOUT_ADDRARDADDRU5", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" ], [ "BRAM_CASCOUT_ADDRARDADDRU6", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" ], [ "BRAM_CASCOUT_ADDRARDADDRU7", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" ], [ "BRAM_CASCOUT_ADDRARDADDRU8", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" ], [ "BRAM_CASCOUT_ADDRARDADDRU9", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" ], [ "BRAM_CASCOUT_ADDRARDADDRU10", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" ], [ "BRAM_CASCOUT_ADDRARDADDRU11", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" ], [ "BRAM_CASCOUT_ADDRARDADDRU12", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" ], [ "BRAM_CASCOUT_ADDRARDADDRU13", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" ], [ "BRAM_CASCOUT_ADDRARDADDRU14", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" ], [ "BRAM_CASCOUT_ADDRBWRADDRU0", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" ], [ "BRAM_CASCOUT_ADDRBWRADDRU1", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" ], [ "BRAM_CASCOUT_ADDRBWRADDRU2", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" ], [ "BRAM_CASCOUT_ADDRBWRADDRU3", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" ], [ "BRAM_CASCOUT_ADDRBWRADDRU4", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" ], [ "BRAM_CASCOUT_ADDRBWRADDRU5", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" ], [ "BRAM_CASCOUT_ADDRBWRADDRU6", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" ], [ "BRAM_CASCOUT_ADDRBWRADDRU7", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" ], [ "BRAM_CASCOUT_ADDRBWRADDRU8", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" ], [ "BRAM_CASCOUT_ADDRBWRADDRU9", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" ], [ "BRAM_CASCOUT_ADDRBWRADDRU10", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" ], [ "BRAM_CASCOUT_ADDRBWRADDRU11", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" ], [ "BRAM_CASCOUT_ADDRBWRADDRU12", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" ], [ "BRAM_CASCOUT_ADDRBWRADDRU13", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" ], [ "BRAM_CASCOUT_ADDRBWRADDRU14", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" ], [ "BRAM_FIFO36_CASCADEOUTA_1", "HCLK_BRAM_CASCADEA_R" ], [ "BRAM_FIFO36_CASCADEOUTB_1", "HCLK_BRAM_CASCADEB_R" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "BRAM_R", "HCLK_BRAM" ], "wire_pairs": [ [ "BRAM_CASCINBOT_ADDRARDADDRU0", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0" ], [ "BRAM_CASCINBOT_ADDRARDADDRU1", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1" ], [ "BRAM_CASCINBOT_ADDRARDADDRU2", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2" ], [ "BRAM_CASCINBOT_ADDRARDADDRU3", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3" ], [ "BRAM_CASCINBOT_ADDRARDADDRU4", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4" ], [ "BRAM_CASCINBOT_ADDRARDADDRU5", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5" ], [ "BRAM_CASCINBOT_ADDRARDADDRU6", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6" ], [ "BRAM_CASCINBOT_ADDRARDADDRU7", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7" ], [ "BRAM_CASCINBOT_ADDRARDADDRU8", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8" ], [ "BRAM_CASCINBOT_ADDRARDADDRU9", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9" ], [ "BRAM_CASCINBOT_ADDRARDADDRU10", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10" ], [ "BRAM_CASCINBOT_ADDRARDADDRU11", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11" ], [ "BRAM_CASCINBOT_ADDRARDADDRU12", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12" ], [ "BRAM_CASCINBOT_ADDRARDADDRU13", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13" ], [ "BRAM_CASCINBOT_ADDRARDADDRU14", "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU0", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU1", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU2", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU3", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU4", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU5", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU6", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU7", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU8", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU9", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU10", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU11", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU12", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU13", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13" ], [ "BRAM_CASCINBOT_ADDRBWRADDRU14", "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14" ], [ "BRAM_CASCOUT_ADDRARDADDRU0", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0" ], [ "BRAM_CASCOUT_ADDRARDADDRU1", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1" ], [ "BRAM_CASCOUT_ADDRARDADDRU2", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2" ], [ "BRAM_CASCOUT_ADDRARDADDRU3", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3" ], [ "BRAM_CASCOUT_ADDRARDADDRU4", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4" ], [ "BRAM_CASCOUT_ADDRARDADDRU5", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5" ], [ "BRAM_CASCOUT_ADDRARDADDRU6", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6" ], [ "BRAM_CASCOUT_ADDRARDADDRU7", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7" ], [ "BRAM_CASCOUT_ADDRARDADDRU8", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8" ], [ "BRAM_CASCOUT_ADDRARDADDRU9", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9" ], [ "BRAM_CASCOUT_ADDRARDADDRU10", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10" ], [ "BRAM_CASCOUT_ADDRARDADDRU11", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11" ], [ "BRAM_CASCOUT_ADDRARDADDRU12", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12" ], [ "BRAM_CASCOUT_ADDRARDADDRU13", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13" ], [ "BRAM_CASCOUT_ADDRARDADDRU14", "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14" ], [ "BRAM_CASCOUT_ADDRBWRADDRU0", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0" ], [ "BRAM_CASCOUT_ADDRBWRADDRU1", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1" ], [ "BRAM_CASCOUT_ADDRBWRADDRU2", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2" ], [ "BRAM_CASCOUT_ADDRBWRADDRU3", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3" ], [ "BRAM_CASCOUT_ADDRBWRADDRU4", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4" ], [ "BRAM_CASCOUT_ADDRBWRADDRU5", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5" ], [ "BRAM_CASCOUT_ADDRBWRADDRU6", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6" ], [ "BRAM_CASCOUT_ADDRBWRADDRU7", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7" ], [ "BRAM_CASCOUT_ADDRBWRADDRU8", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8" ], [ "BRAM_CASCOUT_ADDRBWRADDRU9", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9" ], [ "BRAM_CASCOUT_ADDRBWRADDRU10", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10" ], [ "BRAM_CASCOUT_ADDRBWRADDRU11", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11" ], [ "BRAM_CASCOUT_ADDRBWRADDRU12", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12" ], [ "BRAM_CASCOUT_ADDRBWRADDRU13", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13" ], [ "BRAM_CASCOUT_ADDRBWRADDRU14", "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14" ], [ "BRAM_FIFO36_CASCADEINA", "HCLK_BRAM_CASCADEA_R" ], [ "BRAM_FIFO36_CASCADEINB", "HCLK_BRAM_CASCADEB_R" ], [ "BRAM_PMVBRAM_O", "HCLK_BRAM_PMVBRAM_O" ], [ "BRAM_PMVBRAM_ODIV2", "HCLK_BRAM_PMVBRAM_ODIV2" ], [ "BRAM_PMVBRAM_ODIV4", "HCLK_BRAM_PMVBRAM_ODIV4" ], [ "BRAM_PMVBRAM_SELECT1", "HCLK_BRAM_PMVBRAM_SELECT1" ], [ "BRAM_PMVBRAM_SELECT2", "HCLK_BRAM_PMVBRAM_SELECT2" ], [ "BRAM_PMVBRAM_SELECT3", "HCLK_BRAM_PMVBRAM_SELECT3" ], [ "BRAM_PMVBRAM_SELECT4", "HCLK_BRAM_PMVBRAM_SELECT4" ] ] }, { "grid_deltas": [ 1, -4 ], "tile_types": [ "BRAM_R", "VBRK" ], "wire_pairs": [ [ "BRAM_EE2A0_4", "VBRK_EE2A0" ], [ "BRAM_EE2A1_4", "VBRK_EE2A1" ], [ "BRAM_EE2A2_4", "VBRK_EE2A2" ], [ "BRAM_EE2A3_4", "VBRK_EE2A3" ], [ "BRAM_EE2BEG0_4", "VBRK_EE2BEG0" ], [ "BRAM_EE2BEG1_4", "VBRK_EE2BEG1" ], [ "BRAM_EE2BEG2_4", "VBRK_EE2BEG2" ], [ "BRAM_EE2BEG3_4", "VBRK_EE2BEG3" ], [ "BRAM_EE4A0_4", "VBRK_EE4A0" ], [ "BRAM_EE4A1_4", "VBRK_EE4A1" ], [ "BRAM_EE4A2_4", "VBRK_EE4A2" ], [ "BRAM_EE4A3_4", "VBRK_EE4A3" ], [ "BRAM_EE4B0_4", "VBRK_EE4B0" ], [ "BRAM_EE4B1_4", "VBRK_EE4B1" ], [ "BRAM_EE4B2_4", "VBRK_EE4B2" ], [ "BRAM_EE4B3_4", "VBRK_EE4B3" ], [ "BRAM_EE4BEG0_4", "VBRK_EE4BEG0" ], [ "BRAM_EE4BEG1_4", "VBRK_EE4BEG1" ], [ "BRAM_EE4BEG2_4", "VBRK_EE4BEG2" ], [ "BRAM_EE4BEG3_4", "VBRK_EE4BEG3" ], [ "BRAM_EE4C0_4", "VBRK_EE4C0" ], [ "BRAM_EE4C1_4", "VBRK_EE4C1" ], [ "BRAM_EE4C2_4", "VBRK_EE4C2" ], [ "BRAM_EE4C3_4", "VBRK_EE4C3" ], [ "BRAM_EL1BEG0_4", "VBRK_EL1BEG0" ], [ "BRAM_EL1BEG1_4", "VBRK_EL1BEG1" ], [ "BRAM_EL1BEG2_4", "VBRK_EL1BEG2" ], [ "BRAM_EL1BEG3_4", "VBRK_EL1BEG3" ], [ "BRAM_ER1BEG0_4", "VBRK_ER1BEG0" ], [ "BRAM_ER1BEG1_4", "VBRK_ER1BEG1" ], [ "BRAM_ER1BEG2_4", "VBRK_ER1BEG2" ], [ "BRAM_ER1BEG3_4", "VBRK_ER1BEG3" ], [ "BRAM_LH1_4", "VBRK_LH1" ], [ "BRAM_LH2_4", "VBRK_LH2" ], [ "BRAM_LH3_4", "VBRK_LH3" ], [ "BRAM_LH4_4", "VBRK_LH4" ], [ "BRAM_LH5_4", "VBRK_LH5" ], [ "BRAM_LH6_4", "VBRK_LH6" ], [ "BRAM_LH7_4", "VBRK_LH7" ], [ "BRAM_LH8_4", "VBRK_LH8" ], [ "BRAM_LH9_4", "VBRK_LH9" ], [ "BRAM_LH10_4", "VBRK_LH10" ], [ "BRAM_LH11_4", "VBRK_LH11" ], [ "BRAM_LH12_4", "VBRK_LH12" ], [ "BRAM_MONITOR_N_4", "VBRK_MONITOR_N" ], [ "BRAM_MONITOR_P_4", "VBRK_MONITOR_P" ], [ "BRAM_NE2A0_4", "VBRK_NE2A0" ], [ "BRAM_NE2A1_4", "VBRK_NE2A1" ], [ "BRAM_NE2A2_4", "VBRK_NE2A2" ], [ "BRAM_NE2A3_4", "VBRK_NE2A3" ], [ "BRAM_NE4BEG0_4", "VBRK_NE4BEG0" ], [ "BRAM_NE4BEG1_4", "VBRK_NE4BEG1" ], [ "BRAM_NE4BEG2_4", "VBRK_NE4BEG2" ], [ "BRAM_NE4BEG3_4", "VBRK_NE4BEG3" ], [ "BRAM_NE4C0_4", "VBRK_NE4C0" ], [ "BRAM_NE4C1_4", "VBRK_NE4C1" ], [ "BRAM_NE4C2_4", "VBRK_NE4C2" ], [ "BRAM_NE4C3_4", "VBRK_NE4C3" ], [ "BRAM_NW2A0_4", "VBRK_NW2A0" ], [ "BRAM_NW2A1_4", "VBRK_NW2A1" ], [ "BRAM_NW2A2_4", "VBRK_NW2A2" ], [ "BRAM_NW2A3_4", "VBRK_NW2A3" ], [ "BRAM_NW4A0_4", "VBRK_NW4A0" ], [ "BRAM_NW4A1_4", "VBRK_NW4A1" ], [ "BRAM_NW4A2_4", "VBRK_NW4A2" ], [ "BRAM_NW4A3_4", "VBRK_NW4A3" ], [ "BRAM_NW4END0_4", "VBRK_NW4END0" ], [ "BRAM_NW4END1_4", "VBRK_NW4END1" ], [ "BRAM_NW4END2_4", "VBRK_NW4END2" ], [ "BRAM_NW4END3_4", "VBRK_NW4END3" ], [ "BRAM_SE2A0_4", "VBRK_SE2A0" ], [ "BRAM_SE2A1_4", "VBRK_SE2A1" ], [ "BRAM_SE2A2_4", "VBRK_SE2A2" ], [ "BRAM_SE2A3_4", "VBRK_SE2A3" ], [ "BRAM_SE4BEG0_4", "VBRK_SE4BEG0" ], [ "BRAM_SE4BEG1_4", "VBRK_SE4BEG1" ], [ "BRAM_SE4BEG2_4", "VBRK_SE4BEG2" ], [ "BRAM_SE4BEG3_4", "VBRK_SE4BEG3" ], [ "BRAM_SE4C0_4", "VBRK_SE4C0" ], [ "BRAM_SE4C1_4", "VBRK_SE4C1" ], [ "BRAM_SE4C2_4", "VBRK_SE4C2" ], [ "BRAM_SE4C3_4", "VBRK_SE4C3" ], [ "BRAM_SW2A0_4", "VBRK_SW2A0" ], [ "BRAM_SW2A1_4", "VBRK_SW2A1" ], [ "BRAM_SW2A2_4", "VBRK_SW2A2" ], [ "BRAM_SW2A3_4", "VBRK_SW2A3" ], [ "BRAM_SW4A0_4", "VBRK_SW4A0" ], [ "BRAM_SW4A1_4", "VBRK_SW4A1" ], [ "BRAM_SW4A2_4", "VBRK_SW4A2" ], [ "BRAM_SW4A3_4", "VBRK_SW4A3" ], [ "BRAM_SW4END0_4", "VBRK_SW4END0" ], [ "BRAM_SW4END1_4", "VBRK_SW4END1" ], [ "BRAM_SW4END2_4", "VBRK_SW4END2" ], [ "BRAM_SW4END3_4", "VBRK_SW4END3" ], [ "BRAM_WL1END0_4", "VBRK_WL1END0" ], [ "BRAM_WL1END1_4", "VBRK_WL1END1" ], [ "BRAM_WL1END2_4", "VBRK_WL1END2" ], [ "BRAM_WL1END3_4", "VBRK_WL1END3" ], [ "BRAM_WR1END0_4", "VBRK_WR1END0" ], [ "BRAM_WR1END1_4", "VBRK_WR1END1" ], [ "BRAM_WR1END2_4", "VBRK_WR1END2" ], [ "BRAM_WR1END3_4", "VBRK_WR1END3" ], [ "BRAM_WW2A0_4", "VBRK_WW2A0" ], [ "BRAM_WW2A1_4", "VBRK_WW2A1" ], [ "BRAM_WW2A2_4", "VBRK_WW2A2" ], [ "BRAM_WW2A3_4", "VBRK_WW2A3" ], [ "BRAM_WW2END0_4", "VBRK_WW2END0" ], [ "BRAM_WW2END1_4", "VBRK_WW2END1" ], [ "BRAM_WW2END2_4", "VBRK_WW2END2" ], [ "BRAM_WW2END3_4", "VBRK_WW2END3" ], [ "BRAM_WW4A0_4", "VBRK_WW4A0" ], [ "BRAM_WW4A1_4", "VBRK_WW4A1" ], [ "BRAM_WW4A2_4", "VBRK_WW4A2" ], [ "BRAM_WW4A3_4", "VBRK_WW4A3" ], [ "BRAM_WW4B0_4", "VBRK_WW4B0" ], [ "BRAM_WW4B1_4", "VBRK_WW4B1" ], [ "BRAM_WW4B2_4", "VBRK_WW4B2" ], [ "BRAM_WW4B3_4", "VBRK_WW4B3" ], [ "BRAM_WW4C0_4", "VBRK_WW4C0" ], [ "BRAM_WW4C1_4", "VBRK_WW4C1" ], [ "BRAM_WW4C2_4", "VBRK_WW4C2" ], [ "BRAM_WW4C3_4", "VBRK_WW4C3" ], [ "BRAM_WW4END0_4", "VBRK_WW4END0" ], [ "BRAM_WW4END1_4", "VBRK_WW4END1" ], [ "BRAM_WW4END2_4", "VBRK_WW4END2" ], [ "BRAM_WW4END3_4", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -3 ], "tile_types": [ "BRAM_R", "VBRK" ], "wire_pairs": [ [ "BRAM_EE2A0_3", "VBRK_EE2A0" ], [ "BRAM_EE2A1_3", "VBRK_EE2A1" ], [ "BRAM_EE2A2_3", "VBRK_EE2A2" ], [ "BRAM_EE2A3_3", "VBRK_EE2A3" ], [ "BRAM_EE2BEG0_3", "VBRK_EE2BEG0" ], [ "BRAM_EE2BEG1_3", "VBRK_EE2BEG1" ], [ "BRAM_EE2BEG2_3", "VBRK_EE2BEG2" ], [ "BRAM_EE2BEG3_3", "VBRK_EE2BEG3" ], [ "BRAM_EE4A0_3", "VBRK_EE4A0" ], [ "BRAM_EE4A1_3", "VBRK_EE4A1" ], [ "BRAM_EE4A2_3", "VBRK_EE4A2" ], [ "BRAM_EE4A3_3", "VBRK_EE4A3" ], [ "BRAM_EE4B0_3", "VBRK_EE4B0" ], [ "BRAM_EE4B1_3", "VBRK_EE4B1" ], [ "BRAM_EE4B2_3", "VBRK_EE4B2" ], [ "BRAM_EE4B3_3", "VBRK_EE4B3" ], [ "BRAM_EE4BEG0_3", "VBRK_EE4BEG0" ], [ "BRAM_EE4BEG1_3", "VBRK_EE4BEG1" ], [ "BRAM_EE4BEG2_3", "VBRK_EE4BEG2" ], [ "BRAM_EE4BEG3_3", "VBRK_EE4BEG3" ], [ "BRAM_EE4C0_3", "VBRK_EE4C0" ], [ "BRAM_EE4C1_3", "VBRK_EE4C1" ], [ "BRAM_EE4C2_3", "VBRK_EE4C2" ], [ "BRAM_EE4C3_3", "VBRK_EE4C3" ], [ "BRAM_EL1BEG0_3", "VBRK_EL1BEG0" ], [ "BRAM_EL1BEG1_3", "VBRK_EL1BEG1" ], [ "BRAM_EL1BEG2_3", "VBRK_EL1BEG2" ], [ "BRAM_EL1BEG3_3", "VBRK_EL1BEG3" ], [ "BRAM_ER1BEG0_3", "VBRK_ER1BEG0" ], [ "BRAM_ER1BEG1_3", "VBRK_ER1BEG1" ], [ "BRAM_ER1BEG2_3", "VBRK_ER1BEG2" ], [ "BRAM_ER1BEG3_3", "VBRK_ER1BEG3" ], [ "BRAM_LH1_3", "VBRK_LH1" ], [ "BRAM_LH2_3", "VBRK_LH2" ], [ "BRAM_LH3_3", "VBRK_LH3" ], [ "BRAM_LH4_3", "VBRK_LH4" ], [ "BRAM_LH5_3", "VBRK_LH5" ], [ "BRAM_LH6_3", "VBRK_LH6" ], [ "BRAM_LH7_3", "VBRK_LH7" ], [ "BRAM_LH8_3", "VBRK_LH8" ], [ "BRAM_LH9_3", "VBRK_LH9" ], [ "BRAM_LH10_3", "VBRK_LH10" ], [ "BRAM_LH11_3", "VBRK_LH11" ], [ "BRAM_LH12_3", "VBRK_LH12" ], [ "BRAM_MONITOR_N_3", "VBRK_MONITOR_N" ], [ "BRAM_MONITOR_P_3", "VBRK_MONITOR_P" ], [ "BRAM_NE2A0_3", "VBRK_NE2A0" ], [ "BRAM_NE2A1_3", "VBRK_NE2A1" ], [ "BRAM_NE2A2_3", "VBRK_NE2A2" ], [ "BRAM_NE2A3_3", "VBRK_NE2A3" ], [ "BRAM_NE4BEG0_3", "VBRK_NE4BEG0" ], [ "BRAM_NE4BEG1_3", "VBRK_NE4BEG1" ], [ "BRAM_NE4BEG2_3", "VBRK_NE4BEG2" ], [ "BRAM_NE4BEG3_3", "VBRK_NE4BEG3" ], [ "BRAM_NE4C0_3", "VBRK_NE4C0" ], [ "BRAM_NE4C1_3", "VBRK_NE4C1" ], [ "BRAM_NE4C2_3", "VBRK_NE4C2" ], [ "BRAM_NE4C3_3", "VBRK_NE4C3" ], [ "BRAM_NW2A0_3", "VBRK_NW2A0" ], [ "BRAM_NW2A1_3", "VBRK_NW2A1" ], [ "BRAM_NW2A2_3", "VBRK_NW2A2" ], [ "BRAM_NW2A3_3", "VBRK_NW2A3" ], [ "BRAM_NW4A0_3", "VBRK_NW4A0" ], [ "BRAM_NW4A1_3", "VBRK_NW4A1" ], [ "BRAM_NW4A2_3", "VBRK_NW4A2" ], [ "BRAM_NW4A3_3", "VBRK_NW4A3" ], [ "BRAM_NW4END0_3", "VBRK_NW4END0" ], [ "BRAM_NW4END1_3", "VBRK_NW4END1" ], [ "BRAM_NW4END2_3", "VBRK_NW4END2" ], [ "BRAM_NW4END3_3", "VBRK_NW4END3" ], [ "BRAM_SE2A0_3", "VBRK_SE2A0" ], [ "BRAM_SE2A1_3", "VBRK_SE2A1" ], [ "BRAM_SE2A2_3", "VBRK_SE2A2" ], [ "BRAM_SE2A3_3", "VBRK_SE2A3" ], [ "BRAM_SE4BEG0_3", "VBRK_SE4BEG0" ], [ "BRAM_SE4BEG1_3", "VBRK_SE4BEG1" ], [ "BRAM_SE4BEG2_3", "VBRK_SE4BEG2" ], [ "BRAM_SE4BEG3_3", "VBRK_SE4BEG3" ], [ "BRAM_SE4C0_3", "VBRK_SE4C0" ], [ "BRAM_SE4C1_3", "VBRK_SE4C1" ], [ "BRAM_SE4C2_3", "VBRK_SE4C2" ], [ "BRAM_SE4C3_3", "VBRK_SE4C3" ], [ "BRAM_SW2A0_3", "VBRK_SW2A0" ], [ "BRAM_SW2A1_3", "VBRK_SW2A1" ], [ "BRAM_SW2A2_3", "VBRK_SW2A2" ], [ "BRAM_SW2A3_3", "VBRK_SW2A3" ], [ "BRAM_SW4A0_3", "VBRK_SW4A0" ], [ "BRAM_SW4A1_3", "VBRK_SW4A1" ], [ "BRAM_SW4A2_3", "VBRK_SW4A2" ], [ "BRAM_SW4A3_3", "VBRK_SW4A3" ], [ "BRAM_SW4END0_3", "VBRK_SW4END0" ], [ "BRAM_SW4END1_3", "VBRK_SW4END1" ], [ "BRAM_SW4END2_3", "VBRK_SW4END2" ], [ "BRAM_SW4END3_3", "VBRK_SW4END3" ], [ "BRAM_WL1END0_3", "VBRK_WL1END0" ], [ "BRAM_WL1END1_3", "VBRK_WL1END1" ], [ "BRAM_WL1END2_3", "VBRK_WL1END2" ], [ "BRAM_WL1END3_3", "VBRK_WL1END3" ], [ "BRAM_WR1END0_3", "VBRK_WR1END0" ], [ "BRAM_WR1END1_3", "VBRK_WR1END1" ], [ "BRAM_WR1END2_3", "VBRK_WR1END2" ], [ "BRAM_WR1END3_3", "VBRK_WR1END3" ], [ "BRAM_WW2A0_3", "VBRK_WW2A0" ], [ "BRAM_WW2A1_3", "VBRK_WW2A1" ], [ "BRAM_WW2A2_3", "VBRK_WW2A2" ], [ "BRAM_WW2A3_3", "VBRK_WW2A3" ], [ "BRAM_WW2END0_3", "VBRK_WW2END0" ], [ "BRAM_WW2END1_3", "VBRK_WW2END1" ], [ "BRAM_WW2END2_3", "VBRK_WW2END2" ], [ "BRAM_WW2END3_3", "VBRK_WW2END3" ], [ "BRAM_WW4A0_3", "VBRK_WW4A0" ], [ "BRAM_WW4A1_3", "VBRK_WW4A1" ], [ "BRAM_WW4A2_3", "VBRK_WW4A2" ], [ "BRAM_WW4A3_3", "VBRK_WW4A3" ], [ "BRAM_WW4B0_3", "VBRK_WW4B0" ], [ "BRAM_WW4B1_3", "VBRK_WW4B1" ], [ "BRAM_WW4B2_3", "VBRK_WW4B2" ], [ "BRAM_WW4B3_3", "VBRK_WW4B3" ], [ "BRAM_WW4C0_3", "VBRK_WW4C0" ], [ "BRAM_WW4C1_3", "VBRK_WW4C1" ], [ "BRAM_WW4C2_3", "VBRK_WW4C2" ], [ "BRAM_WW4C3_3", "VBRK_WW4C3" ], [ "BRAM_WW4END0_3", "VBRK_WW4END0" ], [ "BRAM_WW4END1_3", "VBRK_WW4END1" ], [ "BRAM_WW4END2_3", "VBRK_WW4END2" ], [ "BRAM_WW4END3_3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -2 ], "tile_types": [ "BRAM_R", "VBRK" ], "wire_pairs": [ [ "BRAM_EE2A0_2", "VBRK_EE2A0" ], [ "BRAM_EE2A1_2", "VBRK_EE2A1" ], [ "BRAM_EE2A2_2", "VBRK_EE2A2" ], [ "BRAM_EE2A3_2", "VBRK_EE2A3" ], [ "BRAM_EE2BEG0_2", "VBRK_EE2BEG0" ], [ "BRAM_EE2BEG1_2", "VBRK_EE2BEG1" ], [ "BRAM_EE2BEG2_2", "VBRK_EE2BEG2" ], [ "BRAM_EE2BEG3_2", "VBRK_EE2BEG3" ], [ "BRAM_EE4A0_2", "VBRK_EE4A0" ], [ "BRAM_EE4A1_2", "VBRK_EE4A1" ], [ "BRAM_EE4A2_2", "VBRK_EE4A2" ], [ "BRAM_EE4A3_2", "VBRK_EE4A3" ], [ "BRAM_EE4B0_2", "VBRK_EE4B0" ], [ "BRAM_EE4B1_2", "VBRK_EE4B1" ], [ "BRAM_EE4B2_2", "VBRK_EE4B2" ], [ "BRAM_EE4B3_2", "VBRK_EE4B3" ], [ "BRAM_EE4BEG0_2", "VBRK_EE4BEG0" ], [ "BRAM_EE4BEG1_2", "VBRK_EE4BEG1" ], [ "BRAM_EE4BEG2_2", "VBRK_EE4BEG2" ], [ "BRAM_EE4BEG3_2", "VBRK_EE4BEG3" ], [ "BRAM_EE4C0_2", "VBRK_EE4C0" ], [ "BRAM_EE4C1_2", "VBRK_EE4C1" ], [ "BRAM_EE4C2_2", "VBRK_EE4C2" ], [ "BRAM_EE4C3_2", "VBRK_EE4C3" ], [ "BRAM_EL1BEG0_2", "VBRK_EL1BEG0" ], [ "BRAM_EL1BEG1_2", "VBRK_EL1BEG1" ], [ "BRAM_EL1BEG2_2", "VBRK_EL1BEG2" ], [ "BRAM_EL1BEG3_2", "VBRK_EL1BEG3" ], [ "BRAM_ER1BEG0_2", "VBRK_ER1BEG0" ], [ "BRAM_ER1BEG1_2", "VBRK_ER1BEG1" ], [ "BRAM_ER1BEG2_2", "VBRK_ER1BEG2" ], [ "BRAM_ER1BEG3_2", "VBRK_ER1BEG3" ], [ "BRAM_LH1_2", "VBRK_LH1" ], [ "BRAM_LH2_2", "VBRK_LH2" ], [ "BRAM_LH3_2", "VBRK_LH3" ], [ "BRAM_LH4_2", "VBRK_LH4" ], [ "BRAM_LH5_2", "VBRK_LH5" ], [ "BRAM_LH6_2", "VBRK_LH6" ], [ "BRAM_LH7_2", "VBRK_LH7" ], [ "BRAM_LH8_2", "VBRK_LH8" ], [ "BRAM_LH9_2", "VBRK_LH9" ], [ "BRAM_LH10_2", "VBRK_LH10" ], [ "BRAM_LH11_2", "VBRK_LH11" ], [ "BRAM_LH12_2", "VBRK_LH12" ], [ "BRAM_MONITOR_N_2", "VBRK_MONITOR_N" ], [ "BRAM_MONITOR_P_2", "VBRK_MONITOR_P" ], [ "BRAM_NE2A0_2", "VBRK_NE2A0" ], [ "BRAM_NE2A1_2", "VBRK_NE2A1" ], [ "BRAM_NE2A2_2", "VBRK_NE2A2" ], [ "BRAM_NE2A3_2", "VBRK_NE2A3" ], [ "BRAM_NE4BEG0_2", "VBRK_NE4BEG0" ], [ "BRAM_NE4BEG1_2", "VBRK_NE4BEG1" ], [ "BRAM_NE4BEG2_2", "VBRK_NE4BEG2" ], [ "BRAM_NE4BEG3_2", "VBRK_NE4BEG3" ], [ "BRAM_NE4C0_2", "VBRK_NE4C0" ], [ "BRAM_NE4C1_2", "VBRK_NE4C1" ], [ "BRAM_NE4C2_2", "VBRK_NE4C2" ], [ "BRAM_NE4C3_2", "VBRK_NE4C3" ], [ "BRAM_NW2A0_2", "VBRK_NW2A0" ], [ "BRAM_NW2A1_2", "VBRK_NW2A1" ], [ "BRAM_NW2A2_2", "VBRK_NW2A2" ], [ "BRAM_NW2A3_2", "VBRK_NW2A3" ], [ "BRAM_NW4A0_2", "VBRK_NW4A0" ], [ "BRAM_NW4A1_2", "VBRK_NW4A1" ], [ "BRAM_NW4A2_2", "VBRK_NW4A2" ], [ "BRAM_NW4A3_2", "VBRK_NW4A3" ], [ "BRAM_NW4END0_2", "VBRK_NW4END0" ], [ "BRAM_NW4END1_2", "VBRK_NW4END1" ], [ "BRAM_NW4END2_2", "VBRK_NW4END2" ], [ "BRAM_NW4END3_2", "VBRK_NW4END3" ], [ "BRAM_SE2A0_2", "VBRK_SE2A0" ], [ "BRAM_SE2A1_2", "VBRK_SE2A1" ], [ "BRAM_SE2A2_2", "VBRK_SE2A2" ], [ "BRAM_SE2A3_2", "VBRK_SE2A3" ], [ "BRAM_SE4BEG0_2", "VBRK_SE4BEG0" ], [ "BRAM_SE4BEG1_2", "VBRK_SE4BEG1" ], [ "BRAM_SE4BEG2_2", "VBRK_SE4BEG2" ], [ "BRAM_SE4BEG3_2", "VBRK_SE4BEG3" ], [ "BRAM_SE4C0_2", "VBRK_SE4C0" ], [ "BRAM_SE4C1_2", "VBRK_SE4C1" ], [ "BRAM_SE4C2_2", "VBRK_SE4C2" ], [ "BRAM_SE4C3_2", "VBRK_SE4C3" ], [ "BRAM_SW2A0_2", "VBRK_SW2A0" ], [ "BRAM_SW2A1_2", "VBRK_SW2A1" ], [ "BRAM_SW2A2_2", "VBRK_SW2A2" ], [ "BRAM_SW2A3_2", "VBRK_SW2A3" ], [ "BRAM_SW4A0_2", "VBRK_SW4A0" ], [ "BRAM_SW4A1_2", "VBRK_SW4A1" ], [ "BRAM_SW4A2_2", "VBRK_SW4A2" ], [ "BRAM_SW4A3_2", "VBRK_SW4A3" ], [ "BRAM_SW4END0_2", "VBRK_SW4END0" ], [ "BRAM_SW4END1_2", "VBRK_SW4END1" ], [ "BRAM_SW4END2_2", "VBRK_SW4END2" ], [ "BRAM_SW4END3_2", "VBRK_SW4END3" ], [ "BRAM_WL1END0_2", "VBRK_WL1END0" ], [ "BRAM_WL1END1_2", "VBRK_WL1END1" ], [ "BRAM_WL1END2_2", "VBRK_WL1END2" ], [ "BRAM_WL1END3_2", "VBRK_WL1END3" ], [ "BRAM_WR1END0_2", "VBRK_WR1END0" ], [ "BRAM_WR1END1_2", "VBRK_WR1END1" ], [ "BRAM_WR1END2_2", "VBRK_WR1END2" ], [ "BRAM_WR1END3_2", "VBRK_WR1END3" ], [ "BRAM_WW2A0_2", "VBRK_WW2A0" ], [ "BRAM_WW2A1_2", "VBRK_WW2A1" ], [ "BRAM_WW2A2_2", "VBRK_WW2A2" ], [ "BRAM_WW2A3_2", "VBRK_WW2A3" ], [ "BRAM_WW2END0_2", "VBRK_WW2END0" ], [ "BRAM_WW2END1_2", "VBRK_WW2END1" ], [ "BRAM_WW2END2_2", "VBRK_WW2END2" ], [ "BRAM_WW2END3_2", "VBRK_WW2END3" ], [ "BRAM_WW4A0_2", "VBRK_WW4A0" ], [ "BRAM_WW4A1_2", "VBRK_WW4A1" ], [ "BRAM_WW4A2_2", "VBRK_WW4A2" ], [ "BRAM_WW4A3_2", "VBRK_WW4A3" ], [ "BRAM_WW4B0_2", "VBRK_WW4B0" ], [ "BRAM_WW4B1_2", "VBRK_WW4B1" ], [ "BRAM_WW4B2_2", "VBRK_WW4B2" ], [ "BRAM_WW4B3_2", "VBRK_WW4B3" ], [ "BRAM_WW4C0_2", "VBRK_WW4C0" ], [ "BRAM_WW4C1_2", "VBRK_WW4C1" ], [ "BRAM_WW4C2_2", "VBRK_WW4C2" ], [ "BRAM_WW4C3_2", "VBRK_WW4C3" ], [ "BRAM_WW4END0_2", "VBRK_WW4END0" ], [ "BRAM_WW4END1_2", "VBRK_WW4END1" ], [ "BRAM_WW4END2_2", "VBRK_WW4END2" ], [ "BRAM_WW4END3_2", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -1 ], "tile_types": [ "BRAM_R", "VBRK" ], "wire_pairs": [ [ "BRAM_EE2A0_1", "VBRK_EE2A0" ], [ "BRAM_EE2A1_1", "VBRK_EE2A1" ], [ "BRAM_EE2A2_1", "VBRK_EE2A2" ], [ "BRAM_EE2A3_1", "VBRK_EE2A3" ], [ "BRAM_EE2BEG0_1", "VBRK_EE2BEG0" ], [ "BRAM_EE2BEG1_1", "VBRK_EE2BEG1" ], [ "BRAM_EE2BEG2_1", "VBRK_EE2BEG2" ], [ "BRAM_EE2BEG3_1", "VBRK_EE2BEG3" ], [ "BRAM_EE4A0_1", "VBRK_EE4A0" ], [ "BRAM_EE4A1_1", "VBRK_EE4A1" ], [ "BRAM_EE4A2_1", "VBRK_EE4A2" ], [ "BRAM_EE4A3_1", "VBRK_EE4A3" ], [ "BRAM_EE4B0_1", "VBRK_EE4B0" ], [ "BRAM_EE4B1_1", "VBRK_EE4B1" ], [ "BRAM_EE4B2_1", "VBRK_EE4B2" ], [ "BRAM_EE4B3_1", "VBRK_EE4B3" ], [ "BRAM_EE4BEG0_1", "VBRK_EE4BEG0" ], [ "BRAM_EE4BEG1_1", "VBRK_EE4BEG1" ], [ "BRAM_EE4BEG2_1", "VBRK_EE4BEG2" ], [ "BRAM_EE4BEG3_1", "VBRK_EE4BEG3" ], [ "BRAM_EE4C0_1", "VBRK_EE4C0" ], [ "BRAM_EE4C1_1", "VBRK_EE4C1" ], [ "BRAM_EE4C2_1", "VBRK_EE4C2" ], [ "BRAM_EE4C3_1", "VBRK_EE4C3" ], [ "BRAM_EL1BEG0_1", "VBRK_EL1BEG0" ], [ "BRAM_EL1BEG1_1", "VBRK_EL1BEG1" ], [ "BRAM_EL1BEG2_1", "VBRK_EL1BEG2" ], [ "BRAM_EL1BEG3_1", "VBRK_EL1BEG3" ], [ "BRAM_ER1BEG0_1", "VBRK_ER1BEG0" ], [ "BRAM_ER1BEG1_1", "VBRK_ER1BEG1" ], [ "BRAM_ER1BEG2_1", "VBRK_ER1BEG2" ], [ "BRAM_ER1BEG3_1", "VBRK_ER1BEG3" ], [ "BRAM_LH1_1", "VBRK_LH1" ], [ "BRAM_LH2_1", "VBRK_LH2" ], [ "BRAM_LH3_1", "VBRK_LH3" ], [ "BRAM_LH4_1", "VBRK_LH4" ], [ "BRAM_LH5_1", "VBRK_LH5" ], [ "BRAM_LH6_1", "VBRK_LH6" ], [ "BRAM_LH7_1", "VBRK_LH7" ], [ "BRAM_LH8_1", "VBRK_LH8" ], [ "BRAM_LH9_1", "VBRK_LH9" ], [ "BRAM_LH10_1", "VBRK_LH10" ], [ "BRAM_LH11_1", "VBRK_LH11" ], [ "BRAM_LH12_1", "VBRK_LH12" ], [ "BRAM_MONITOR_N_1", "VBRK_MONITOR_N" ], [ "BRAM_MONITOR_P_1", "VBRK_MONITOR_P" ], [ "BRAM_NE2A0_1", "VBRK_NE2A0" ], [ "BRAM_NE2A1_1", "VBRK_NE2A1" ], [ "BRAM_NE2A2_1", "VBRK_NE2A2" ], [ "BRAM_NE2A3_1", "VBRK_NE2A3" ], [ "BRAM_NE4BEG0_1", "VBRK_NE4BEG0" ], [ "BRAM_NE4BEG1_1", "VBRK_NE4BEG1" ], [ "BRAM_NE4BEG2_1", "VBRK_NE4BEG2" ], [ "BRAM_NE4BEG3_1", "VBRK_NE4BEG3" ], [ "BRAM_NE4C0_1", "VBRK_NE4C0" ], [ "BRAM_NE4C1_1", "VBRK_NE4C1" ], [ "BRAM_NE4C2_1", "VBRK_NE4C2" ], [ "BRAM_NE4C3_1", "VBRK_NE4C3" ], [ "BRAM_NW2A0_1", "VBRK_NW2A0" ], [ "BRAM_NW2A1_1", "VBRK_NW2A1" ], [ "BRAM_NW2A2_1", "VBRK_NW2A2" ], [ "BRAM_NW2A3_1", "VBRK_NW2A3" ], [ "BRAM_NW4A0_1", "VBRK_NW4A0" ], [ "BRAM_NW4A1_1", "VBRK_NW4A1" ], [ "BRAM_NW4A2_1", "VBRK_NW4A2" ], [ "BRAM_NW4A3_1", "VBRK_NW4A3" ], [ "BRAM_NW4END0_1", "VBRK_NW4END0" ], [ "BRAM_NW4END1_1", "VBRK_NW4END1" ], [ "BRAM_NW4END2_1", "VBRK_NW4END2" ], [ "BRAM_NW4END3_1", "VBRK_NW4END3" ], [ "BRAM_SE2A0_1", "VBRK_SE2A0" ], [ "BRAM_SE2A1_1", "VBRK_SE2A1" ], [ "BRAM_SE2A2_1", "VBRK_SE2A2" ], [ "BRAM_SE2A3_1", "VBRK_SE2A3" ], [ "BRAM_SE4BEG0_1", "VBRK_SE4BEG0" ], [ "BRAM_SE4BEG1_1", "VBRK_SE4BEG1" ], [ "BRAM_SE4BEG2_1", "VBRK_SE4BEG2" ], [ "BRAM_SE4BEG3_1", "VBRK_SE4BEG3" ], [ "BRAM_SE4C0_1", "VBRK_SE4C0" ], [ "BRAM_SE4C1_1", "VBRK_SE4C1" ], [ "BRAM_SE4C2_1", "VBRK_SE4C2" ], [ "BRAM_SE4C3_1", "VBRK_SE4C3" ], [ "BRAM_SW2A0_1", "VBRK_SW2A0" ], [ "BRAM_SW2A1_1", "VBRK_SW2A1" ], [ "BRAM_SW2A2_1", "VBRK_SW2A2" ], [ "BRAM_SW2A3_1", "VBRK_SW2A3" ], [ "BRAM_SW4A0_1", "VBRK_SW4A0" ], [ "BRAM_SW4A1_1", "VBRK_SW4A1" ], [ "BRAM_SW4A2_1", "VBRK_SW4A2" ], [ "BRAM_SW4A3_1", "VBRK_SW4A3" ], [ "BRAM_SW4END0_1", "VBRK_SW4END0" ], [ "BRAM_SW4END1_1", "VBRK_SW4END1" ], [ "BRAM_SW4END2_1", "VBRK_SW4END2" ], [ "BRAM_SW4END3_1", "VBRK_SW4END3" ], [ "BRAM_WL1END0_1", "VBRK_WL1END0" ], [ "BRAM_WL1END1_1", "VBRK_WL1END1" ], [ "BRAM_WL1END2_1", "VBRK_WL1END2" ], [ "BRAM_WL1END3_1", "VBRK_WL1END3" ], [ "BRAM_WR1END0_1", "VBRK_WR1END0" ], [ "BRAM_WR1END1_1", "VBRK_WR1END1" ], [ "BRAM_WR1END2_1", "VBRK_WR1END2" ], [ "BRAM_WR1END3_1", "VBRK_WR1END3" ], [ "BRAM_WW2A0_1", "VBRK_WW2A0" ], [ "BRAM_WW2A1_1", "VBRK_WW2A1" ], [ "BRAM_WW2A2_1", "VBRK_WW2A2" ], [ "BRAM_WW2A3_1", "VBRK_WW2A3" ], [ "BRAM_WW2END0_1", "VBRK_WW2END0" ], [ "BRAM_WW2END1_1", "VBRK_WW2END1" ], [ "BRAM_WW2END2_1", "VBRK_WW2END2" ], [ "BRAM_WW2END3_1", "VBRK_WW2END3" ], [ "BRAM_WW4A0_1", "VBRK_WW4A0" ], [ "BRAM_WW4A1_1", "VBRK_WW4A1" ], [ "BRAM_WW4A2_1", "VBRK_WW4A2" ], [ "BRAM_WW4A3_1", "VBRK_WW4A3" ], [ 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"B_TERM_UTURN_INT_WR1END0", "WR1END0" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "BRKH_CLB", "CLBLL_L" ], "wire_pairs": [ [ "BRKH_CLB_COUT0_L", "CLBLL_LL_CIN" ], [ "BRKH_CLB_COUT1_L", "CLBLL_L_CIN" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "BRKH_CLB", "CLBLL_L" ], "wire_pairs": [ [ "BRKH_CLB_COUT0_L", "CLBLL_LL_COUT_N" ], [ "BRKH_CLB_COUT1_L", "CLBLL_L_COUT_N" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "BRKH_CLB", "CLBLL_R" ], "wire_pairs": [ [ "BRKH_CLB_COUT0_R", "CLBLL_L_CIN" ], [ "BRKH_CLB_COUT1_R", "CLBLL_LL_CIN" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "BRKH_CLB", "CLBLL_R" ], "wire_pairs": [ [ "BRKH_CLB_COUT0_R", "CLBLL_L_COUT_N" ], [ "BRKH_CLB_COUT1_R", "CLBLL_LL_COUT_N" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "BRKH_CLB", "CLBLM_L" ], "wire_pairs": [ [ "BRKH_CLB_COUT0_L", "CLBLM_M_CIN" ], [ "BRKH_CLB_COUT1_L", "CLBLM_L_CIN" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "BRKH_CLB", "CLBLM_L" ], "wire_pairs": [ [ "BRKH_CLB_COUT0_L", "CLBLM_M_COUT_N" ], [ "BRKH_CLB_COUT1_L", "CLBLM_L_COUT_N" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "BRKH_CLB", "CLBLM_R" ], "wire_pairs": [ [ "BRKH_CLB_COUT0_R", "CLBLM_L_CIN" ], [ "BRKH_CLB_COUT1_R", "CLBLM_M_CIN" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "BRKH_CLB", "CLBLM_R" ], "wire_pairs": [ [ "BRKH_CLB_COUT0_R", "CLBLM_L_COUT_N" ], [ "BRKH_CLB_COUT1_R", "CLBLM_M_COUT_N" ] ] }, { "grid_deltas": [ 0, 4 ], "tile_types": [ "BRKH_CLK", "CLK_BUFG_BOT_R" ], "wire_pairs": [ [ "BRKH_CLK_R_CK_GCLK0", "CLK_BUFG_CK_GCLK0" ], [ "BRKH_CLK_R_CK_GCLK1", "CLK_BUFG_CK_GCLK1" ], [ "BRKH_CLK_R_CK_GCLK2", "CLK_BUFG_CK_GCLK2" ], [ "BRKH_CLK_R_CK_GCLK3", "CLK_BUFG_CK_GCLK3" ], [ "BRKH_CLK_R_CK_GCLK4", "CLK_BUFG_CK_GCLK4" ], [ "BRKH_CLK_R_CK_GCLK5", "CLK_BUFG_CK_GCLK5" ], [ "BRKH_CLK_R_CK_GCLK6", "CLK_BUFG_CK_GCLK6" ], [ "BRKH_CLK_R_CK_GCLK7", "CLK_BUFG_CK_GCLK7" ], [ "BRKH_CLK_R_CK_GCLK8", "CLK_BUFG_CK_GCLK8" ], [ "BRKH_CLK_R_CK_GCLK9", "CLK_BUFG_CK_GCLK9" ], [ "BRKH_CLK_R_CK_GCLK10", "CLK_BUFG_CK_GCLK10" ], [ "BRKH_CLK_R_CK_GCLK11", "CLK_BUFG_CK_GCLK11" ], [ "BRKH_CLK_R_CK_GCLK12", "CLK_BUFG_CK_GCLK12" ], [ "BRKH_CLK_R_CK_GCLK13", "CLK_BUFG_CK_GCLK13" ], [ "BRKH_CLK_R_CK_GCLK14", "CLK_BUFG_CK_GCLK14" ], [ "BRKH_CLK_R_CK_GCLK15", "CLK_BUFG_CK_GCLK15" ], [ "BRKH_CLK_R_CK_GCLK16", "CLK_BUFG_CK_GCLK16" ], [ "BRKH_CLK_R_CK_GCLK17", "CLK_BUFG_CK_GCLK17" ], [ "BRKH_CLK_R_CK_GCLK18", "CLK_BUFG_CK_GCLK18" ], [ "BRKH_CLK_R_CK_GCLK19", "CLK_BUFG_CK_GCLK19" ], [ "BRKH_CLK_R_CK_GCLK20", "CLK_BUFG_CK_GCLK20" ], [ "BRKH_CLK_R_CK_GCLK21", "CLK_BUFG_CK_GCLK21" ], [ "BRKH_CLK_R_CK_GCLK22", "CLK_BUFG_CK_GCLK22" ], [ "BRKH_CLK_R_CK_GCLK23", "CLK_BUFG_CK_GCLK23" ], [ "BRKH_CLK_R_CK_GCLK24", "CLK_BUFG_CK_GCLK24" ], [ "BRKH_CLK_R_CK_GCLK25", "CLK_BUFG_CK_GCLK25" ], [ "BRKH_CLK_R_CK_GCLK26", "CLK_BUFG_CK_GCLK26" ], [ "BRKH_CLK_R_CK_GCLK27", "CLK_BUFG_CK_GCLK27" ], [ "BRKH_CLK_R_CK_GCLK28", "CLK_BUFG_CK_GCLK28" ], [ "BRKH_CLK_R_CK_GCLK29", "CLK_BUFG_CK_GCLK29" ], [ "BRKH_CLK_R_CK_GCLK30", "CLK_BUFG_CK_GCLK30" ], [ "BRKH_CLK_R_CK_GCLK31", "CLK_BUFG_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "BRKH_CLK", "CLK_BUFG_TOP_R" ], "wire_pairs": [ [ "BRKH_CLK_R_CK_GCLK0", "CLK_BUFG_CK_GCLK0" ], [ "BRKH_CLK_R_CK_GCLK1", "CLK_BUFG_CK_GCLK1" ], [ "BRKH_CLK_R_CK_GCLK2", "CLK_BUFG_CK_GCLK2" ], [ "BRKH_CLK_R_CK_GCLK3", "CLK_BUFG_CK_GCLK3" ], [ "BRKH_CLK_R_CK_GCLK4", "CLK_BUFG_CK_GCLK4" ], [ "BRKH_CLK_R_CK_GCLK5", "CLK_BUFG_CK_GCLK5" ], [ "BRKH_CLK_R_CK_GCLK6", "CLK_BUFG_CK_GCLK6" ], [ "BRKH_CLK_R_CK_GCLK7", "CLK_BUFG_CK_GCLK7" ], [ "BRKH_CLK_R_CK_GCLK8", "CLK_BUFG_CK_GCLK8" ], [ "BRKH_CLK_R_CK_GCLK9", "CLK_BUFG_CK_GCLK9" ], [ "BRKH_CLK_R_CK_GCLK10", "CLK_BUFG_CK_GCLK10" ], [ "BRKH_CLK_R_CK_GCLK11", "CLK_BUFG_CK_GCLK11" ], [ "BRKH_CLK_R_CK_GCLK12", "CLK_BUFG_CK_GCLK12" ], [ "BRKH_CLK_R_CK_GCLK13", "CLK_BUFG_CK_GCLK13" ], [ "BRKH_CLK_R_CK_GCLK14", "CLK_BUFG_CK_GCLK14" ], [ "BRKH_CLK_R_CK_GCLK15", "CLK_BUFG_CK_GCLK15" ], [ "BRKH_CLK_R_CK_GCLK16", "CLK_BUFG_CK_GCLK16" ], [ "BRKH_CLK_R_CK_GCLK17", "CLK_BUFG_CK_GCLK17" ], [ "BRKH_CLK_R_CK_GCLK18", "CLK_BUFG_CK_GCLK18" ], [ "BRKH_CLK_R_CK_GCLK19", "CLK_BUFG_CK_GCLK19" ], [ "BRKH_CLK_R_CK_GCLK20", "CLK_BUFG_CK_GCLK20" ], [ "BRKH_CLK_R_CK_GCLK21", "CLK_BUFG_CK_GCLK21" ], [ "BRKH_CLK_R_CK_GCLK22", "CLK_BUFG_CK_GCLK22" ], [ "BRKH_CLK_R_CK_GCLK23", "CLK_BUFG_CK_GCLK23" ], [ "BRKH_CLK_R_CK_GCLK24", "CLK_BUFG_CK_GCLK24" ], [ "BRKH_CLK_R_CK_GCLK25", "CLK_BUFG_CK_GCLK25" ], [ "BRKH_CLK_R_CK_GCLK26", "CLK_BUFG_CK_GCLK26" ], [ "BRKH_CLK_R_CK_GCLK27", "CLK_BUFG_CK_GCLK27" ], [ "BRKH_CLK_R_CK_GCLK28", "CLK_BUFG_CK_GCLK28" ], [ "BRKH_CLK_R_CK_GCLK29", "CLK_BUFG_CK_GCLK29" ], [ "BRKH_CLK_R_CK_GCLK30", "CLK_BUFG_CK_GCLK30" ], [ "BRKH_CLK_R_CK_GCLK31", "CLK_BUFG_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "BRKH_CLK", "CLK_FEED" ], "wire_pairs": [ [ "BRKH_CLK_R_CK_BUFG_CASC0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ "BRKH_CLK_R_CK_BUFG_CASC1", "CLK_FEED_R_CK_BUFG_CASC1" ], [ "BRKH_CLK_R_CK_BUFG_CASC2", "CLK_FEED_R_CK_BUFG_CASC2" ], [ "BRKH_CLK_R_CK_BUFG_CASC3", "CLK_FEED_R_CK_BUFG_CASC3" ], [ "BRKH_CLK_R_CK_BUFG_CASC4", "CLK_FEED_R_CK_BUFG_CASC4" ], [ "BRKH_CLK_R_CK_BUFG_CASC5", "CLK_FEED_R_CK_BUFG_CASC5" ], [ "BRKH_CLK_R_CK_BUFG_CASC6", "CLK_FEED_R_CK_BUFG_CASC6" ], [ "BRKH_CLK_R_CK_BUFG_CASC7", "CLK_FEED_R_CK_BUFG_CASC7" ], [ "BRKH_CLK_R_CK_BUFG_CASC8", "CLK_FEED_R_CK_BUFG_CASC8" ], [ "BRKH_CLK_R_CK_BUFG_CASC9", "CLK_FEED_R_CK_BUFG_CASC9" ], [ "BRKH_CLK_R_CK_BUFG_CASC10", "CLK_FEED_R_CK_BUFG_CASC10" ], [ "BRKH_CLK_R_CK_BUFG_CASC11", "CLK_FEED_R_CK_BUFG_CASC11" ], [ "BRKH_CLK_R_CK_BUFG_CASC12", "CLK_FEED_R_CK_BUFG_CASC12" ], [ "BRKH_CLK_R_CK_BUFG_CASC13", "CLK_FEED_R_CK_BUFG_CASC13" ], [ "BRKH_CLK_R_CK_BUFG_CASC14", "CLK_FEED_R_CK_BUFG_CASC14" ], [ "BRKH_CLK_R_CK_BUFG_CASC15", "CLK_FEED_R_CK_BUFG_CASC15" ], [ "BRKH_CLK_R_CK_BUFG_CASC16", "CLK_FEED_R_CK_BUFG_CASC16" ], [ "BRKH_CLK_R_CK_BUFG_CASC17", "CLK_FEED_R_CK_BUFG_CASC17" ], [ "BRKH_CLK_R_CK_BUFG_CASC18", "CLK_FEED_R_CK_BUFG_CASC18" ], [ "BRKH_CLK_R_CK_BUFG_CASC19", "CLK_FEED_R_CK_BUFG_CASC19" ], [ "BRKH_CLK_R_CK_BUFG_CASC20", "CLK_FEED_R_CK_BUFG_CASC20" ], [ "BRKH_CLK_R_CK_BUFG_CASC21", "CLK_FEED_R_CK_BUFG_CASC21" ], [ "BRKH_CLK_R_CK_BUFG_CASC22", "CLK_FEED_R_CK_BUFG_CASC22" ], [ "BRKH_CLK_R_CK_BUFG_CASC23", "CLK_FEED_R_CK_BUFG_CASC23" ], [ "BRKH_CLK_R_CK_BUFG_CASC24", "CLK_FEED_R_CK_BUFG_CASC24" ], [ "BRKH_CLK_R_CK_BUFG_CASC25", "CLK_FEED_R_CK_BUFG_CASC25" ], [ "BRKH_CLK_R_CK_BUFG_CASC26", "CLK_FEED_R_CK_BUFG_CASC26" ], [ "BRKH_CLK_R_CK_BUFG_CASC27", "CLK_FEED_R_CK_BUFG_CASC27" ], [ "BRKH_CLK_R_CK_BUFG_CASC28", "CLK_FEED_R_CK_BUFG_CASC28" ], [ "BRKH_CLK_R_CK_BUFG_CASC29", "CLK_FEED_R_CK_BUFG_CASC29" ], [ "BRKH_CLK_R_CK_BUFG_CASC30", "CLK_FEED_R_CK_BUFG_CASC30" ], [ "BRKH_CLK_R_CK_BUFG_CASC31", "CLK_FEED_R_CK_BUFG_CASC31" ], [ "BRKH_CLK_R_CK_GCLK0", "CLK_FEED_R_CK_GCLK0" ], [ "BRKH_CLK_R_CK_GCLK1", "CLK_FEED_R_CK_GCLK1" ], [ "BRKH_CLK_R_CK_GCLK2", "CLK_FEED_R_CK_GCLK2" ], [ "BRKH_CLK_R_CK_GCLK3", "CLK_FEED_R_CK_GCLK3" ], [ "BRKH_CLK_R_CK_GCLK4", "CLK_FEED_R_CK_GCLK4" ], [ "BRKH_CLK_R_CK_GCLK5", "CLK_FEED_R_CK_GCLK5" ], [ "BRKH_CLK_R_CK_GCLK6", "CLK_FEED_R_CK_GCLK6" ], [ "BRKH_CLK_R_CK_GCLK7", "CLK_FEED_R_CK_GCLK7" ], [ "BRKH_CLK_R_CK_GCLK8", "CLK_FEED_R_CK_GCLK8" ], [ "BRKH_CLK_R_CK_GCLK9", "CLK_FEED_R_CK_GCLK9" ], [ "BRKH_CLK_R_CK_GCLK10", "CLK_FEED_R_CK_GCLK10" ], [ "BRKH_CLK_R_CK_GCLK11", "CLK_FEED_R_CK_GCLK11" ], [ "BRKH_CLK_R_CK_GCLK12", "CLK_FEED_R_CK_GCLK12" ], [ "BRKH_CLK_R_CK_GCLK13", "CLK_FEED_R_CK_GCLK13" ], [ "BRKH_CLK_R_CK_GCLK14", "CLK_FEED_R_CK_GCLK14" ], [ "BRKH_CLK_R_CK_GCLK15", "CLK_FEED_R_CK_GCLK15" ], [ "BRKH_CLK_R_CK_GCLK16", "CLK_FEED_R_CK_GCLK16" ], [ "BRKH_CLK_R_CK_GCLK17", "CLK_FEED_R_CK_GCLK17" ], [ "BRKH_CLK_R_CK_GCLK18", "CLK_FEED_R_CK_GCLK18" ], [ "BRKH_CLK_R_CK_GCLK19", "CLK_FEED_R_CK_GCLK19" ], [ "BRKH_CLK_R_CK_GCLK20", "CLK_FEED_R_CK_GCLK20" ], [ "BRKH_CLK_R_CK_GCLK21", "CLK_FEED_R_CK_GCLK21" ], [ "BRKH_CLK_R_CK_GCLK22", "CLK_FEED_R_CK_GCLK22" ], [ "BRKH_CLK_R_CK_GCLK23", "CLK_FEED_R_CK_GCLK23" ], [ "BRKH_CLK_R_CK_GCLK24", "CLK_FEED_R_CK_GCLK24" ], [ "BRKH_CLK_R_CK_GCLK25", "CLK_FEED_R_CK_GCLK25" ], [ "BRKH_CLK_R_CK_GCLK26", "CLK_FEED_R_CK_GCLK26" ], [ "BRKH_CLK_R_CK_GCLK27", "CLK_FEED_R_CK_GCLK27" ], [ "BRKH_CLK_R_CK_GCLK28", "CLK_FEED_R_CK_GCLK28" ], [ "BRKH_CLK_R_CK_GCLK29", "CLK_FEED_R_CK_GCLK29" ], [ "BRKH_CLK_R_CK_GCLK30", "CLK_FEED_R_CK_GCLK30" ], [ "BRKH_CLK_R_CK_GCLK31", "CLK_FEED_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "BRKH_CLK", "CLK_FEED" ], "wire_pairs": [ [ "BRKH_CLK_R_CK_BUFG_CASC0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ "BRKH_CLK_R_CK_BUFG_CASC1", "CLK_FEED_R_CK_BUFG_CASC1" ], [ "BRKH_CLK_R_CK_BUFG_CASC2", "CLK_FEED_R_CK_BUFG_CASC2" ], [ "BRKH_CLK_R_CK_BUFG_CASC3", "CLK_FEED_R_CK_BUFG_CASC3" ], [ "BRKH_CLK_R_CK_BUFG_CASC4", "CLK_FEED_R_CK_BUFG_CASC4" ], [ "BRKH_CLK_R_CK_BUFG_CASC5", "CLK_FEED_R_CK_BUFG_CASC5" ], [ "BRKH_CLK_R_CK_BUFG_CASC6", "CLK_FEED_R_CK_BUFG_CASC6" ], [ "BRKH_CLK_R_CK_BUFG_CASC7", "CLK_FEED_R_CK_BUFG_CASC7" ], [ "BRKH_CLK_R_CK_BUFG_CASC8", "CLK_FEED_R_CK_BUFG_CASC8" ], [ "BRKH_CLK_R_CK_BUFG_CASC9", "CLK_FEED_R_CK_BUFG_CASC9" ], [ "BRKH_CLK_R_CK_BUFG_CASC10", "CLK_FEED_R_CK_BUFG_CASC10" ], [ "BRKH_CLK_R_CK_BUFG_CASC11", "CLK_FEED_R_CK_BUFG_CASC11" ], [ "BRKH_CLK_R_CK_BUFG_CASC12", "CLK_FEED_R_CK_BUFG_CASC12" ], [ "BRKH_CLK_R_CK_BUFG_CASC13", "CLK_FEED_R_CK_BUFG_CASC13" ], [ "BRKH_CLK_R_CK_BUFG_CASC14", "CLK_FEED_R_CK_BUFG_CASC14" ], [ "BRKH_CLK_R_CK_BUFG_CASC15", "CLK_FEED_R_CK_BUFG_CASC15" ], [ "BRKH_CLK_R_CK_BUFG_CASC16", "CLK_FEED_R_CK_BUFG_CASC16" ], [ "BRKH_CLK_R_CK_BUFG_CASC17", "CLK_FEED_R_CK_BUFG_CASC17" ], [ "BRKH_CLK_R_CK_BUFG_CASC18", "CLK_FEED_R_CK_BUFG_CASC18" ], [ "BRKH_CLK_R_CK_BUFG_CASC19", "CLK_FEED_R_CK_BUFG_CASC19" ], [ "BRKH_CLK_R_CK_BUFG_CASC20", "CLK_FEED_R_CK_BUFG_CASC20" ], [ "BRKH_CLK_R_CK_BUFG_CASC21", "CLK_FEED_R_CK_BUFG_CASC21" ], [ "BRKH_CLK_R_CK_BUFG_CASC22", "CLK_FEED_R_CK_BUFG_CASC22" ], [ "BRKH_CLK_R_CK_BUFG_CASC23", "CLK_FEED_R_CK_BUFG_CASC23" ], [ "BRKH_CLK_R_CK_BUFG_CASC24", "CLK_FEED_R_CK_BUFG_CASC24" ], [ "BRKH_CLK_R_CK_BUFG_CASC25", "CLK_FEED_R_CK_BUFG_CASC25" ], [ "BRKH_CLK_R_CK_BUFG_CASC26", "CLK_FEED_R_CK_BUFG_CASC26" ], [ "BRKH_CLK_R_CK_BUFG_CASC27", "CLK_FEED_R_CK_BUFG_CASC27" ], [ "BRKH_CLK_R_CK_BUFG_CASC28", "CLK_FEED_R_CK_BUFG_CASC28" ], [ "BRKH_CLK_R_CK_BUFG_CASC29", "CLK_FEED_R_CK_BUFG_CASC29" ], [ "BRKH_CLK_R_CK_BUFG_CASC30", "CLK_FEED_R_CK_BUFG_CASC30" ], [ "BRKH_CLK_R_CK_BUFG_CASC31", "CLK_FEED_R_CK_BUFG_CASC31" ], [ "BRKH_CLK_R_CK_GCLK0", "CLK_FEED_R_CK_GCLK0" ], [ "BRKH_CLK_R_CK_GCLK1", "CLK_FEED_R_CK_GCLK1" ], [ "BRKH_CLK_R_CK_GCLK2", "CLK_FEED_R_CK_GCLK2" ], [ "BRKH_CLK_R_CK_GCLK3", "CLK_FEED_R_CK_GCLK3" ], [ "BRKH_CLK_R_CK_GCLK4", "CLK_FEED_R_CK_GCLK4" ], [ "BRKH_CLK_R_CK_GCLK5", "CLK_FEED_R_CK_GCLK5" ], [ "BRKH_CLK_R_CK_GCLK6", "CLK_FEED_R_CK_GCLK6" ], [ "BRKH_CLK_R_CK_GCLK7", "CLK_FEED_R_CK_GCLK7" ], [ "BRKH_CLK_R_CK_GCLK8", "CLK_FEED_R_CK_GCLK8" ], [ "BRKH_CLK_R_CK_GCLK9", "CLK_FEED_R_CK_GCLK9" ], [ "BRKH_CLK_R_CK_GCLK10", "CLK_FEED_R_CK_GCLK10" ], [ "BRKH_CLK_R_CK_GCLK11", "CLK_FEED_R_CK_GCLK11" ], [ "BRKH_CLK_R_CK_GCLK12", "CLK_FEED_R_CK_GCLK12" ], [ "BRKH_CLK_R_CK_GCLK13", "CLK_FEED_R_CK_GCLK13" ], [ "BRKH_CLK_R_CK_GCLK14", "CLK_FEED_R_CK_GCLK14" ], [ "BRKH_CLK_R_CK_GCLK15", "CLK_FEED_R_CK_GCLK15" ], [ "BRKH_CLK_R_CK_GCLK16", "CLK_FEED_R_CK_GCLK16" ], [ "BRKH_CLK_R_CK_GCLK17", "CLK_FEED_R_CK_GCLK17" ], [ "BRKH_CLK_R_CK_GCLK18", "CLK_FEED_R_CK_GCLK18" ], [ "BRKH_CLK_R_CK_GCLK19", "CLK_FEED_R_CK_GCLK19" ], [ "BRKH_CLK_R_CK_GCLK20", "CLK_FEED_R_CK_GCLK20" ], [ "BRKH_CLK_R_CK_GCLK21", "CLK_FEED_R_CK_GCLK21" ], [ "BRKH_CLK_R_CK_GCLK22", "CLK_FEED_R_CK_GCLK22" ], [ "BRKH_CLK_R_CK_GCLK23", "CLK_FEED_R_CK_GCLK23" ], [ "BRKH_CLK_R_CK_GCLK24", "CLK_FEED_R_CK_GCLK24" ], [ "BRKH_CLK_R_CK_GCLK25", "CLK_FEED_R_CK_GCLK25" ], [ "BRKH_CLK_R_CK_GCLK26", "CLK_FEED_R_CK_GCLK26" ], [ "BRKH_CLK_R_CK_GCLK27", "CLK_FEED_R_CK_GCLK27" ], [ "BRKH_CLK_R_CK_GCLK28", "CLK_FEED_R_CK_GCLK28" ], [ "BRKH_CLK_R_CK_GCLK29", "CLK_FEED_R_CK_GCLK29" ], [ "BRKH_CLK_R_CK_GCLK30", "CLK_FEED_R_CK_GCLK30" ], [ "BRKH_CLK_R_CK_GCLK31", "CLK_FEED_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, -9 ], "tile_types": [ "BRKH_CMT", "CMT_TOP_L_LOWER_B" ], "wire_pairs": [ [ "BRKH_CMT_FREQ_REF_NS0", "MMCM_CLK_FREQ_BB_REBUF0_NS" ], [ "BRKH_CMT_FREQ_REF_NS1", "MMCM_CLK_FREQ_BB_REBUF1_NS" ], [ "BRKH_CMT_FREQ_REF_NS2", "MMCM_CLK_FREQ_BB_REBUF2_NS" ], [ "BRKH_CMT_FREQ_REF_NS3", "MMCM_CLK_FREQ_BB_REBUF3_NS" ], [ "BRKH_CMT_PHASEREF0", "CMT_MMCM_PHASERREF0" ], [ "BRKH_CMT_PHASEREF1", "CMT_MMCM_PHASERREF1" ], [ "BRKH_CMT_PHASEREF_BELOW0", "CMT_MMCM_PHASERREF_BELOW0" ], [ "BRKH_CMT_PHASEREF_BELOW1", "CMT_MMCM_PHASERREF_BELOW1" ], [ "BRKH_CMT_PHYCTRL_SYNC_BB", "CMT_MMCM_PHYCTRL_SYNC_BB_DN" ] ] }, { "grid_deltas": [ 0, 8 ], "tile_types": [ "BRKH_CMT", "CMT_TOP_L_UPPER_T" ], "wire_pairs": [ [ "BRKH_CMT_FREQ_REF_NS0", "PLL_CLK_FREQ_BB_BUFOUT_NS0" ], [ "BRKH_CMT_FREQ_REF_NS1", "PLL_CLK_FREQ_BB_BUFOUT_NS1" ], [ "BRKH_CMT_FREQ_REF_NS2", "PLL_CLK_FREQ_BB_BUFOUT_NS2" ], [ "BRKH_CMT_FREQ_REF_NS3", "PLL_CLK_FREQ_BB_BUFOUT_NS3" ], [ "BRKH_CMT_PHASEREF0", "CMT_PLL_PHASERREF_ABOVE0" ], [ "BRKH_CMT_PHASEREF1", "CMT_PLL_PHASERREF_ABOVE1" ], [ "BRKH_CMT_PHASEREF_BELOW0", "CMT_PLL_PHASERREF0" ], [ "BRKH_CMT_PHASEREF_BELOW1", "CMT_PLL_PHASERREF1" ], [ "BRKH_CMT_PHYCTRL_SYNC_BB", "CMT_PLL_PHYCTRL_SYNC_BB_UP" ] ] }, { "grid_deltas": [ 0, -9 ], "tile_types": [ "BRKH_CMT", "CMT_TOP_R_LOWER_B" ], "wire_pairs": [ [ "BRKH_CMT_FREQ_REF_NS0", "MMCM_CLK_FREQ_BB_REBUF0_NS" ], [ "BRKH_CMT_FREQ_REF_NS1", "MMCM_CLK_FREQ_BB_REBUF1_NS" ], [ "BRKH_CMT_FREQ_REF_NS2", "MMCM_CLK_FREQ_BB_REBUF2_NS" ], [ "BRKH_CMT_FREQ_REF_NS3", "MMCM_CLK_FREQ_BB_REBUF3_NS" ], [ "BRKH_CMT_PHASEREF0", "CMT_MMCM_PHASERREF0" ], [ "BRKH_CMT_PHASEREF1", "CMT_MMCM_PHASERREF1" ], [ "BRKH_CMT_PHASEREF_BELOW0", "CMT_MMCM_PHASERREF_BELOW0" ], [ "BRKH_CMT_PHASEREF_BELOW1", "CMT_MMCM_PHASERREF_BELOW1" ], [ "BRKH_CMT_PHYCTRL_SYNC_BB", "CMT_MMCM_PHYCTRL_SYNC_BB_DN" ] ] }, { "grid_deltas": [ 0, 8 ], "tile_types": [ "BRKH_CMT", "CMT_TOP_R_UPPER_T" ], "wire_pairs": [ [ "BRKH_CMT_FREQ_REF_NS0", "PLL_CLK_FREQ_BB_BUFOUT_NS0" ], [ "BRKH_CMT_FREQ_REF_NS1", "PLL_CLK_FREQ_BB_BUFOUT_NS1" ], [ "BRKH_CMT_FREQ_REF_NS2", "PLL_CLK_FREQ_BB_BUFOUT_NS2" ], [ "BRKH_CMT_FREQ_REF_NS3", "PLL_CLK_FREQ_BB_BUFOUT_NS3" ], [ "BRKH_CMT_PHASEREF0", "CMT_PLL_PHASERREF_ABOVE0" ], [ "BRKH_CMT_PHASEREF1", "CMT_PLL_PHASERREF_ABOVE1" ], [ "BRKH_CMT_PHASEREF_BELOW0", "CMT_PLL_PHASERREF0" ], [ "BRKH_CMT_PHASEREF_BELOW1", "CMT_PLL_PHASERREF1" ], [ "BRKH_CMT_PHYCTRL_SYNC_BB", "CMT_PLL_PHYCTRL_SYNC_BB_UP" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "BRKH_DSP_L", "DSP_L" ], "wire_pairs": [ [ "BRKH_DSP_ACIN0", "DSP_0_ACIN0" ], [ "BRKH_DSP_ACIN1", "DSP_0_ACIN1" ], [ "BRKH_DSP_ACIN2", "DSP_0_ACIN2" ], [ "BRKH_DSP_ACIN3", "DSP_0_ACIN3" ], [ "BRKH_DSP_ACIN4", "DSP_0_ACIN4" ], [ "BRKH_DSP_ACIN5", "DSP_0_ACIN5" ], [ "BRKH_DSP_ACIN6", "DSP_0_ACIN6" ], [ "BRKH_DSP_ACIN7", "DSP_0_ACIN7" ], [ "BRKH_DSP_ACIN8", "DSP_0_ACIN8" ], [ "BRKH_DSP_ACIN9", "DSP_0_ACIN9" ], [ "BRKH_DSP_ACIN10", "DSP_0_ACIN10" ], [ "BRKH_DSP_ACIN11", "DSP_0_ACIN11" ], [ "BRKH_DSP_ACIN12", "DSP_0_ACIN12" ], [ "BRKH_DSP_ACIN13", "DSP_0_ACIN13" ], [ "BRKH_DSP_ACIN14", "DSP_0_ACIN14" ], [ "BRKH_DSP_ACIN15", "DSP_0_ACIN15" ], [ "BRKH_DSP_ACIN16", "DSP_0_ACIN16" ], [ "BRKH_DSP_ACIN17", "DSP_0_ACIN17" ], [ "BRKH_DSP_ACIN18", "DSP_0_ACIN18" ], [ "BRKH_DSP_ACIN19", "DSP_0_ACIN19" ], [ "BRKH_DSP_ACIN20", "DSP_0_ACIN20" ], [ "BRKH_DSP_ACIN21", "DSP_0_ACIN21" ], [ "BRKH_DSP_ACIN22", "DSP_0_ACIN22" ], [ "BRKH_DSP_ACIN23", "DSP_0_ACIN23" ], [ "BRKH_DSP_ACIN24", "DSP_0_ACIN24" ], [ "BRKH_DSP_ACIN25", "DSP_0_ACIN25" ], [ "BRKH_DSP_ACIN26", "DSP_0_ACIN26" ], [ "BRKH_DSP_ACIN27", "DSP_0_ACIN27" ], [ "BRKH_DSP_ACIN28", "DSP_0_ACIN28" ], [ "BRKH_DSP_ACIN29", "DSP_0_ACIN29" ], [ "BRKH_DSP_BCIN0", "DSP_0_BCIN0" ], [ "BRKH_DSP_BCIN1", "DSP_0_BCIN1" ], [ "BRKH_DSP_BCIN2", "DSP_0_BCIN2" ], [ "BRKH_DSP_BCIN3", "DSP_0_BCIN3" ], [ "BRKH_DSP_BCIN4", "DSP_0_BCIN4" ], [ "BRKH_DSP_BCIN5", "DSP_0_BCIN5" ], [ "BRKH_DSP_BCIN6", "DSP_0_BCIN6" ], [ "BRKH_DSP_BCIN7", "DSP_0_BCIN7" ], [ "BRKH_DSP_BCIN8", "DSP_0_BCIN8" ], [ "BRKH_DSP_BCIN9", "DSP_0_BCIN9" ], [ "BRKH_DSP_BCIN10", "DSP_0_BCIN10" ], [ "BRKH_DSP_BCIN11", "DSP_0_BCIN11" ], [ "BRKH_DSP_BCIN12", "DSP_0_BCIN12" ], [ "BRKH_DSP_BCIN13", "DSP_0_BCIN13" ], [ "BRKH_DSP_BCIN14", "DSP_0_BCIN14" ], [ "BRKH_DSP_BCIN15", "DSP_0_BCIN15" ], [ "BRKH_DSP_BCIN16", "DSP_0_BCIN16" ], [ "BRKH_DSP_BCIN17", "DSP_0_BCIN17" ], [ "BRKH_DSP_CARRYCASCIN", "DSP_0_CARRYCASCIN" ], [ "BRKH_DSP_MULTSIGNIN", "DSP_0_MULTSIGNIN" ], [ "BRKH_DSP_PCIN0", "DSP_0_PCIN0" ], [ "BRKH_DSP_PCIN1", "DSP_0_PCIN1" ], [ "BRKH_DSP_PCIN2", "DSP_0_PCIN2" ], [ "BRKH_DSP_PCIN3", "DSP_0_PCIN3" ], [ "BRKH_DSP_PCIN4", "DSP_0_PCIN4" ], [ "BRKH_DSP_PCIN5", "DSP_0_PCIN5" ], [ "BRKH_DSP_PCIN6", "DSP_0_PCIN6" ], [ "BRKH_DSP_PCIN7", "DSP_0_PCIN7" ], [ "BRKH_DSP_PCIN8", "DSP_0_PCIN8" ], [ "BRKH_DSP_PCIN9", "DSP_0_PCIN9" ], [ "BRKH_DSP_PCIN10", "DSP_0_PCIN10" ], [ "BRKH_DSP_PCIN11", "DSP_0_PCIN11" ], [ "BRKH_DSP_PCIN12", "DSP_0_PCIN12" ], [ "BRKH_DSP_PCIN13", "DSP_0_PCIN13" ], [ "BRKH_DSP_PCIN14", "DSP_0_PCIN14" ], [ "BRKH_DSP_PCIN15", "DSP_0_PCIN15" ], [ "BRKH_DSP_PCIN16", "DSP_0_PCIN16" ], [ "BRKH_DSP_PCIN17", "DSP_0_PCIN17" ], [ "BRKH_DSP_PCIN18", "DSP_0_PCIN18" ], [ "BRKH_DSP_PCIN19", "DSP_0_PCIN19" ], [ "BRKH_DSP_PCIN20", "DSP_0_PCIN20" ], [ "BRKH_DSP_PCIN21", "DSP_0_PCIN21" ], [ "BRKH_DSP_PCIN22", "DSP_0_PCIN22" ], [ "BRKH_DSP_PCIN23", "DSP_0_PCIN23" ], [ "BRKH_DSP_PCIN24", "DSP_0_PCIN24" ], [ "BRKH_DSP_PCIN25", "DSP_0_PCIN25" ], [ "BRKH_DSP_PCIN26", "DSP_0_PCIN26" ], [ "BRKH_DSP_PCIN27", "DSP_0_PCIN27" ], [ "BRKH_DSP_PCIN28", "DSP_0_PCIN28" ], [ "BRKH_DSP_PCIN29", "DSP_0_PCIN29" ], [ "BRKH_DSP_PCIN30", "DSP_0_PCIN30" ], [ "BRKH_DSP_PCIN31", "DSP_0_PCIN31" ], [ "BRKH_DSP_PCIN32", "DSP_0_PCIN32" ], [ "BRKH_DSP_PCIN33", "DSP_0_PCIN33" ], [ "BRKH_DSP_PCIN34", "DSP_0_PCIN34" ], [ "BRKH_DSP_PCIN35", "DSP_0_PCIN35" ], [ "BRKH_DSP_PCIN36", "DSP_0_PCIN36" ], [ "BRKH_DSP_PCIN37", "DSP_0_PCIN37" ], [ "BRKH_DSP_PCIN38", "DSP_0_PCIN38" ], [ "BRKH_DSP_PCIN39", "DSP_0_PCIN39" ], [ "BRKH_DSP_PCIN40", "DSP_0_PCIN40" ], [ "BRKH_DSP_PCIN41", "DSP_0_PCIN41" ], [ "BRKH_DSP_PCIN42", "DSP_0_PCIN42" ], [ "BRKH_DSP_PCIN43", "DSP_0_PCIN43" ], [ "BRKH_DSP_PCIN44", "DSP_0_PCIN44" ], [ "BRKH_DSP_PCIN45", "DSP_0_PCIN45" ], [ "BRKH_DSP_PCIN46", "DSP_0_PCIN46" ], [ "BRKH_DSP_PCIN47", "DSP_0_PCIN47" ] ] }, { "grid_deltas": [ 0, 5 ], "tile_types": [ "BRKH_DSP_L", "DSP_L" ], "wire_pairs": [ [ "BRKH_DSP_ACIN0", "DSP_ACOUT0" ], [ "BRKH_DSP_ACIN1", "DSP_ACOUT1" ], [ "BRKH_DSP_ACIN2", "DSP_ACOUT2" ], [ "BRKH_DSP_ACIN3", "DSP_ACOUT3" ], [ "BRKH_DSP_ACIN4", "DSP_ACOUT4" ], [ "BRKH_DSP_ACIN5", "DSP_ACOUT5" ], [ "BRKH_DSP_ACIN6", "DSP_ACOUT6" ], [ "BRKH_DSP_ACIN7", "DSP_ACOUT7" ], [ "BRKH_DSP_ACIN8", "DSP_ACOUT8" ], [ "BRKH_DSP_ACIN9", "DSP_ACOUT9" ], [ "BRKH_DSP_ACIN10", "DSP_ACOUT10" ], [ "BRKH_DSP_ACIN11", "DSP_ACOUT11" ], [ "BRKH_DSP_ACIN12", "DSP_ACOUT12" ], [ "BRKH_DSP_ACIN13", "DSP_ACOUT13" ], [ "BRKH_DSP_ACIN14", "DSP_ACOUT14" ], [ "BRKH_DSP_ACIN15", "DSP_ACOUT15" ], [ "BRKH_DSP_ACIN16", "DSP_ACOUT16" ], [ "BRKH_DSP_ACIN17", "DSP_ACOUT17" ], [ "BRKH_DSP_ACIN18", "DSP_ACOUT18" ], [ "BRKH_DSP_ACIN19", "DSP_ACOUT19" ], [ "BRKH_DSP_ACIN20", "DSP_ACOUT20" ], [ "BRKH_DSP_ACIN21", "DSP_ACOUT21" ], [ "BRKH_DSP_ACIN22", "DSP_ACOUT22" ], [ "BRKH_DSP_ACIN23", "DSP_ACOUT23" ], [ "BRKH_DSP_ACIN24", "DSP_ACOUT24" ], [ "BRKH_DSP_ACIN25", "DSP_ACOUT25" ], [ "BRKH_DSP_ACIN26", "DSP_ACOUT26" ], [ "BRKH_DSP_ACIN27", "DSP_ACOUT27" ], [ "BRKH_DSP_ACIN28", "DSP_ACOUT28" ], [ "BRKH_DSP_ACIN29", "DSP_ACOUT29" ], [ "BRKH_DSP_BCIN0", "DSP_BCOUT0" ], [ "BRKH_DSP_BCIN1", "DSP_BCOUT1" ], [ "BRKH_DSP_BCIN2", "DSP_BCOUT2" ], [ "BRKH_DSP_BCIN3", "DSP_BCOUT3" ], [ "BRKH_DSP_BCIN4", "DSP_BCOUT4" ], [ "BRKH_DSP_BCIN5", "DSP_BCOUT5" ], [ "BRKH_DSP_BCIN6", "DSP_BCOUT6" ], [ "BRKH_DSP_BCIN7", "DSP_BCOUT7" ], [ "BRKH_DSP_BCIN8", "DSP_BCOUT8" ], [ "BRKH_DSP_BCIN9", "DSP_BCOUT9" ], [ "BRKH_DSP_BCIN10", "DSP_BCOUT10" ], [ "BRKH_DSP_BCIN11", "DSP_BCOUT11" ], [ "BRKH_DSP_BCIN12", "DSP_BCOUT12" ], [ "BRKH_DSP_BCIN13", "DSP_BCOUT13" ], [ "BRKH_DSP_BCIN14", "DSP_BCOUT14" ], [ "BRKH_DSP_BCIN15", "DSP_BCOUT15" ], [ "BRKH_DSP_BCIN16", "DSP_BCOUT16" ], [ "BRKH_DSP_BCIN17", "DSP_BCOUT17" ], [ "BRKH_DSP_CARRYCASCIN", "DSP_CARRYCASCOUT" ], [ "BRKH_DSP_MULTSIGNIN", "DSP_MULTSIGNOUT" ], [ "BRKH_DSP_PCIN0", "DSP_PCOUT0" ], [ "BRKH_DSP_PCIN1", "DSP_PCOUT1" ], [ "BRKH_DSP_PCIN2", "DSP_PCOUT2" ], [ "BRKH_DSP_PCIN3", "DSP_PCOUT3" ], [ "BRKH_DSP_PCIN4", "DSP_PCOUT4" ], [ "BRKH_DSP_PCIN5", "DSP_PCOUT5" ], [ "BRKH_DSP_PCIN6", "DSP_PCOUT6" ], [ "BRKH_DSP_PCIN7", "DSP_PCOUT7" ], [ "BRKH_DSP_PCIN8", "DSP_PCOUT8" ], [ "BRKH_DSP_PCIN9", "DSP_PCOUT9" ], [ "BRKH_DSP_PCIN10", "DSP_PCOUT10" ], [ "BRKH_DSP_PCIN11", "DSP_PCOUT11" ], [ "BRKH_DSP_PCIN12", "DSP_PCOUT12" ], [ "BRKH_DSP_PCIN13", "DSP_PCOUT13" ], [ "BRKH_DSP_PCIN14", "DSP_PCOUT14" ], [ "BRKH_DSP_PCIN15", "DSP_PCOUT15" ], [ "BRKH_DSP_PCIN16", "DSP_PCOUT16" ], [ "BRKH_DSP_PCIN17", "DSP_PCOUT17" ], [ "BRKH_DSP_PCIN18", "DSP_PCOUT18" ], [ "BRKH_DSP_PCIN19", "DSP_PCOUT19" ], [ "BRKH_DSP_PCIN20", "DSP_PCOUT20" ], [ "BRKH_DSP_PCIN21", "DSP_PCOUT21" ], [ "BRKH_DSP_PCIN22", "DSP_PCOUT22" ], [ "BRKH_DSP_PCIN23", "DSP_PCOUT23" ], [ "BRKH_DSP_PCIN24", "DSP_PCOUT24" ], [ "BRKH_DSP_PCIN25", "DSP_PCOUT25" ], [ "BRKH_DSP_PCIN26", "DSP_PCOUT26" ], [ "BRKH_DSP_PCIN27", "DSP_PCOUT27" ], [ "BRKH_DSP_PCIN28", "DSP_PCOUT28" ], [ "BRKH_DSP_PCIN29", "DSP_PCOUT29" ], [ "BRKH_DSP_PCIN30", "DSP_PCOUT30" ], [ "BRKH_DSP_PCIN31", "DSP_PCOUT31" ], [ "BRKH_DSP_PCIN32", "DSP_PCOUT32" ], [ "BRKH_DSP_PCIN33", "DSP_PCOUT33" ], [ "BRKH_DSP_PCIN34", "DSP_PCOUT34" ], [ "BRKH_DSP_PCIN35", "DSP_PCOUT35" ], [ "BRKH_DSP_PCIN36", "DSP_PCOUT36" ], [ "BRKH_DSP_PCIN37", "DSP_PCOUT37" ], [ "BRKH_DSP_PCIN38", "DSP_PCOUT38" ], [ "BRKH_DSP_PCIN39", "DSP_PCOUT39" ], [ "BRKH_DSP_PCIN40", "DSP_PCOUT40" ], [ "BRKH_DSP_PCIN41", "DSP_PCOUT41" ], [ "BRKH_DSP_PCIN42", "DSP_PCOUT42" ], [ "BRKH_DSP_PCIN43", "DSP_PCOUT43" ], [ "BRKH_DSP_PCIN44", "DSP_PCOUT44" ], [ "BRKH_DSP_PCIN45", "DSP_PCOUT45" ], [ "BRKH_DSP_PCIN46", "DSP_PCOUT46" ], [ "BRKH_DSP_PCIN47", "DSP_PCOUT47" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "BRKH_DSP_R", "DSP_R" ], "wire_pairs": [ [ "BRKH_DSP_ACIN0", "DSP_0_ACIN0" ], [ "BRKH_DSP_ACIN1", "DSP_0_ACIN1" ], [ "BRKH_DSP_ACIN2", "DSP_0_ACIN2" ], [ "BRKH_DSP_ACIN3", "DSP_0_ACIN3" ], [ "BRKH_DSP_ACIN4", "DSP_0_ACIN4" ], [ "BRKH_DSP_ACIN5", "DSP_0_ACIN5" ], [ "BRKH_DSP_ACIN6", "DSP_0_ACIN6" ], [ "BRKH_DSP_ACIN7", "DSP_0_ACIN7" ], [ "BRKH_DSP_ACIN8", "DSP_0_ACIN8" ], [ "BRKH_DSP_ACIN9", "DSP_0_ACIN9" ], [ "BRKH_DSP_ACIN10", "DSP_0_ACIN10" ], [ "BRKH_DSP_ACIN11", "DSP_0_ACIN11" ], [ "BRKH_DSP_ACIN12", "DSP_0_ACIN12" ], [ "BRKH_DSP_ACIN13", "DSP_0_ACIN13" ], [ "BRKH_DSP_ACIN14", "DSP_0_ACIN14" ], [ "BRKH_DSP_ACIN15", "DSP_0_ACIN15" ], [ "BRKH_DSP_ACIN16", "DSP_0_ACIN16" ], [ "BRKH_DSP_ACIN17", "DSP_0_ACIN17" ], [ "BRKH_DSP_ACIN18", "DSP_0_ACIN18" ], [ "BRKH_DSP_ACIN19", "DSP_0_ACIN19" ], [ "BRKH_DSP_ACIN20", "DSP_0_ACIN20" ], [ "BRKH_DSP_ACIN21", "DSP_0_ACIN21" ], [ "BRKH_DSP_ACIN22", "DSP_0_ACIN22" ], [ "BRKH_DSP_ACIN23", "DSP_0_ACIN23" ], [ "BRKH_DSP_ACIN24", "DSP_0_ACIN24" ], [ "BRKH_DSP_ACIN25", "DSP_0_ACIN25" ], [ "BRKH_DSP_ACIN26", "DSP_0_ACIN26" ], [ "BRKH_DSP_ACIN27", "DSP_0_ACIN27" ], [ "BRKH_DSP_ACIN28", "DSP_0_ACIN28" ], [ "BRKH_DSP_ACIN29", "DSP_0_ACIN29" ], [ "BRKH_DSP_BCIN0", "DSP_0_BCIN0" ], [ "BRKH_DSP_BCIN1", "DSP_0_BCIN1" ], [ "BRKH_DSP_BCIN2", "DSP_0_BCIN2" ], [ "BRKH_DSP_BCIN3", "DSP_0_BCIN3" ], [ "BRKH_DSP_BCIN4", "DSP_0_BCIN4" ], [ "BRKH_DSP_BCIN5", "DSP_0_BCIN5" ], [ "BRKH_DSP_BCIN6", "DSP_0_BCIN6" ], [ "BRKH_DSP_BCIN7", "DSP_0_BCIN7" ], [ "BRKH_DSP_BCIN8", "DSP_0_BCIN8" ], [ "BRKH_DSP_BCIN9", "DSP_0_BCIN9" ], [ "BRKH_DSP_BCIN10", "DSP_0_BCIN10" ], [ "BRKH_DSP_BCIN11", "DSP_0_BCIN11" ], [ "BRKH_DSP_BCIN12", "DSP_0_BCIN12" ], [ "BRKH_DSP_BCIN13", "DSP_0_BCIN13" ], [ "BRKH_DSP_BCIN14", "DSP_0_BCIN14" ], [ "BRKH_DSP_BCIN15", "DSP_0_BCIN15" ], [ "BRKH_DSP_BCIN16", "DSP_0_BCIN16" ], [ "BRKH_DSP_BCIN17", "DSP_0_BCIN17" ], [ "BRKH_DSP_CARRYCASCIN", "DSP_0_CARRYCASCIN" ], [ "BRKH_DSP_MULTSIGNIN", "DSP_0_MULTSIGNIN" ], [ "BRKH_DSP_PCIN0", "DSP_0_PCIN0" ], [ "BRKH_DSP_PCIN1", "DSP_0_PCIN1" ], [ "BRKH_DSP_PCIN2", "DSP_0_PCIN2" ], [ "BRKH_DSP_PCIN3", "DSP_0_PCIN3" ], [ "BRKH_DSP_PCIN4", "DSP_0_PCIN4" ], [ "BRKH_DSP_PCIN5", "DSP_0_PCIN5" ], [ "BRKH_DSP_PCIN6", "DSP_0_PCIN6" ], [ "BRKH_DSP_PCIN7", "DSP_0_PCIN7" ], [ "BRKH_DSP_PCIN8", "DSP_0_PCIN8" ], [ "BRKH_DSP_PCIN9", "DSP_0_PCIN9" ], [ "BRKH_DSP_PCIN10", "DSP_0_PCIN10" ], [ "BRKH_DSP_PCIN11", "DSP_0_PCIN11" ], [ "BRKH_DSP_PCIN12", "DSP_0_PCIN12" ], [ "BRKH_DSP_PCIN13", "DSP_0_PCIN13" ], [ "BRKH_DSP_PCIN14", "DSP_0_PCIN14" ], [ "BRKH_DSP_PCIN15", "DSP_0_PCIN15" ], [ "BRKH_DSP_PCIN16", "DSP_0_PCIN16" ], [ "BRKH_DSP_PCIN17", "DSP_0_PCIN17" ], [ "BRKH_DSP_PCIN18", "DSP_0_PCIN18" ], [ "BRKH_DSP_PCIN19", "DSP_0_PCIN19" ], [ "BRKH_DSP_PCIN20", "DSP_0_PCIN20" ], [ "BRKH_DSP_PCIN21", "DSP_0_PCIN21" ], [ "BRKH_DSP_PCIN22", "DSP_0_PCIN22" ], [ "BRKH_DSP_PCIN23", "DSP_0_PCIN23" ], [ "BRKH_DSP_PCIN24", "DSP_0_PCIN24" ], [ "BRKH_DSP_PCIN25", "DSP_0_PCIN25" ], [ "BRKH_DSP_PCIN26", "DSP_0_PCIN26" ], [ "BRKH_DSP_PCIN27", "DSP_0_PCIN27" ], [ "BRKH_DSP_PCIN28", "DSP_0_PCIN28" ], [ "BRKH_DSP_PCIN29", "DSP_0_PCIN29" ], [ "BRKH_DSP_PCIN30", "DSP_0_PCIN30" ], [ "BRKH_DSP_PCIN31", "DSP_0_PCIN31" ], [ "BRKH_DSP_PCIN32", "DSP_0_PCIN32" ], [ "BRKH_DSP_PCIN33", "DSP_0_PCIN33" ], [ "BRKH_DSP_PCIN34", "DSP_0_PCIN34" ], [ "BRKH_DSP_PCIN35", "DSP_0_PCIN35" ], [ "BRKH_DSP_PCIN36", "DSP_0_PCIN36" ], [ "BRKH_DSP_PCIN37", "DSP_0_PCIN37" ], [ "BRKH_DSP_PCIN38", "DSP_0_PCIN38" ], [ "BRKH_DSP_PCIN39", "DSP_0_PCIN39" ], [ "BRKH_DSP_PCIN40", "DSP_0_PCIN40" ], [ "BRKH_DSP_PCIN41", "DSP_0_PCIN41" ], [ "BRKH_DSP_PCIN42", "DSP_0_PCIN42" ], [ "BRKH_DSP_PCIN43", "DSP_0_PCIN43" ], [ "BRKH_DSP_PCIN44", "DSP_0_PCIN44" ], [ "BRKH_DSP_PCIN45", "DSP_0_PCIN45" ], [ "BRKH_DSP_PCIN46", "DSP_0_PCIN46" ], [ "BRKH_DSP_PCIN47", "DSP_0_PCIN47" ] ] }, { "grid_deltas": [ 0, 5 ], "tile_types": [ "BRKH_DSP_R", "DSP_R" ], "wire_pairs": [ [ "BRKH_DSP_ACIN0", "DSP_ACOUT0" ], [ "BRKH_DSP_ACIN1", "DSP_ACOUT1" ], [ "BRKH_DSP_ACIN2", "DSP_ACOUT2" ], [ "BRKH_DSP_ACIN3", "DSP_ACOUT3" ], [ "BRKH_DSP_ACIN4", "DSP_ACOUT4" ], [ "BRKH_DSP_ACIN5", "DSP_ACOUT5" ], [ "BRKH_DSP_ACIN6", "DSP_ACOUT6" ], [ "BRKH_DSP_ACIN7", "DSP_ACOUT7" ], [ "BRKH_DSP_ACIN8", "DSP_ACOUT8" ], [ "BRKH_DSP_ACIN9", "DSP_ACOUT9" ], [ "BRKH_DSP_ACIN10", "DSP_ACOUT10" ], [ "BRKH_DSP_ACIN11", "DSP_ACOUT11" ], [ "BRKH_DSP_ACIN12", "DSP_ACOUT12" ], [ "BRKH_DSP_ACIN13", "DSP_ACOUT13" ], [ "BRKH_DSP_ACIN14", "DSP_ACOUT14" ], [ "BRKH_DSP_ACIN15", "DSP_ACOUT15" ], [ "BRKH_DSP_ACIN16", "DSP_ACOUT16" ], [ "BRKH_DSP_ACIN17", "DSP_ACOUT17" ], [ "BRKH_DSP_ACIN18", "DSP_ACOUT18" ], [ "BRKH_DSP_ACIN19", "DSP_ACOUT19" ], [ "BRKH_DSP_ACIN20", "DSP_ACOUT20" ], [ "BRKH_DSP_ACIN21", "DSP_ACOUT21" ], [ "BRKH_DSP_ACIN22", "DSP_ACOUT22" ], [ "BRKH_DSP_ACIN23", "DSP_ACOUT23" ], [ "BRKH_DSP_ACIN24", "DSP_ACOUT24" ], [ "BRKH_DSP_ACIN25", "DSP_ACOUT25" ], [ "BRKH_DSP_ACIN26", "DSP_ACOUT26" ], [ "BRKH_DSP_ACIN27", "DSP_ACOUT27" ], [ "BRKH_DSP_ACIN28", "DSP_ACOUT28" ], [ "BRKH_DSP_ACIN29", "DSP_ACOUT29" ], [ "BRKH_DSP_BCIN0", "DSP_BCOUT0" ], [ "BRKH_DSP_BCIN1", "DSP_BCOUT1" ], [ "BRKH_DSP_BCIN2", "DSP_BCOUT2" ], [ "BRKH_DSP_BCIN3", "DSP_BCOUT3" ], [ "BRKH_DSP_BCIN4", "DSP_BCOUT4" ], [ "BRKH_DSP_BCIN5", "DSP_BCOUT5" ], [ "BRKH_DSP_BCIN6", "DSP_BCOUT6" ], [ "BRKH_DSP_BCIN7", "DSP_BCOUT7" ], [ "BRKH_DSP_BCIN8", "DSP_BCOUT8" ], [ "BRKH_DSP_BCIN9", "DSP_BCOUT9" ], [ "BRKH_DSP_BCIN10", "DSP_BCOUT10" ], [ "BRKH_DSP_BCIN11", "DSP_BCOUT11" ], [ "BRKH_DSP_BCIN12", "DSP_BCOUT12" ], [ "BRKH_DSP_BCIN13", "DSP_BCOUT13" ], [ "BRKH_DSP_BCIN14", "DSP_BCOUT14" ], [ "BRKH_DSP_BCIN15", "DSP_BCOUT15" ], [ "BRKH_DSP_BCIN16", "DSP_BCOUT16" ], [ "BRKH_DSP_BCIN17", "DSP_BCOUT17" ], [ "BRKH_DSP_CARRYCASCIN", "DSP_CARRYCASCOUT" ], [ "BRKH_DSP_MULTSIGNIN", "DSP_MULTSIGNOUT" ], [ "BRKH_DSP_PCIN0", "DSP_PCOUT0" ], [ "BRKH_DSP_PCIN1", "DSP_PCOUT1" ], [ "BRKH_DSP_PCIN2", "DSP_PCOUT2" ], [ "BRKH_DSP_PCIN3", "DSP_PCOUT3" ], [ "BRKH_DSP_PCIN4", "DSP_PCOUT4" ], [ "BRKH_DSP_PCIN5", "DSP_PCOUT5" ], [ "BRKH_DSP_PCIN6", "DSP_PCOUT6" ], [ "BRKH_DSP_PCIN7", "DSP_PCOUT7" ], [ "BRKH_DSP_PCIN8", "DSP_PCOUT8" ], [ "BRKH_DSP_PCIN9", "DSP_PCOUT9" ], [ "BRKH_DSP_PCIN10", "DSP_PCOUT10" ], [ "BRKH_DSP_PCIN11", "DSP_PCOUT11" ], [ "BRKH_DSP_PCIN12", "DSP_PCOUT12" ], [ "BRKH_DSP_PCIN13", "DSP_PCOUT13" ], [ "BRKH_DSP_PCIN14", "DSP_PCOUT14" ], [ "BRKH_DSP_PCIN15", "DSP_PCOUT15" ], [ "BRKH_DSP_PCIN16", "DSP_PCOUT16" ], [ "BRKH_DSP_PCIN17", "DSP_PCOUT17" ], [ "BRKH_DSP_PCIN18", "DSP_PCOUT18" ], [ "BRKH_DSP_PCIN19", "DSP_PCOUT19" ], [ "BRKH_DSP_PCIN20", "DSP_PCOUT20" ], [ "BRKH_DSP_PCIN21", "DSP_PCOUT21" ], [ "BRKH_DSP_PCIN22", "DSP_PCOUT22" ], [ "BRKH_DSP_PCIN23", "DSP_PCOUT23" ], [ "BRKH_DSP_PCIN24", "DSP_PCOUT24" ], [ "BRKH_DSP_PCIN25", "DSP_PCOUT25" ], [ "BRKH_DSP_PCIN26", "DSP_PCOUT26" ], [ "BRKH_DSP_PCIN27", "DSP_PCOUT27" ], [ "BRKH_DSP_PCIN28", "DSP_PCOUT28" ], [ "BRKH_DSP_PCIN29", "DSP_PCOUT29" ], [ "BRKH_DSP_PCIN30", "DSP_PCOUT30" ], [ "BRKH_DSP_PCIN31", "DSP_PCOUT31" ], [ "BRKH_DSP_PCIN32", "DSP_PCOUT32" ], [ "BRKH_DSP_PCIN33", "DSP_PCOUT33" ], [ "BRKH_DSP_PCIN34", "DSP_PCOUT34" ], [ "BRKH_DSP_PCIN35", "DSP_PCOUT35" ], [ "BRKH_DSP_PCIN36", "DSP_PCOUT36" ], [ "BRKH_DSP_PCIN37", "DSP_PCOUT37" ], [ "BRKH_DSP_PCIN38", "DSP_PCOUT38" ], [ "BRKH_DSP_PCIN39", "DSP_PCOUT39" ], [ "BRKH_DSP_PCIN40", "DSP_PCOUT40" ], [ "BRKH_DSP_PCIN41", "DSP_PCOUT41" ], [ "BRKH_DSP_PCIN42", "DSP_PCOUT42" ], [ "BRKH_DSP_PCIN43", "DSP_PCOUT43" ], [ "BRKH_DSP_PCIN44", "DSP_PCOUT44" ], [ "BRKH_DSP_PCIN45", "DSP_PCOUT45" ], [ "BRKH_DSP_PCIN46", "DSP_PCOUT46" ], [ "BRKH_DSP_PCIN47", "DSP_PCOUT47" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "BRKH_INT", "INT_L" ], "wire_pairs": [ [ "BRKH_INT_BYP_BOUNCE2", "BYP_BOUNCE_N3_2" ], [ "BRKH_INT_BYP_BOUNCE3", "BYP_BOUNCE_N3_3" ], [ "BRKH_INT_BYP_BOUNCE6", "BYP_BOUNCE_N3_6" ], [ "BRKH_INT_BYP_BOUNCE7", "BYP_BOUNCE_N3_7" ], [ "BRKH_INT_EL1BEG3", "EL1BEG_N3" ], [ "BRKH_INT_EL1END_S3_0", "EL1END0" ], [ "BRKH_INT_ER1BEG_S0", "ER1BEG0" ], [ "BRKH_INT_ER1END3", "ER1END_N3_3" ], [ "BRKH_INT_FAN_BOUNCE_S3_0", "FAN_BOUNCE0" ], [ "BRKH_INT_FAN_BOUNCE_S3_2", "FAN_BOUNCE2" ], [ "BRKH_INT_FAN_BOUNCE_S3_4", "FAN_BOUNCE4" ], [ "BRKH_INT_FAN_BOUNCE_S3_6", "FAN_BOUNCE6" ], [ "BRKH_INT_LVB_L1", "LVB_L1" ], [ "BRKH_INT_LVB_L2", "LVB_L2" ], [ "BRKH_INT_LVB_L3", "LVB_L3" ], [ "BRKH_INT_LVB_L4", "LVB_L4" ], [ "BRKH_INT_LVB_L5", "LVB_L5" ], [ "BRKH_INT_LVB_L6", "LVB_L6" ], [ "BRKH_INT_LVB_L7", "LVB_L7" ], [ "BRKH_INT_LVB_L8", "LVB_L8" ], [ "BRKH_INT_LVB_L9", "LVB_L9" ], [ "BRKH_INT_LVB_L10", "LVB_L10" ], [ "BRKH_INT_LVB_L11", "LVB_L11" ], [ "BRKH_INT_LVB_L12", "LVB_L12" ], [ "BRKH_INT_L_LV0", "LV_L1" ], [ "BRKH_INT_L_LV1", "LV_L2" ], [ "BRKH_INT_L_LV2", "LV_L3" ], [ "BRKH_INT_L_LV3", "LV_L4" ], [ "BRKH_INT_L_LV4", "LV_L5" ], [ "BRKH_INT_L_LV5", "LV_L6" ], [ "BRKH_INT_L_LV6", "LV_L7" ], [ "BRKH_INT_L_LV7", "LV_L8" ], [ "BRKH_INT_L_LV8", "LV_L9" ], [ "BRKH_INT_L_LV9", "LV_L10" ], [ "BRKH_INT_L_LV10", "LV_L11" ], [ "BRKH_INT_L_LV11", "LV_L12" ], [ "BRKH_INT_L_LV12", "LV_L13" ], [ "BRKH_INT_L_LV13", "LV_L14" ], [ "BRKH_INT_L_LV14", "LV_L15" ], [ "BRKH_INT_L_LV15", "LV_L16" ], [ "BRKH_INT_L_LV16", "LV_L17" ], [ "BRKH_INT_L_LV17", "LV_L18" ], [ "BRKH_INT_NE2BEG0", "NE2A0" ], [ "BRKH_INT_NE2BEG1", "NE2A1" ], [ "BRKH_INT_NE2BEG2", "NE2A2" ], [ "BRKH_INT_NE2BEG3", "NE2A3" ], [ "BRKH_INT_NE2END_S3_0", "NE2END0" ], [ "BRKH_INT_NE6A0", "NE6B0" ], [ "BRKH_INT_NE6A1", "NE6B1" ], [ "BRKH_INT_NE6A2", "NE6B2" ], [ "BRKH_INT_NE6A3", "NE6B3" ], [ "BRKH_INT_NE6B0", "NE6C0" ], [ "BRKH_INT_NE6B1", "NE6C1" ], [ "BRKH_INT_NE6B2", "NE6C2" ], [ "BRKH_INT_NE6B3", "NE6C3" ], [ "BRKH_INT_NE6C0", "NE6D0" ], [ "BRKH_INT_NE6C1", "NE6D1" ], [ "BRKH_INT_NE6C2", "NE6D2" ], [ "BRKH_INT_NE6C3", "NE6D3" ], [ "BRKH_INT_NE6D0", "NE6E0" ], [ "BRKH_INT_NE6D1", "NE6E1" ], [ "BRKH_INT_NE6D2", "NE6E2" ], [ "BRKH_INT_NE6D3", "NE6E3" ], [ "BRKH_INT_NL1BEG0_SLOW", "NL1END0" ], [ "BRKH_INT_NL1BEG1_SLOW", "NL1END1" ], [ "BRKH_INT_NL1BEG2_SLOW", "NL1END2" ], [ "BRKH_INT_NL1END_S3_0", "NL1END0" ], [ "BRKH_INT_NN2A0", "NN2END0" ], [ "BRKH_INT_NN2A1", "NN2END1" ], [ "BRKH_INT_NN2A2", "NN2END2" ], [ "BRKH_INT_NN2A3", "NN2END3" ], [ "BRKH_INT_NN2BEG0", "NN2A0" ], [ "BRKH_INT_NN2BEG1", "NN2A1" ], [ "BRKH_INT_NN2BEG2", "NN2A2" ], [ "BRKH_INT_NN2BEG3", "NN2A3" ], [ "BRKH_INT_NN2END_S2_0", "NN2END0" ], [ "BRKH_INT_NN6A0", "NN6B0" ], [ "BRKH_INT_NN6A1", "NN6B1" ], [ "BRKH_INT_NN6A2", "NN6B2" ], [ "BRKH_INT_NN6A3", "NN6B3" ], [ "BRKH_INT_NN6B0", "NN6C0" ], [ "BRKH_INT_NN6B1", "NN6C1" ], [ "BRKH_INT_NN6B2", "NN6C2" ], [ "BRKH_INT_NN6B3", "NN6C3" ], [ "BRKH_INT_NN6BEG0", "NN6A0" ], [ "BRKH_INT_NN6BEG1", "NN6A1" ], [ "BRKH_INT_NN6BEG2", "NN6A2" ], [ "BRKH_INT_NN6BEG3", "NN6A3" ], [ "BRKH_INT_NN6C0", "NN6D0" ], [ "BRKH_INT_NN6C1", "NN6D1" ], [ "BRKH_INT_NN6C2", "NN6D2" ], [ "BRKH_INT_NN6C3", "NN6D3" ], [ "BRKH_INT_NN6D0", "NN6E0" ], [ "BRKH_INT_NN6D1", "NN6E1" ], [ "BRKH_INT_NN6D2", "NN6E2" ], [ "BRKH_INT_NN6D3", "NN6E3" ], [ "BRKH_INT_NN6E0", "NN6END0" ], [ "BRKH_INT_NN6E1", "NN6END1" ], [ "BRKH_INT_NN6E2", "NN6END2" ], [ "BRKH_INT_NN6E3", "NN6END3" ], [ "BRKH_INT_NN6END_S1_0", "NN6END0" ], [ "BRKH_INT_NR1BEG0_SLOW", "NR1END0" ], [ "BRKH_INT_NR1BEG1_SLOW", "NR1END1" ], [ "BRKH_INT_NR1BEG2_SLOW", "NR1END2" ], [ "BRKH_INT_NR1BEG3_SLOW", "NR1END3" ], [ "BRKH_INT_NW2BEG0", "NW2A0" ], [ "BRKH_INT_NW2BEG1", "NW2A1" ], [ "BRKH_INT_NW2BEG2", "NW2A2" ], [ "BRKH_INT_NW2BEG3", "NW2A3" ], [ "BRKH_INT_NW2END_S0_0", "NW2END0" ], [ "BRKH_INT_NW6A0", "NW6B0" ], [ "BRKH_INT_NW6A1", "NW6B1" ], [ "BRKH_INT_NW6A2", "NW6B2" ], [ "BRKH_INT_NW6A3", "NW6B3" ], [ "BRKH_INT_NW6B0", "NW6C0" ], [ "BRKH_INT_NW6B1", "NW6C1" ], [ "BRKH_INT_NW6B2", "NW6C2" ], [ "BRKH_INT_NW6B3", "NW6C3" ], [ "BRKH_INT_NW6C0", "NW6D0" ], [ "BRKH_INT_NW6C1", "NW6D1" ], [ "BRKH_INT_NW6C2", "NW6D2" ], [ "BRKH_INT_NW6C3", "NW6D3" ], [ "BRKH_INT_NW6D0", "NW6E0" ], [ "BRKH_INT_NW6D1", "NW6E1" ], [ "BRKH_INT_NW6D2", "NW6E2" ], [ "BRKH_INT_NW6D3", "NW6E3" ], [ "BRKH_INT_NW6END_S0_0", "NW6END0" ], [ "BRKH_INT_SE2A0", "SE2BEG0" ], [ "BRKH_INT_SE2A1", "SE2BEG1" ], [ "BRKH_INT_SE2A2", "SE2BEG2" ], [ "BRKH_INT_SE2A3", "SE2BEG3" ], [ "BRKH_INT_SE6B0", "SE6A0" ], [ "BRKH_INT_SE6B1", "SE6A1" ], [ "BRKH_INT_SE6B2", "SE6A2" ], [ "BRKH_INT_SE6B3", "SE6A3" ], [ "BRKH_INT_SE6C0", "SE6B0" ], [ "BRKH_INT_SE6C1", "SE6B1" ], [ "BRKH_INT_SE6C2", "SE6B2" ], [ "BRKH_INT_SE6C3", "SE6B3" ], [ "BRKH_INT_SE6D0", "SE6C0" ], [ "BRKH_INT_SE6D1", "SE6C1" ], [ "BRKH_INT_SE6D2", "SE6C2" ], [ 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"BRKH_INT_NN2A1", "NN2A1" ], [ "BRKH_INT_NN2A2", "NN2A2" ], [ "BRKH_INT_NN2A3", "NN2A3" ], [ "BRKH_INT_NN2BEG0", "NN2BEG0" ], [ "BRKH_INT_NN2BEG1", "NN2BEG1" ], [ "BRKH_INT_NN2BEG2", "NN2BEG2" ], [ "BRKH_INT_NN2BEG3", "NN2BEG3" ], [ "BRKH_INT_NN2END_S2_0", "NN2END_S2_0" ], [ "BRKH_INT_NN6A0", "NN6A0" ], [ "BRKH_INT_NN6A1", "NN6A1" ], [ "BRKH_INT_NN6A2", "NN6A2" ], [ "BRKH_INT_NN6A3", "NN6A3" ], [ "BRKH_INT_NN6B0", "NN6B0" ], [ "BRKH_INT_NN6B1", "NN6B1" ], [ "BRKH_INT_NN6B2", "NN6B2" ], [ "BRKH_INT_NN6B3", "NN6B3" ], [ "BRKH_INT_NN6BEG0", "NN6BEG0" ], [ "BRKH_INT_NN6BEG1", "NN6BEG1" ], [ "BRKH_INT_NN6BEG2", "NN6BEG2" ], [ "BRKH_INT_NN6BEG3", "NN6BEG3" ], [ "BRKH_INT_NN6C0", "NN6C0" ], [ "BRKH_INT_NN6C1", "NN6C1" ], [ "BRKH_INT_NN6C2", "NN6C2" ], [ "BRKH_INT_NN6C3", "NN6C3" ], [ "BRKH_INT_NN6D0", "NN6D0" ], [ "BRKH_INT_NN6D1", "NN6D1" ], [ "BRKH_INT_NN6D2", "NN6D2" ], [ "BRKH_INT_NN6D3", "NN6D3" ], [ "BRKH_INT_NN6E0", "NN6E0" ], [ "BRKH_INT_NN6E1", "NN6E1" ], [ "BRKH_INT_NN6E2", "NN6E2" ], [ "BRKH_INT_NN6E3", "NN6E3" ], [ "BRKH_INT_NN6END_S1_0", "NN6END_S1_0" ], [ "BRKH_INT_NR1BEG0", "NR1BEG0" ], [ "BRKH_INT_NR1BEG1", "NR1BEG1" ], [ "BRKH_INT_NR1BEG2", "NR1BEG2" ], [ "BRKH_INT_NR1BEG3", "NR1BEG3" ], [ "BRKH_INT_NW2BEG0", "NW2BEG0" ], [ "BRKH_INT_NW2BEG1", "NW2BEG1" ], [ "BRKH_INT_NW2BEG2", "NW2BEG2" ], [ "BRKH_INT_NW2BEG3", "NW2BEG3" ], [ "BRKH_INT_NW2END_S0_0", "NW2END_S0_0" ], [ "BRKH_INT_NW6A0", "NW6A0" ], [ "BRKH_INT_NW6A1", "NW6A1" ], [ "BRKH_INT_NW6A2", "NW6A2" ], [ "BRKH_INT_NW6A3", "NW6A3" ], [ "BRKH_INT_NW6B0", "NW6B0" ], [ "BRKH_INT_NW6B1", "NW6B1" ], [ "BRKH_INT_NW6B2", "NW6B2" ], [ "BRKH_INT_NW6B3", "NW6B3" ], [ "BRKH_INT_NW6C0", "NW6C0" ], [ "BRKH_INT_NW6C1", "NW6C1" ], [ "BRKH_INT_NW6C2", "NW6C2" ], [ "BRKH_INT_NW6C3", "NW6C3" ], [ "BRKH_INT_NW6D0", "NW6D0" ], [ "BRKH_INT_NW6D1", "NW6D1" ], [ "BRKH_INT_NW6D2", "NW6D2" ], [ "BRKH_INT_NW6D3", "NW6D3" ], [ "BRKH_INT_NW6END_S0_0", "NW6END_S0_0" ], [ "BRKH_INT_SE2A0", "SE2A0" ], [ "BRKH_INT_SE2A1", "SE2A1" ], [ "BRKH_INT_SE2A2", "SE2A2" ], [ "BRKH_INT_SE2A3", "SE2A3" ], [ "BRKH_INT_SE6B0", "SE6B0" ], [ "BRKH_INT_SE6B1", "SE6B1" ], [ "BRKH_INT_SE6B2", "SE6B2" ], [ "BRKH_INT_SE6B3", "SE6B3" ], [ "BRKH_INT_SE6C0", "SE6C0" ], [ "BRKH_INT_SE6C1", "SE6C1" ], [ "BRKH_INT_SE6C2", "SE6C2" ], [ "BRKH_INT_SE6C3", "SE6C3" ], [ "BRKH_INT_SE6D0", "SE6D0" ], [ "BRKH_INT_SE6D1", "SE6D1" ], [ "BRKH_INT_SE6D2", "SE6D2" ], [ "BRKH_INT_SE6D3", "SE6D3" ], [ "BRKH_INT_SE6E0", "SE6E0" ], [ "BRKH_INT_SE6E1", "SE6E1" ], [ "BRKH_INT_SE6E2", "SE6E2" ], [ "BRKH_INT_SE6E3", "SE6E3" ], [ "BRKH_INT_SL1END0", "SL1END0" ], [ "BRKH_INT_SL1END1", "SL1END1" ], [ "BRKH_INT_SL1END2", "SL1END2" ], [ "BRKH_INT_SL1END3", "SL1END3" ], [ "BRKH_INT_SR1END1", "SR1END1" ], [ "BRKH_INT_SR1END2", "SR1END2" ], [ "BRKH_INT_SR1END3", "SR1END3" ], [ "BRKH_INT_SR1END_N3_3", "SR1END3" ], [ "BRKH_INT_SS2A0", "SS2A0" ], [ "BRKH_INT_SS2A1", "SS2A1" ], [ "BRKH_INT_SS2A2", "SS2A2" ], [ "BRKH_INT_SS2A3", "SS2A3" ], [ "BRKH_INT_SS2END0", "SS2END0" ], [ "BRKH_INT_SS2END1", "SS2END1" ], [ "BRKH_INT_SS2END2", "SS2END2" ], [ "BRKH_INT_SS2END3", "SS2END3" ], [ "BRKH_INT_SS2END_N0_3", "SS2END3" ], [ "BRKH_INT_SS6A0", "SS6A0" ], [ "BRKH_INT_SS6A1", "SS6A1" ], [ "BRKH_INT_SS6A2", "SS6A2" ], [ "BRKH_INT_SS6A3", "SS6A3" ], [ "BRKH_INT_SS6B0", "SS6B0" ], [ "BRKH_INT_SS6B1", "SS6B1" ], [ "BRKH_INT_SS6B2", "SS6B2" ], [ "BRKH_INT_SS6B3", "SS6B3" ], [ "BRKH_INT_SS6C0", "SS6C0" ], [ "BRKH_INT_SS6C1", "SS6C1" ], [ "BRKH_INT_SS6C2", "SS6C2" ], [ "BRKH_INT_SS6C3", "SS6C3" ], [ "BRKH_INT_SS6D0", "SS6D0" ], [ "BRKH_INT_SS6D1", "SS6D1" ], [ "BRKH_INT_SS6D2", "SS6D2" ], [ "BRKH_INT_SS6D3", "SS6D3" ], [ "BRKH_INT_SS6E0", "SS6E0" ], [ "BRKH_INT_SS6E1", "SS6E1" ], [ "BRKH_INT_SS6E2", "SS6E2" ], [ "BRKH_INT_SS6E3", "SS6E3" ], [ "BRKH_INT_SS6END0", "SS6END0" ], [ "BRKH_INT_SS6END1", "SS6END1" ], [ "BRKH_INT_SS6END2", "SS6END2" ], [ "BRKH_INT_SS6END3", "SS6END3" ], [ "BRKH_INT_SS6END_N0_3", "SS6END3" ], [ "BRKH_INT_SW2A0", "SW2A0" ], [ "BRKH_INT_SW2A1", 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], [ "BRKH_INT_SE6E2", "SE6E2" ], [ "BRKH_INT_SE6E3", "SE6E3" ], [ "BRKH_INT_SL1END0", "SL1END0" ], [ "BRKH_INT_SL1END1", "SL1END1" ], [ "BRKH_INT_SL1END2", "SL1END2" ], [ "BRKH_INT_SL1END3", "SL1END3" ], [ "BRKH_INT_SR1END1", "SR1END1" ], [ "BRKH_INT_SR1END2", "SR1END2" ], [ "BRKH_INT_SR1END3", "SR1END3" ], [ "BRKH_INT_SR1END_N3_3", "SR1END3" ], [ "BRKH_INT_SS2A0", "SS2A0" ], [ "BRKH_INT_SS2A1", "SS2A1" ], [ "BRKH_INT_SS2A2", "SS2A2" ], [ "BRKH_INT_SS2A3", "SS2A3" ], [ "BRKH_INT_SS2END0", "SS2END0" ], [ "BRKH_INT_SS2END1", "SS2END1" ], [ "BRKH_INT_SS2END2", "SS2END2" ], [ "BRKH_INT_SS2END3", "SS2END3" ], [ "BRKH_INT_SS2END_N0_3", "SS2END3" ], [ "BRKH_INT_SS6A0", "SS6A0" ], [ "BRKH_INT_SS6A1", "SS6A1" ], [ "BRKH_INT_SS6A2", "SS6A2" ], [ "BRKH_INT_SS6A3", "SS6A3" ], [ "BRKH_INT_SS6B0", "SS6B0" ], [ "BRKH_INT_SS6B1", "SS6B1" ], [ "BRKH_INT_SS6B2", "SS6B2" ], [ "BRKH_INT_SS6B3", "SS6B3" ], [ "BRKH_INT_SS6C0", "SS6C0" ], [ "BRKH_INT_SS6C1", "SS6C1" ], [ "BRKH_INT_SS6C2", "SS6C2" ], [ "BRKH_INT_SS6C3", "SS6C3" ], [ "BRKH_INT_SS6D0", "SS6D0" ], [ "BRKH_INT_SS6D1", "SS6D1" ], [ "BRKH_INT_SS6D2", "SS6D2" ], [ "BRKH_INT_SS6D3", "SS6D3" ], [ "BRKH_INT_SS6E0", "SS6E0" ], [ "BRKH_INT_SS6E1", "SS6E1" ], [ "BRKH_INT_SS6E2", "SS6E2" ], [ "BRKH_INT_SS6E3", "SS6E3" ], [ "BRKH_INT_SS6END0", "SS6END0" ], [ "BRKH_INT_SS6END1", "SS6END1" ], [ "BRKH_INT_SS6END2", "SS6END2" ], [ "BRKH_INT_SS6END3", "SS6END3" ], [ "BRKH_INT_SS6END_N0_3", "SS6END3" ], [ "BRKH_INT_SW2A0", "SW2A0" ], [ "BRKH_INT_SW2A1", "SW2A1" ], [ "BRKH_INT_SW2A2", "SW2A2" ], [ "BRKH_INT_SW2A3", "SW2A3" ], [ "BRKH_INT_SW2END3", "SW2END3" ], [ "BRKH_INT_SW6B0", "SW6B0" ], [ "BRKH_INT_SW6B1", "SW6B1" ], [ "BRKH_INT_SW6B2", "SW6B2" ], [ "BRKH_INT_SW6B3", "SW6B3" ], [ "BRKH_INT_SW6C0", "SW6C0" ], [ "BRKH_INT_SW6C1", "SW6C1" ], [ "BRKH_INT_SW6C2", "SW6C2" ], [ "BRKH_INT_SW6C3", "SW6C3" ], [ "BRKH_INT_SW6D0", "SW6D0" ], [ "BRKH_INT_SW6D1", "SW6D1" ], [ "BRKH_INT_SW6D2", "SW6D2" ], [ "BRKH_INT_SW6D3", "SW6D3" ], [ "BRKH_INT_SW6E0", "SW6E0" ], [ "BRKH_INT_SW6E1", "SW6E1" ], [ "BRKH_INT_SW6E2", "SW6E2" ], [ "BRKH_INT_SW6E3", "SW6E3" ], [ "BRKH_INT_SW6END3", "SW6END3" ], [ "BRKH_INT_WL1BEG3", "WL1BEG3" ], [ "BRKH_INT_WL1END3", "WL1END3" ], [ "BRKH_INT_WR1BEG_S0", "WR1BEG_S0" ], [ "BRKH_INT_WR1END_S1_0", "WR1END_S1_0" ], [ "BRKH_INT_WW2END3", "WW2END3" ], [ "BRKH_INT_WW4END_S0_0", "WW4END_S0_0" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "BRKH_TERM_INT", "INT_L" ], "wire_pairs": [ [ "T_TERM_UTURN_INT_ER1BEG_S0", "EL1BEG3" ], [ "T_TERM_UTURN_INT_ER1BEG_S0", "ER1BEG_S0" ], [ "T_TERM_UTURN_INT_ER1END3", "EL1END_S3_0" ], [ "T_TERM_UTURN_INT_ER1END3", "ER1END3" ], [ "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", "BYP_BOUNCE7" ], [ "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", "FAN_BOUNCE_S3_0" ], [ "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", "BYP_BOUNCE3" ], [ "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", "FAN_BOUNCE_S3_2" ], [ "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", "BYP_BOUNCE6" ], [ "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", "FAN_BOUNCE_S3_4" ], [ "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", "BYP_BOUNCE2" ], [ "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", "FAN_BOUNCE_S3_6" ], [ "T_TERM_UTURN_INT_LVB_L0", "LVB_L0" ], [ "T_TERM_UTURN_INT_LVB_L0", "LVB_L11" ], [ "T_TERM_UTURN_INT_LVB_L1", "LVB_L1" ], [ "T_TERM_UTURN_INT_LVB_L1", "LVB_L10" ], [ "T_TERM_UTURN_INT_LVB_L2", "LVB_L2" ], [ "T_TERM_UTURN_INT_LVB_L2", "LVB_L9" ], [ "T_TERM_UTURN_INT_LVB_L3", "LVB_L3" ], [ "T_TERM_UTURN_INT_LVB_L3", "LVB_L8" ], [ "T_TERM_UTURN_INT_LVB_L4", "LVB_L4" ], [ "T_TERM_UTURN_INT_LVB_L4", "LVB_L7" ], [ "T_TERM_UTURN_INT_LVB_L5", "LVB_L5" ], [ "T_TERM_UTURN_INT_LVB_L5", "LVB_L6" ], [ "T_TERM_UTURN_INT_LV_L2", "LV_L2" ], [ "T_TERM_UTURN_INT_LV_L2", "LV_L15" ], [ "T_TERM_UTURN_INT_LV_L3", "LV_L3" ], [ "T_TERM_UTURN_INT_LV_L3", "LV_L14" ], [ "T_TERM_UTURN_INT_LV_L4", "LV_L4" ], [ "T_TERM_UTURN_INT_LV_L4", "LV_L13" ], [ "T_TERM_UTURN_INT_LV_L5", "LV_L5" ], [ "T_TERM_UTURN_INT_LV_L5", "LV_L12" ], [ "T_TERM_UTURN_INT_LV_L6", "LV_L6" ], [ "T_TERM_UTURN_INT_LV_L6", "LV_L11" ], [ "T_TERM_UTURN_INT_LV_L7", "LV_L7" ], [ "T_TERM_UTURN_INT_LV_L7", "LV_L10" ], [ "T_TERM_UTURN_INT_LV_L9", "LV_L8" ], [ "T_TERM_UTURN_INT_LV_L9", "LV_L9" ], [ "T_TERM_UTURN_INT_LV_L16", "LV_L1" ], [ "T_TERM_UTURN_INT_LV_L16", "LV_L16" ], [ "T_TERM_UTURN_INT_LV_L17", "LV_L0" ], [ "T_TERM_UTURN_INT_LV_L17", "LV_L17" ], [ "T_TERM_UTURN_INT_SE2A0", "NE2BEG3" ], [ "T_TERM_UTURN_INT_SE2A0", "SE2A0" ], [ "T_TERM_UTURN_INT_SE2A1", "NE2BEG2" ], [ "T_TERM_UTURN_INT_SE2A1", "SE2A1" ], [ "T_TERM_UTURN_INT_SE2A2", "NE2BEG1" ], [ "T_TERM_UTURN_INT_SE2A2", "SE2A2" ], [ "T_TERM_UTURN_INT_SE2A3", "NE2BEG0" ], [ "T_TERM_UTURN_INT_SE2A3", "SE2A3" ], [ "T_TERM_UTURN_INT_SE6B0", "NE6A3" ], [ "T_TERM_UTURN_INT_SE6B0", "SE6B0" ], [ "T_TERM_UTURN_INT_SE6B1", "NE6A2" ], [ "T_TERM_UTURN_INT_SE6B1", "SE6B1" ], [ "T_TERM_UTURN_INT_SE6B2", "NE6A1" ], [ "T_TERM_UTURN_INT_SE6B2", "SE6B2" ], [ "T_TERM_UTURN_INT_SE6B3", "NE6A0" ], [ "T_TERM_UTURN_INT_SE6B3", "SE6B3" ], [ "T_TERM_UTURN_INT_SE6C0", "NE6B3" ], [ "T_TERM_UTURN_INT_SE6C0", "SE6C0" ], [ "T_TERM_UTURN_INT_SE6C1", "NE6B2" ], [ "T_TERM_UTURN_INT_SE6C1", "SE6C1" ], [ "T_TERM_UTURN_INT_SE6C2", "NE6B1" ], [ "T_TERM_UTURN_INT_SE6C2", "SE6C2" ], [ "T_TERM_UTURN_INT_SE6C3", "NE6B0" ], [ "T_TERM_UTURN_INT_SE6C3", "SE6C3" ], [ "T_TERM_UTURN_INT_SE6D0", "NE6C3" ], [ "T_TERM_UTURN_INT_SE6D0", "SE6D0" ], [ "T_TERM_UTURN_INT_SE6D1", "NE6C2" ], [ "T_TERM_UTURN_INT_SE6D1", "SE6D1" ], [ "T_TERM_UTURN_INT_SE6D2", "NE6C1" ], [ "T_TERM_UTURN_INT_SE6D2", "SE6D2" ], [ "T_TERM_UTURN_INT_SE6D3", "NE6C0" ], [ "T_TERM_UTURN_INT_SE6D3", "SE6D3" ], [ "T_TERM_UTURN_INT_SE6E0", "NE6D3" ], [ "T_TERM_UTURN_INT_SE6E0", "SE6E0" ], [ "T_TERM_UTURN_INT_SE6E1", "NE6D2" ], [ "T_TERM_UTURN_INT_SE6E1", "SE6E1" ], [ "T_TERM_UTURN_INT_SE6E2", "NE6D1" ], [ "T_TERM_UTURN_INT_SE6E2", "SE6E2" ], [ "T_TERM_UTURN_INT_SE6E3", "NE6D0" ], [ "T_TERM_UTURN_INT_SE6E3", "SE6E3" ], [ "T_TERM_UTURN_INT_SL1END0_SLOW", "NR1BEG3" ], [ "T_TERM_UTURN_INT_SL1END0_SLOW", "SL1END0" ], [ "T_TERM_UTURN_INT_SL1END1_SLOW", "NR1BEG2" ], [ "T_TERM_UTURN_INT_SL1END1_SLOW", "SL1END1" ], [ "T_TERM_UTURN_INT_SL1END2_SLOW", "NR1BEG1" ], [ "T_TERM_UTURN_INT_SL1END2_SLOW", "SL1END2" ], [ "T_TERM_UTURN_INT_SL1END3_SLOW", "NR1BEG0" ], [ "T_TERM_UTURN_INT_SL1END3_SLOW", "SL1END3" ], [ "T_TERM_UTURN_INT_SR1END1_SLOW", "NL1BEG2" ], [ "T_TERM_UTURN_INT_SR1END1_SLOW", "SR1END1" ], [ "T_TERM_UTURN_INT_SR1END2_SLOW", "NL1BEG1" ], [ "T_TERM_UTURN_INT_SR1END2_SLOW", "SR1END2" ], [ "T_TERM_UTURN_INT_SR1END3_SLOW", "NL1BEG0" ], [ "T_TERM_UTURN_INT_SR1END3_SLOW", "SR1END3" ], [ "T_TERM_UTURN_INT_SS2A0", "NN2BEG3" ], [ "T_TERM_UTURN_INT_SS2A0", "SS2A0" ], [ "T_TERM_UTURN_INT_SS2A1", "NN2BEG2" ], [ "T_TERM_UTURN_INT_SS2A1", "SS2A1" ], [ "T_TERM_UTURN_INT_SS2A2", "NN2BEG1" ], [ "T_TERM_UTURN_INT_SS2A2", "SS2A2" ], [ "T_TERM_UTURN_INT_SS2A3", "NN2BEG0" ], [ "T_TERM_UTURN_INT_SS2A3", "SS2A3" ], [ "T_TERM_UTURN_INT_SS2END0", "NN2A3" ], [ "T_TERM_UTURN_INT_SS2END0", "SS2END0" ], [ "T_TERM_UTURN_INT_SS2END1", "NN2A2" ], [ "T_TERM_UTURN_INT_SS2END1", "SS2END1" ], [ "T_TERM_UTURN_INT_SS2END2", "NN2A1" ], [ "T_TERM_UTURN_INT_SS2END2", "SS2END2" ], [ "T_TERM_UTURN_INT_SS2END3", "NN2A0" ], [ "T_TERM_UTURN_INT_SS2END3", "SS2END3" ], [ "T_TERM_UTURN_INT_SS6A0", "NN6BEG3" ], [ "T_TERM_UTURN_INT_SS6A0", "SS6A0" ], [ "T_TERM_UTURN_INT_SS6A1", "NN6BEG2" ], [ "T_TERM_UTURN_INT_SS6A1", "SS6A1" ], [ "T_TERM_UTURN_INT_SS6A2", "NN6BEG1" ], [ "T_TERM_UTURN_INT_SS6A2", "SS6A2" ], [ "T_TERM_UTURN_INT_SS6A3", "NN6BEG0" ], [ "T_TERM_UTURN_INT_SS6A3", "SS6A3" ], [ "T_TERM_UTURN_INT_SS6B0", "NN6A3" ], [ "T_TERM_UTURN_INT_SS6B0", "SS6B0" ], [ "T_TERM_UTURN_INT_SS6B1", "NN6A2" ], [ "T_TERM_UTURN_INT_SS6B1", "SS6B1" ], [ "T_TERM_UTURN_INT_SS6B2", "NN6A1" ], [ "T_TERM_UTURN_INT_SS6B2", "SS6B2" ], [ "T_TERM_UTURN_INT_SS6B3", "NN6A0" ], [ "T_TERM_UTURN_INT_SS6B3", "SS6B3" ], [ "T_TERM_UTURN_INT_SS6C0", "NN6B3" ], [ "T_TERM_UTURN_INT_SS6C0", "SS6C0" ], [ "T_TERM_UTURN_INT_SS6C1", "NN6B2" ], [ "T_TERM_UTURN_INT_SS6C1", "SS6C1" ], [ "T_TERM_UTURN_INT_SS6C2", "NN6B1" ], [ "T_TERM_UTURN_INT_SS6C2", "SS6C2" ], [ "T_TERM_UTURN_INT_SS6C3", "NN6B0" ], [ "T_TERM_UTURN_INT_SS6C3", "SS6C3" ], [ "T_TERM_UTURN_INT_SS6D0", "NN6C3" ], [ "T_TERM_UTURN_INT_SS6D0", "SS6D0" ], [ "T_TERM_UTURN_INT_SS6D1", "NN6C2" ], [ "T_TERM_UTURN_INT_SS6D1", "SS6D1" ], [ "T_TERM_UTURN_INT_SS6D2", "NN6C1" ], [ "T_TERM_UTURN_INT_SS6D2", "SS6D2" ], [ "T_TERM_UTURN_INT_SS6D3", "NN6C0" ], [ "T_TERM_UTURN_INT_SS6D3", "SS6D3" ], [ "T_TERM_UTURN_INT_SS6E0", "NN6D3" ], [ "T_TERM_UTURN_INT_SS6E0", "SS6E0" ], [ "T_TERM_UTURN_INT_SS6E1", "NN6D2" ], [ "T_TERM_UTURN_INT_SS6E1", "SS6E1" ], [ "T_TERM_UTURN_INT_SS6E2", "NN6D1" ], [ "T_TERM_UTURN_INT_SS6E2", "SS6E2" ], [ "T_TERM_UTURN_INT_SS6E3", "NN6D0" ], [ "T_TERM_UTURN_INT_SS6E3", "SS6E3" ], [ "T_TERM_UTURN_INT_SS6END0", "NN6E3" ], [ "T_TERM_UTURN_INT_SS6END0", "SS6END0" ], [ "T_TERM_UTURN_INT_SS6END1", "NN6E2" ], [ "T_TERM_UTURN_INT_SS6END1", "SS6END1" ], [ "T_TERM_UTURN_INT_SS6END2", "NN6E1" ], [ "T_TERM_UTURN_INT_SS6END2", "SS6END2" ], [ "T_TERM_UTURN_INT_SS6END3", "NN6E0" ], [ "T_TERM_UTURN_INT_SS6END3", "SS6END3" ], [ "T_TERM_UTURN_INT_SW2A0", "NW2BEG3" ], [ "T_TERM_UTURN_INT_SW2A0", "SW2A0" ], [ "T_TERM_UTURN_INT_SW2A1", "NW2BEG2" ], [ "T_TERM_UTURN_INT_SW2A1", "SW2A1" ], [ "T_TERM_UTURN_INT_SW2A2", "NW2BEG1" ], [ "T_TERM_UTURN_INT_SW2A2", "SW2A2" ], [ "T_TERM_UTURN_INT_SW2A3", "NW2BEG0" ], [ "T_TERM_UTURN_INT_SW2A3", "SW2A3" ], [ "T_TERM_UTURN_INT_SW6B0", "NW6A3" ], [ "T_TERM_UTURN_INT_SW6B0", "SW6B0" ], [ "T_TERM_UTURN_INT_SW6B1", "NW6A2" ], [ "T_TERM_UTURN_INT_SW6B1", "SW6B1" ], [ "T_TERM_UTURN_INT_SW6B2", "NW6A1" ], [ "T_TERM_UTURN_INT_SW6B2", "SW6B2" ], [ "T_TERM_UTURN_INT_SW6B3", "NW6A0" ], [ "T_TERM_UTURN_INT_SW6B3", "SW6B3" ], [ "T_TERM_UTURN_INT_SW6C0", "NW6B3" ], [ "T_TERM_UTURN_INT_SW6C0", "SW6C0" ], [ "T_TERM_UTURN_INT_SW6C1", "NW6B2" ], [ "T_TERM_UTURN_INT_SW6C1", "SW6C1" ], [ "T_TERM_UTURN_INT_SW6C2", "NW6B1" ], [ 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], "wire_pairs": [ [ "T_TERM_INT_UTURN_LV_R2", "LV2" ], [ "T_TERM_INT_UTURN_LV_R2", "LV15" ], [ "T_TERM_INT_UTURN_LV_R3", "LV3" ], [ "T_TERM_INT_UTURN_LV_R3", "LV14" ], [ "T_TERM_INT_UTURN_LV_R4", "LV4" ], [ "T_TERM_INT_UTURN_LV_R4", "LV13" ], [ "T_TERM_INT_UTURN_LV_R5", "LV5" ], [ "T_TERM_INT_UTURN_LV_R5", "LV12" ], [ "T_TERM_INT_UTURN_LV_R6", "LV6" ], [ "T_TERM_INT_UTURN_LV_R6", "LV11" ], [ "T_TERM_INT_UTURN_LV_R7", "LV7" ], [ "T_TERM_INT_UTURN_LV_R7", "LV10" ], [ "T_TERM_INT_UTURN_LV_R9", "LV8" ], [ "T_TERM_INT_UTURN_LV_R9", "LV9" ], [ "T_TERM_INT_UTURN_LV_R16", "LV1" ], [ "T_TERM_INT_UTURN_LV_R16", "LV16" ], [ "T_TERM_INT_UTURN_LV_R17", "LV0" ], [ "T_TERM_INT_UTURN_LV_R17", "LV17" ], [ "T_TERM_UTURN_INT_ER1BEG_S0", "EL1BEG3" ], [ "T_TERM_UTURN_INT_ER1BEG_S0", "ER1BEG_S0" ], [ "T_TERM_UTURN_INT_ER1END3", "EL1END_S3_0" ], [ "T_TERM_UTURN_INT_ER1END3", "ER1END3" ], [ "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", "BYP_BOUNCE7" ], [ "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", "FAN_BOUNCE_S3_0" ], [ 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"CLBLL_WW4B2", "CLBLM_WW4B2" ], [ "CLBLL_WW4B3", "CLBLM_WW4B3" ], [ "CLBLL_WW4C0", "CLBLM_WW4C0" ], [ "CLBLL_WW4C1", "CLBLM_WW4C1" ], [ "CLBLL_WW4C2", "CLBLM_WW4C2" ], [ "CLBLL_WW4C3", "CLBLM_WW4C3" ], [ "CLBLL_WW4END0", "CLBLM_WW4END0" ], [ "CLBLL_WW4END1", "CLBLM_WW4END1" ], [ "CLBLL_WW4END2", "CLBLM_WW4END2" ], [ "CLBLL_WW4END3", "CLBLM_WW4END3" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "CLBLL_L", "HCLK_CLB" ], "wire_pairs": [ [ "CLBLL_LL_COUT_N", "HCLK_CLB_COUT0_L" ], [ "CLBLL_L_COUT_N", "HCLK_CLB_COUT1_L" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "CLBLL_L", "HCLK_CLB" ], "wire_pairs": [ [ "CLBLL_LL_CIN", "HCLK_CLB_COUT0_L" ], [ "CLBLL_L_CIN", "HCLK_CLB_COUT1_L" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLBLL_L", "INT_L" ], "wire_pairs": [ [ "CLBLL_BYP0", "BYP_L0" ], [ "CLBLL_BYP1", "BYP_L1" ], [ "CLBLL_BYP2", "BYP_L2" ], [ "CLBLL_BYP3", "BYP_L3" ], [ "CLBLL_BYP4", "BYP_L4" ], [ "CLBLL_BYP5", "BYP_L5" ], [ "CLBLL_BYP6", "BYP_L6" ], [ "CLBLL_BYP7", "BYP_L7" ], [ "CLBLL_CLK0", "CLK_L0" ], [ "CLBLL_CLK1", "CLK_L1" ], [ "CLBLL_CTRL0", "CTRL_L0" ], [ "CLBLL_CTRL1", "CTRL_L1" ], [ "CLBLL_EE2A0", "EE2END0" ], [ "CLBLL_EE2A1", "EE2END1" ], [ "CLBLL_EE2A2", "EE2END2" ], [ "CLBLL_EE2A3", "EE2END3" ], [ "CLBLL_EE2BEG0", "EE2A0" ], [ "CLBLL_EE2BEG1", "EE2A1" ], [ "CLBLL_EE2BEG2", "EE2A2" ], [ "CLBLL_EE2BEG3", "EE2A3" ], [ "CLBLL_EE4A0", "EE4B0" ], [ "CLBLL_EE4A1", "EE4B1" ], [ "CLBLL_EE4A2", "EE4B2" ], [ "CLBLL_EE4A3", "EE4B3" ], [ "CLBLL_EE4B0", "EE4C0" ], [ "CLBLL_EE4B1", "EE4C1" ], [ "CLBLL_EE4B2", "EE4C2" ], [ "CLBLL_EE4B3", "EE4C3" ], [ "CLBLL_EE4BEG0", "EE4A0" ], [ "CLBLL_EE4BEG1", "EE4A1" ], [ "CLBLL_EE4BEG2", "EE4A2" ], [ "CLBLL_EE4BEG3", "EE4A3" ], [ "CLBLL_EE4C0", "EE4END0" ], [ "CLBLL_EE4C1", "EE4END1" ], [ "CLBLL_EE4C2", "EE4END2" ], [ "CLBLL_EE4C3", "EE4END3" ], [ "CLBLL_EL1BEG0", "EL1END0" ], [ "CLBLL_EL1BEG1", "EL1END1" ], [ "CLBLL_EL1BEG2", "EL1END2" ], [ "CLBLL_EL1BEG3", "EL1END3" ], [ "CLBLL_ER1BEG0", "ER1END0" ], [ "CLBLL_ER1BEG1", "ER1END1" ], [ "CLBLL_ER1BEG2", "ER1END2" ], [ "CLBLL_ER1BEG3", "ER1END3" ], [ "CLBLL_FAN0", "FAN_L0" ], [ "CLBLL_FAN1", "FAN_L1" ], [ "CLBLL_FAN2", "FAN_L2" ], [ "CLBLL_FAN3", "FAN_L3" ], [ "CLBLL_FAN4", "FAN_L4" ], [ "CLBLL_FAN5", "FAN_L5" ], [ "CLBLL_FAN6", "FAN_L6" ], [ "CLBLL_FAN7", "FAN_L7" ], [ "CLBLL_IMUX0", "IMUX_L0" ], [ "CLBLL_IMUX1", "IMUX_L1" ], [ "CLBLL_IMUX2", "IMUX_L2" ], [ "CLBLL_IMUX3", "IMUX_L3" ], [ "CLBLL_IMUX4", "IMUX_L4" ], [ "CLBLL_IMUX5", "IMUX_L5" ], [ "CLBLL_IMUX6", "IMUX_L6" ], [ "CLBLL_IMUX7", "IMUX_L7" ], [ "CLBLL_IMUX8", "IMUX_L8" ], [ "CLBLL_IMUX9", "IMUX_L9" ], [ "CLBLL_IMUX10", "IMUX_L10" ], [ "CLBLL_IMUX11", "IMUX_L11" ], [ "CLBLL_IMUX12", "IMUX_L12" ], [ "CLBLL_IMUX13", "IMUX_L13" ], [ "CLBLL_IMUX14", "IMUX_L14" ], [ "CLBLL_IMUX15", "IMUX_L15" ], [ "CLBLL_IMUX16", "IMUX_L16" ], [ "CLBLL_IMUX17", "IMUX_L17" ], [ "CLBLL_IMUX18", "IMUX_L18" ], [ "CLBLL_IMUX19", "IMUX_L19" ], [ "CLBLL_IMUX20", "IMUX_L20" ], [ "CLBLL_IMUX21", "IMUX_L21" ], [ "CLBLL_IMUX22", "IMUX_L22" ], [ "CLBLL_IMUX23", "IMUX_L23" ], [ "CLBLL_IMUX24", "IMUX_L24" ], [ "CLBLL_IMUX25", "IMUX_L25" ], [ "CLBLL_IMUX26", "IMUX_L26" ], [ "CLBLL_IMUX27", "IMUX_L27" ], [ "CLBLL_IMUX28", "IMUX_L28" ], [ "CLBLL_IMUX29", "IMUX_L29" ], [ "CLBLL_IMUX30", "IMUX_L30" ], [ "CLBLL_IMUX31", "IMUX_L31" ], [ "CLBLL_IMUX32", "IMUX_L32" ], [ "CLBLL_IMUX33", "IMUX_L33" ], [ "CLBLL_IMUX34", "IMUX_L34" ], [ "CLBLL_IMUX35", "IMUX_L35" ], [ "CLBLL_IMUX36", "IMUX_L36" ], [ "CLBLL_IMUX37", "IMUX_L37" ], [ "CLBLL_IMUX38", "IMUX_L38" ], [ "CLBLL_IMUX39", "IMUX_L39" ], [ "CLBLL_IMUX40", "IMUX_L40" ], [ "CLBLL_IMUX41", "IMUX_L41" ], [ "CLBLL_IMUX42", "IMUX_L42" ], [ "CLBLL_IMUX43", "IMUX_L43" ], [ "CLBLL_IMUX44", "IMUX_L44" ], [ "CLBLL_IMUX45", "IMUX_L45" ], [ "CLBLL_IMUX46", "IMUX_L46" ], [ "CLBLL_IMUX47", "IMUX_L47" ], [ "CLBLL_LH1", "LH0" ], [ "CLBLL_LH2", "LH1" ], [ "CLBLL_LH3", "LH2" ], [ "CLBLL_LH4", "LH3" ], [ "CLBLL_LH5", "LH4" ], [ "CLBLL_LH6", "LH5" ], [ "CLBLL_LH7", "LH6" ], [ "CLBLL_LH8", "LH7" ], [ "CLBLL_LH9", "LH8" ], [ "CLBLL_LH10", "LH9" ], [ "CLBLL_LH11", "LH10" ], [ "CLBLL_LH12", "LH11" ], [ "CLBLL_LOGIC_OUTS0", "LOGIC_OUTS_L0" ], [ "CLBLL_LOGIC_OUTS1", "LOGIC_OUTS_L1" ], [ "CLBLL_LOGIC_OUTS2", "LOGIC_OUTS_L2" ], [ "CLBLL_LOGIC_OUTS3", "LOGIC_OUTS_L3" ], [ "CLBLL_LOGIC_OUTS4", "LOGIC_OUTS_L4" ], [ "CLBLL_LOGIC_OUTS5", "LOGIC_OUTS_L5" ], [ "CLBLL_LOGIC_OUTS6", "LOGIC_OUTS_L6" ], [ "CLBLL_LOGIC_OUTS7", "LOGIC_OUTS_L7" ], [ "CLBLL_LOGIC_OUTS8", "LOGIC_OUTS_L8" ], [ "CLBLL_LOGIC_OUTS9", "LOGIC_OUTS_L9" ], [ "CLBLL_LOGIC_OUTS10", "LOGIC_OUTS_L10" ], [ "CLBLL_LOGIC_OUTS11", "LOGIC_OUTS_L11" ], [ "CLBLL_LOGIC_OUTS12", "LOGIC_OUTS_L12" ], [ "CLBLL_LOGIC_OUTS13", "LOGIC_OUTS_L13" ], [ "CLBLL_LOGIC_OUTS14", "LOGIC_OUTS_L14" ], [ "CLBLL_LOGIC_OUTS15", "LOGIC_OUTS_L15" ], [ "CLBLL_LOGIC_OUTS16", "LOGIC_OUTS_L16" ], [ "CLBLL_LOGIC_OUTS17", "LOGIC_OUTS_L17" ], [ "CLBLL_LOGIC_OUTS18", "LOGIC_OUTS_L18" ], [ "CLBLL_LOGIC_OUTS19", "LOGIC_OUTS_L19" ], [ "CLBLL_LOGIC_OUTS20", "LOGIC_OUTS_L20" ], [ "CLBLL_LOGIC_OUTS21", "LOGIC_OUTS_L21" ], [ "CLBLL_LOGIC_OUTS22", "LOGIC_OUTS_L22" ], [ "CLBLL_LOGIC_OUTS23", "LOGIC_OUTS_L23" ], [ "CLBLL_MONITOR_N", "MONITOR_N" ], [ "CLBLL_MONITOR_P", "MONITOR_P" ], [ "CLBLL_NE2A0", "NE2END0" ], [ "CLBLL_NE2A1", "NE2END1" ], [ "CLBLL_NE2A2", "NE2END2" ], [ "CLBLL_NE2A3", "NE2END3" ], [ "CLBLL_NE4BEG0", "NE6A0" ], [ "CLBLL_NE4BEG1", "NE6A1" ], [ "CLBLL_NE4BEG2", "NE6A2" ], [ "CLBLL_NE4BEG3", "NE6A3" ], [ "CLBLL_NE4C0", "NE6END0" ], [ "CLBLL_NE4C1", "NE6END1" ], [ "CLBLL_NE4C2", "NE6END2" ], [ "CLBLL_NE4C3", "NE6END3" ], [ "CLBLL_NW2A0", "NW2A0" ], [ "CLBLL_NW2A1", "NW2A1" ], [ "CLBLL_NW2A2", "NW2A2" ], [ "CLBLL_NW2A3", "NW2A3" ], [ "CLBLL_NW4A0", "NW6BEG0" ], [ "CLBLL_NW4A1", "NW6BEG1" ], [ "CLBLL_NW4A2", "NW6BEG2" ], [ "CLBLL_NW4A3", "NW6BEG3" ], [ "CLBLL_NW4END0", "NW6E0" ], [ "CLBLL_NW4END1", "NW6E1" ], [ "CLBLL_NW4END2", "NW6E2" ], [ "CLBLL_NW4END3", "NW6E3" ], [ "CLBLL_SE2A0", "SE2END0" ], [ "CLBLL_SE2A1", "SE2END1" ], [ "CLBLL_SE2A2", "SE2END2" ], [ "CLBLL_SE2A3", "SE2END3" ], [ "CLBLL_SE4BEG0", "SE6A0" ], [ "CLBLL_SE4BEG1", "SE6A1" ], [ "CLBLL_SE4BEG2", "SE6A2" ], [ "CLBLL_SE4BEG3", "SE6A3" ], [ "CLBLL_SE4C0", "SE6END0" ], [ "CLBLL_SE4C1", "SE6END1" ], [ "CLBLL_SE4C2", "SE6END2" ], [ "CLBLL_SE4C3", "SE6END3" ], [ "CLBLL_SW2A0", "SW2A0" ], [ "CLBLL_SW2A1", "SW2A1" ], [ "CLBLL_SW2A2", "SW2A2" ], [ "CLBLL_SW2A3", "SW2A3" ], [ "CLBLL_SW4A0", "SW6BEG0" ], [ "CLBLL_SW4A1", "SW6BEG1" ], [ "CLBLL_SW4A2", "SW6BEG2" ], [ "CLBLL_SW4A3", "SW6BEG3" ], [ "CLBLL_SW4END0", "SW6E0" ], [ "CLBLL_SW4END1", "SW6E1" ], [ "CLBLL_SW4END2", "SW6E2" ], [ "CLBLL_SW4END3", "SW6E3" ], [ "CLBLL_WL1END0", "WL1BEG0" ], [ "CLBLL_WL1END1", "WL1BEG1" ], [ "CLBLL_WL1END2", "WL1BEG2" ], [ "CLBLL_WL1END3", "WL1BEG3" ], [ "CLBLL_WR1END0", "WR1BEG0" ], [ "CLBLL_WR1END1", "WR1BEG1" ], [ "CLBLL_WR1END2", "WR1BEG2" ], [ "CLBLL_WR1END3", "WR1BEG3" ], [ "CLBLL_WW2A0", "WW2BEG0" ], [ "CLBLL_WW2A1", "WW2BEG1" ], [ "CLBLL_WW2A2", "WW2BEG2" ], [ "CLBLL_WW2A3", "WW2BEG3" ], [ "CLBLL_WW2END0", "WW2A0" ], [ "CLBLL_WW2END1", "WW2A1" ], [ "CLBLL_WW2END2", "WW2A2" ], [ "CLBLL_WW2END3", "WW2A3" ], [ "CLBLL_WW4A0", "WW4BEG0" ], [ "CLBLL_WW4A1", "WW4BEG1" ], [ "CLBLL_WW4A2", "WW4BEG2" ], [ "CLBLL_WW4A3", "WW4BEG3" ], [ "CLBLL_WW4B0", "WW4A0" ], [ "CLBLL_WW4B1", "WW4A1" ], [ "CLBLL_WW4B2", "WW4A2" ], [ "CLBLL_WW4B3", "WW4A3" ], [ "CLBLL_WW4C0", "WW4B0" ], [ "CLBLL_WW4C1", "WW4B1" ], [ "CLBLL_WW4C2", "WW4B2" ], [ "CLBLL_WW4C3", "WW4B3" ], [ "CLBLL_WW4END0", "WW4C0" ], [ "CLBLL_WW4END1", "WW4C1" ], [ "CLBLL_WW4END2", "WW4C2" ], [ "CLBLL_WW4END3", "WW4C3" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "CLBLL_L", "VBRK" ], "wire_pairs": [ [ "CLBLL_EE2A0", "VBRK_EE2A0" ], [ "CLBLL_EE2A1", "VBRK_EE2A1" ], [ "CLBLL_EE2A2", "VBRK_EE2A2" ], [ "CLBLL_EE2A3", "VBRK_EE2A3" ], [ "CLBLL_EE2BEG0", "VBRK_EE2BEG0" ], [ "CLBLL_EE2BEG1", "VBRK_EE2BEG1" ], [ "CLBLL_EE2BEG2", "VBRK_EE2BEG2" ], [ "CLBLL_EE2BEG3", "VBRK_EE2BEG3" ], [ "CLBLL_EE4A0", "VBRK_EE4A0" ], [ "CLBLL_EE4A1", "VBRK_EE4A1" ], [ "CLBLL_EE4A2", "VBRK_EE4A2" ], [ "CLBLL_EE4A3", "VBRK_EE4A3" ], [ "CLBLL_EE4B0", "VBRK_EE4B0" ], [ "CLBLL_EE4B1", "VBRK_EE4B1" ], [ "CLBLL_EE4B2", "VBRK_EE4B2" ], [ "CLBLL_EE4B3", "VBRK_EE4B3" ], [ "CLBLL_EE4BEG0", "VBRK_EE4BEG0" ], [ "CLBLL_EE4BEG1", "VBRK_EE4BEG1" ], [ "CLBLL_EE4BEG2", "VBRK_EE4BEG2" ], [ "CLBLL_EE4BEG3", "VBRK_EE4BEG3" ], [ "CLBLL_EE4C0", "VBRK_EE4C0" ], [ "CLBLL_EE4C1", "VBRK_EE4C1" ], [ "CLBLL_EE4C2", "VBRK_EE4C2" ], [ "CLBLL_EE4C3", "VBRK_EE4C3" ], [ "CLBLL_EL1BEG0", "VBRK_EL1BEG0" ], [ "CLBLL_EL1BEG1", "VBRK_EL1BEG1" ], [ "CLBLL_EL1BEG2", "VBRK_EL1BEG2" ], [ "CLBLL_EL1BEG3", "VBRK_EL1BEG3" ], [ "CLBLL_ER1BEG0", "VBRK_ER1BEG0" ], [ "CLBLL_ER1BEG1", "VBRK_ER1BEG1" ], [ "CLBLL_ER1BEG2", "VBRK_ER1BEG2" ], [ "CLBLL_ER1BEG3", "VBRK_ER1BEG3" ], [ "CLBLL_LH1", "VBRK_LH1" ], [ "CLBLL_LH2", "VBRK_LH2" ], [ "CLBLL_LH3", "VBRK_LH3" ], [ "CLBLL_LH4", "VBRK_LH4" ], [ "CLBLL_LH5", "VBRK_LH5" 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"CLBLM_LOGIC_OUTS17", "LOGIC_OUTS17" ], [ "CLBLM_LOGIC_OUTS18", "LOGIC_OUTS18" ], [ "CLBLM_LOGIC_OUTS19", "LOGIC_OUTS19" ], [ "CLBLM_LOGIC_OUTS20", "LOGIC_OUTS20" ], [ "CLBLM_LOGIC_OUTS21", "LOGIC_OUTS21" ], [ "CLBLM_LOGIC_OUTS22", "LOGIC_OUTS22" ], [ "CLBLM_LOGIC_OUTS23", "LOGIC_OUTS23" ], [ "CLBLM_MONITOR_N", "MONITOR_N" ], [ "CLBLM_MONITOR_P", "MONITOR_P" ], [ "CLBLM_NE2A0", "NE2A0" ], [ "CLBLM_NE2A1", "NE2A1" ], [ "CLBLM_NE2A2", "NE2A2" ], [ "CLBLM_NE2A3", "NE2A3" ], [ "CLBLM_NE4BEG0", "NE6BEG0" ], [ "CLBLM_NE4BEG1", "NE6BEG1" ], [ "CLBLM_NE4BEG2", "NE6BEG2" ], [ "CLBLM_NE4BEG3", "NE6BEG3" ], [ "CLBLM_NE4C0", "NE6E0" ], [ "CLBLM_NE4C1", "NE6E1" ], [ "CLBLM_NE4C2", "NE6E2" ], [ "CLBLM_NE4C3", "NE6E3" ], [ "CLBLM_NW2A0", "NW2END0" ], [ "CLBLM_NW2A1", "NW2END1" ], [ "CLBLM_NW2A2", "NW2END2" ], [ "CLBLM_NW2A3", "NW2END3" ], [ "CLBLM_NW4A0", "NW6A0" ], [ "CLBLM_NW4A1", "NW6A1" ], [ "CLBLM_NW4A2", "NW6A2" ], [ "CLBLM_NW4A3", "NW6A3" ], [ "CLBLM_NW4END0", "NW6END0" ], [ "CLBLM_NW4END1", "NW6END1" ], [ "CLBLM_NW4END2", "NW6END2" ], [ "CLBLM_NW4END3", "NW6END3" ], [ "CLBLM_SE2A0", "SE2A0" ], [ "CLBLM_SE2A1", "SE2A1" ], [ "CLBLM_SE2A2", "SE2A2" ], [ "CLBLM_SE2A3", "SE2A3" ], [ "CLBLM_SE4BEG0", "SE6BEG0" ], [ "CLBLM_SE4BEG1", "SE6BEG1" ], [ "CLBLM_SE4BEG2", "SE6BEG2" ], [ "CLBLM_SE4BEG3", "SE6BEG3" ], [ "CLBLM_SE4C0", "SE6E0" ], [ "CLBLM_SE4C1", "SE6E1" ], [ "CLBLM_SE4C2", "SE6E2" ], [ "CLBLM_SE4C3", "SE6E3" ], [ "CLBLM_SW2A0", "SW2END0" ], [ "CLBLM_SW2A1", "SW2END1" ], [ "CLBLM_SW2A2", "SW2END2" ], [ "CLBLM_SW2A3", "SW2END3" ], [ "CLBLM_SW4A0", "SW6A0" ], [ "CLBLM_SW4A1", "SW6A1" ], [ "CLBLM_SW4A2", "SW6A2" ], [ "CLBLM_SW4A3", "SW6A3" ], [ "CLBLM_SW4END0", "SW6END0" ], [ "CLBLM_SW4END1", "SW6END1" ], [ "CLBLM_SW4END2", "SW6END2" ], [ "CLBLM_SW4END3", "SW6END3" ], [ "CLBLM_WL1END0", "WL1END0" ], [ "CLBLM_WL1END1", "WL1END1" ], [ "CLBLM_WL1END2", "WL1END2" ], [ "CLBLM_WL1END3", "WL1END3" ], [ "CLBLM_WR1END0", "WR1END0" ], [ "CLBLM_WR1END1", "WR1END1" ], [ "CLBLM_WR1END2", "WR1END2" ], [ "CLBLM_WR1END3", "WR1END3" ], [ "CLBLM_WW2A0", "WW2A0" ], [ "CLBLM_WW2A1", "WW2A1" ], [ "CLBLM_WW2A2", "WW2A2" ], [ "CLBLM_WW2A3", "WW2A3" ], [ "CLBLM_WW2END0", "WW2END0" ], [ "CLBLM_WW2END1", "WW2END1" ], [ "CLBLM_WW2END2", "WW2END2" ], [ "CLBLM_WW2END3", "WW2END3" ], [ "CLBLM_WW4A0", "WW4A0" ], [ "CLBLM_WW4A1", "WW4A1" ], [ "CLBLM_WW4A2", "WW4A2" ], [ "CLBLM_WW4A3", "WW4A3" ], [ "CLBLM_WW4B0", "WW4B0" ], [ "CLBLM_WW4B1", "WW4B1" ], [ "CLBLM_WW4B2", "WW4B2" ], [ "CLBLM_WW4B3", "WW4B3" ], [ "CLBLM_WW4C0", "WW4C0" ], [ "CLBLM_WW4C1", "WW4C1" ], [ "CLBLM_WW4C2", "WW4C2" ], [ "CLBLM_WW4C3", "WW4C3" ], [ "CLBLM_WW4END0", "WW4END0" ], [ "CLBLM_WW4END1", "WW4END1" ], [ "CLBLM_WW4END2", "WW4END2" ], [ "CLBLM_WW4END3", "WW4END3" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLBLM_R", "VBRK" ], "wire_pairs": [ [ "CLBLM_EE2A0", "VBRK_EE2A0" ], [ "CLBLM_EE2A1", "VBRK_EE2A1" ], [ "CLBLM_EE2A2", "VBRK_EE2A2" ], [ "CLBLM_EE2A3", "VBRK_EE2A3" ], [ "CLBLM_EE2BEG0", "VBRK_EE2BEG0" ], [ "CLBLM_EE2BEG1", "VBRK_EE2BEG1" ], [ "CLBLM_EE2BEG2", "VBRK_EE2BEG2" ], [ "CLBLM_EE2BEG3", "VBRK_EE2BEG3" ], [ "CLBLM_EE4A0", "VBRK_EE4A0" ], [ "CLBLM_EE4A1", "VBRK_EE4A1" ], [ "CLBLM_EE4A2", "VBRK_EE4A2" ], [ "CLBLM_EE4A3", "VBRK_EE4A3" ], [ "CLBLM_EE4B0", "VBRK_EE4B0" ], [ "CLBLM_EE4B1", "VBRK_EE4B1" ], [ "CLBLM_EE4B2", "VBRK_EE4B2" ], [ "CLBLM_EE4B3", "VBRK_EE4B3" ], [ "CLBLM_EE4BEG0", "VBRK_EE4BEG0" ], [ "CLBLM_EE4BEG1", "VBRK_EE4BEG1" ], [ "CLBLM_EE4BEG2", "VBRK_EE4BEG2" ], [ "CLBLM_EE4BEG3", "VBRK_EE4BEG3" ], [ "CLBLM_EE4C0", "VBRK_EE4C0" ], [ "CLBLM_EE4C1", "VBRK_EE4C1" ], [ "CLBLM_EE4C2", "VBRK_EE4C2" ], [ "CLBLM_EE4C3", "VBRK_EE4C3" ], [ "CLBLM_EL1BEG0", "VBRK_EL1BEG0" ], [ "CLBLM_EL1BEG1", "VBRK_EL1BEG1" ], [ "CLBLM_EL1BEG2", "VBRK_EL1BEG2" ], [ "CLBLM_EL1BEG3", "VBRK_EL1BEG3" ], [ "CLBLM_ER1BEG0", "VBRK_ER1BEG0" ], [ "CLBLM_ER1BEG1", "VBRK_ER1BEG1" ], [ "CLBLM_ER1BEG2", "VBRK_ER1BEG2" ], [ "CLBLM_ER1BEG3", "VBRK_ER1BEG3" ], [ "CLBLM_LH1", "VBRK_LH1" ], [ "CLBLM_LH2", "VBRK_LH2" ], [ "CLBLM_LH3", "VBRK_LH3" ], [ "CLBLM_LH4", "VBRK_LH4" ], [ "CLBLM_LH5", "VBRK_LH5" ], [ "CLBLM_LH6", "VBRK_LH6" ], [ "CLBLM_LH7", "VBRK_LH7" ], [ "CLBLM_LH8", "VBRK_LH8" ], [ "CLBLM_LH9", "VBRK_LH9" ], [ "CLBLM_LH10", "VBRK_LH10" ], [ "CLBLM_LH11", "VBRK_LH11" ], [ "CLBLM_LH12", "VBRK_LH12" ], [ "CLBLM_MONITOR_N", "VBRK_MONITOR_N" ], [ "CLBLM_MONITOR_P", "VBRK_MONITOR_P" ], [ "CLBLM_NE2A0", "VBRK_NE2A0" ], [ "CLBLM_NE2A1", "VBRK_NE2A1" ], [ "CLBLM_NE2A2", "VBRK_NE2A2" ], [ "CLBLM_NE2A3", "VBRK_NE2A3" ], [ "CLBLM_NE4BEG0", "VBRK_NE4BEG0" ], [ "CLBLM_NE4BEG1", "VBRK_NE4BEG1" ], [ "CLBLM_NE4BEG2", "VBRK_NE4BEG2" ], [ "CLBLM_NE4BEG3", "VBRK_NE4BEG3" ], [ "CLBLM_NE4C0", "VBRK_NE4C0" ], [ "CLBLM_NE4C1", "VBRK_NE4C1" ], [ "CLBLM_NE4C2", "VBRK_NE4C2" ], [ "CLBLM_NE4C3", "VBRK_NE4C3" ], [ "CLBLM_NW2A0", "VBRK_NW2A0" ], [ "CLBLM_NW2A1", "VBRK_NW2A1" ], [ "CLBLM_NW2A2", "VBRK_NW2A2" ], [ "CLBLM_NW2A3", "VBRK_NW2A3" ], [ "CLBLM_NW4A0", "VBRK_NW4A0" ], [ "CLBLM_NW4A1", "VBRK_NW4A1" ], [ "CLBLM_NW4A2", "VBRK_NW4A2" ], [ "CLBLM_NW4A3", "VBRK_NW4A3" ], [ "CLBLM_NW4END0", "VBRK_NW4END0" ], [ "CLBLM_NW4END1", "VBRK_NW4END1" ], [ "CLBLM_NW4END2", "VBRK_NW4END2" ], [ "CLBLM_NW4END3", "VBRK_NW4END3" ], [ "CLBLM_SE2A0", "VBRK_SE2A0" ], [ "CLBLM_SE2A1", "VBRK_SE2A1" ], [ "CLBLM_SE2A2", "VBRK_SE2A2" ], [ "CLBLM_SE2A3", "VBRK_SE2A3" ], [ "CLBLM_SE4BEG0", "VBRK_SE4BEG0" ], [ "CLBLM_SE4BEG1", "VBRK_SE4BEG1" ], [ "CLBLM_SE4BEG2", "VBRK_SE4BEG2" ], [ "CLBLM_SE4BEG3", "VBRK_SE4BEG3" ], [ "CLBLM_SE4C0", "VBRK_SE4C0" ], [ "CLBLM_SE4C1", "VBRK_SE4C1" ], [ "CLBLM_SE4C2", "VBRK_SE4C2" ], [ "CLBLM_SE4C3", "VBRK_SE4C3" ], [ "CLBLM_SW2A0", "VBRK_SW2A0" ], [ "CLBLM_SW2A1", "VBRK_SW2A1" ], [ "CLBLM_SW2A2", "VBRK_SW2A2" ], [ "CLBLM_SW2A3", "VBRK_SW2A3" ], [ "CLBLM_SW4A0", "VBRK_SW4A0" ], [ "CLBLM_SW4A1", "VBRK_SW4A1" ], [ "CLBLM_SW4A2", "VBRK_SW4A2" ], [ "CLBLM_SW4A3", "VBRK_SW4A3" ], [ "CLBLM_SW4END0", "VBRK_SW4END0" ], [ "CLBLM_SW4END1", "VBRK_SW4END1" ], [ "CLBLM_SW4END2", "VBRK_SW4END2" ], [ "CLBLM_SW4END3", "VBRK_SW4END3" ], [ "CLBLM_WL1END0", "VBRK_WL1END0" ], [ "CLBLM_WL1END1", "VBRK_WL1END1" ], [ "CLBLM_WL1END2", "VBRK_WL1END2" ], [ "CLBLM_WL1END3", "VBRK_WL1END3" ], [ "CLBLM_WR1END0", "VBRK_WR1END0" ], [ "CLBLM_WR1END1", "VBRK_WR1END1" ], [ "CLBLM_WR1END2", "VBRK_WR1END2" ], [ "CLBLM_WR1END3", "VBRK_WR1END3" ], [ "CLBLM_WW2A0", "VBRK_WW2A0" ], [ "CLBLM_WW2A1", "VBRK_WW2A1" ], [ "CLBLM_WW2A2", "VBRK_WW2A2" ], [ "CLBLM_WW2A3", "VBRK_WW2A3" ], [ "CLBLM_WW2END0", "VBRK_WW2END0" ], [ "CLBLM_WW2END1", "VBRK_WW2END1" ], [ "CLBLM_WW2END2", "VBRK_WW2END2" ], [ "CLBLM_WW2END3", "VBRK_WW2END3" ], [ "CLBLM_WW4A0", "VBRK_WW4A0" ], [ "CLBLM_WW4A1", "VBRK_WW4A1" ], [ "CLBLM_WW4A2", "VBRK_WW4A2" ], [ "CLBLM_WW4A3", "VBRK_WW4A3" ], [ "CLBLM_WW4B0", "VBRK_WW4B0" ], [ "CLBLM_WW4B1", "VBRK_WW4B1" ], [ "CLBLM_WW4B2", "VBRK_WW4B2" ], [ "CLBLM_WW4B3", "VBRK_WW4B3" ], [ "CLBLM_WW4C0", "VBRK_WW4C0" ], [ "CLBLM_WW4C1", "VBRK_WW4C1" ], [ "CLBLM_WW4C2", "VBRK_WW4C2" ], [ "CLBLM_WW4C3", "VBRK_WW4C3" ], [ "CLBLM_WW4END0", "VBRK_WW4END0" ], [ "CLBLM_WW4END1", "VBRK_WW4END1" ], [ "CLBLM_WW4END2", "VBRK_WW4END2" ], [ "CLBLM_WW4END3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "CLK_BUFG_BOT_R", "CLK_MTBF2" ], "wire_pairs": [ [ "CLK_BUFG_BOT_R_CK_MUXED0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ "CLK_BUFG_BOT_R_CK_MUXED1", "CLK_FEED_R_CK_BUFG_CASC1" ], [ "CLK_BUFG_BOT_R_CK_MUXED2", "CLK_FEED_R_CK_BUFG_CASC2" ], [ "CLK_BUFG_BOT_R_CK_MUXED3", "CLK_FEED_R_CK_BUFG_CASC3" ], [ "CLK_BUFG_BOT_R_CK_MUXED4", "CLK_FEED_R_CK_BUFG_CASC4" ], [ "CLK_BUFG_BOT_R_CK_MUXED5", "CLK_FEED_R_CK_BUFG_CASC5" ], [ "CLK_BUFG_BOT_R_CK_MUXED6", "CLK_FEED_R_CK_BUFG_CASC6" ], [ "CLK_BUFG_BOT_R_CK_MUXED7", "CLK_FEED_R_CK_BUFG_CASC7" ], [ "CLK_BUFG_BOT_R_CK_MUXED8", "CLK_FEED_R_CK_BUFG_CASC8" ], [ "CLK_BUFG_BOT_R_CK_MUXED9", "CLK_FEED_R_CK_BUFG_CASC9" ], [ "CLK_BUFG_BOT_R_CK_MUXED10", "CLK_FEED_R_CK_BUFG_CASC10" ], [ "CLK_BUFG_BOT_R_CK_MUXED11", "CLK_FEED_R_CK_BUFG_CASC11" ], [ "CLK_BUFG_BOT_R_CK_MUXED12", "CLK_FEED_R_CK_BUFG_CASC12" ], [ "CLK_BUFG_BOT_R_CK_MUXED13", "CLK_FEED_R_CK_BUFG_CASC13" ], [ "CLK_BUFG_BOT_R_CK_MUXED14", "CLK_FEED_R_CK_BUFG_CASC14" ], [ "CLK_BUFG_BOT_R_CK_MUXED15", "CLK_FEED_R_CK_BUFG_CASC15" ], [ "CLK_BUFG_BOT_R_CK_MUXED16", "CLK_FEED_R_CK_BUFG_CASC16" ], [ "CLK_BUFG_BOT_R_CK_MUXED17", "CLK_FEED_R_CK_BUFG_CASC17" ], [ "CLK_BUFG_BOT_R_CK_MUXED18", "CLK_FEED_R_CK_BUFG_CASC18" ], [ "CLK_BUFG_BOT_R_CK_MUXED19", "CLK_FEED_R_CK_BUFG_CASC19" ], [ "CLK_BUFG_BOT_R_CK_MUXED20", "CLK_FEED_R_CK_BUFG_CASC20" ], [ "CLK_BUFG_BOT_R_CK_MUXED21", "CLK_FEED_R_CK_BUFG_CASC21" ], [ "CLK_BUFG_BOT_R_CK_MUXED22", "CLK_FEED_R_CK_BUFG_CASC22" ], [ "CLK_BUFG_BOT_R_CK_MUXED23", "CLK_FEED_R_CK_BUFG_CASC23" ], [ "CLK_BUFG_BOT_R_CK_MUXED24", "CLK_FEED_R_CK_BUFG_CASC24" ], [ "CLK_BUFG_BOT_R_CK_MUXED25", "CLK_FEED_R_CK_BUFG_CASC25" ], [ "CLK_BUFG_BOT_R_CK_MUXED26", "CLK_FEED_R_CK_BUFG_CASC26" ], [ "CLK_BUFG_BOT_R_CK_MUXED27", "CLK_FEED_R_CK_BUFG_CASC27" ], [ "CLK_BUFG_BOT_R_CK_MUXED28", "CLK_FEED_R_CK_BUFG_CASC28" ], [ "CLK_BUFG_BOT_R_CK_MUXED29", "CLK_FEED_R_CK_BUFG_CASC29" ], [ "CLK_BUFG_BOT_R_CK_MUXED30", "CLK_FEED_R_CK_BUFG_CASC30" ], [ "CLK_BUFG_BOT_R_CK_MUXED31", "CLK_FEED_R_CK_BUFG_CASC31" ], [ "CLK_BUFG_CK_GCLK0", "CLK_FEED_R_CK_GCLK0" ], [ "CLK_BUFG_CK_GCLK1", "CLK_FEED_R_CK_GCLK1" ], [ "CLK_BUFG_CK_GCLK2", "CLK_FEED_R_CK_GCLK2" ], [ "CLK_BUFG_CK_GCLK3", "CLK_FEED_R_CK_GCLK3" ], [ "CLK_BUFG_CK_GCLK4", "CLK_FEED_R_CK_GCLK4" ], [ "CLK_BUFG_CK_GCLK5", "CLK_FEED_R_CK_GCLK5" ], [ "CLK_BUFG_CK_GCLK6", "CLK_FEED_R_CK_GCLK6" ], [ "CLK_BUFG_CK_GCLK7", "CLK_FEED_R_CK_GCLK7" ], [ "CLK_BUFG_CK_GCLK8", "CLK_FEED_R_CK_GCLK8" ], [ "CLK_BUFG_CK_GCLK9", "CLK_FEED_R_CK_GCLK9" ], [ "CLK_BUFG_CK_GCLK10", "CLK_FEED_R_CK_GCLK10" ], [ "CLK_BUFG_CK_GCLK11", "CLK_FEED_R_CK_GCLK11" ], [ "CLK_BUFG_CK_GCLK12", "CLK_FEED_R_CK_GCLK12" ], [ "CLK_BUFG_CK_GCLK13", "CLK_FEED_R_CK_GCLK13" ], [ "CLK_BUFG_CK_GCLK14", "CLK_FEED_R_CK_GCLK14" ], [ "CLK_BUFG_CK_GCLK15", "CLK_FEED_R_CK_GCLK15" ], [ "CLK_BUFG_CK_GCLK16", "CLK_FEED_R_CK_GCLK16" ], [ "CLK_BUFG_CK_GCLK17", "CLK_FEED_R_CK_GCLK17" ], [ "CLK_BUFG_CK_GCLK18", "CLK_FEED_R_CK_GCLK18" ], [ "CLK_BUFG_CK_GCLK19", "CLK_FEED_R_CK_GCLK19" ], [ "CLK_BUFG_CK_GCLK20", "CLK_FEED_R_CK_GCLK20" ], [ "CLK_BUFG_CK_GCLK21", "CLK_FEED_R_CK_GCLK21" ], [ "CLK_BUFG_CK_GCLK22", "CLK_FEED_R_CK_GCLK22" ], [ "CLK_BUFG_CK_GCLK23", "CLK_FEED_R_CK_GCLK23" ], [ "CLK_BUFG_CK_GCLK24", "CLK_FEED_R_CK_GCLK24" ], [ "CLK_BUFG_CK_GCLK25", "CLK_FEED_R_CK_GCLK25" ], [ "CLK_BUFG_CK_GCLK26", "CLK_FEED_R_CK_GCLK26" ], [ "CLK_BUFG_CK_GCLK27", "CLK_FEED_R_CK_GCLK27" ], [ "CLK_BUFG_CK_GCLK28", "CLK_FEED_R_CK_GCLK28" ], [ "CLK_BUFG_CK_GCLK29", "CLK_FEED_R_CK_GCLK29" ], [ "CLK_BUFG_CK_GCLK30", "CLK_FEED_R_CK_GCLK30" ], [ "CLK_BUFG_CK_GCLK31", "CLK_FEED_R_CK_GCLK31" ] ] }, { "grid_deltas": [ -1, -3 ], "tile_types": [ "CLK_BUFG_BOT_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_BUFG_IMUX0_3", "INT_INTERFACE_IMUX0" ], [ "CLK_BUFG_IMUX1_3", "INT_INTERFACE_IMUX1" ], [ "CLK_BUFG_IMUX2_3", "INT_INTERFACE_IMUX2" ], [ "CLK_BUFG_IMUX3_3", "INT_INTERFACE_IMUX3" ], [ "CLK_BUFG_IMUX4_3", "INT_INTERFACE_IMUX4" ], [ "CLK_BUFG_IMUX5_3", "INT_INTERFACE_IMUX5" ], [ "CLK_BUFG_IMUX6_3", "INT_INTERFACE_IMUX6" ], [ "CLK_BUFG_IMUX7_3", "INT_INTERFACE_IMUX7" ], [ "CLK_BUFG_IMUX8_3", "INT_INTERFACE_IMUX8" ], [ "CLK_BUFG_IMUX9_3", "INT_INTERFACE_IMUX9" ], [ "CLK_BUFG_IMUX10_3", "INT_INTERFACE_IMUX10" ], [ "CLK_BUFG_IMUX11_3", "INT_INTERFACE_IMUX11" ], [ "CLK_BUFG_IMUX12_3", "INT_INTERFACE_IMUX12" ], [ "CLK_BUFG_IMUX13_3", "INT_INTERFACE_IMUX13" ], [ "CLK_BUFG_IMUX14_3", "INT_INTERFACE_IMUX14" ], [ "CLK_BUFG_IMUX15_3", "INT_INTERFACE_IMUX15" ], [ "CLK_BUFG_IMUX16_3", "INT_INTERFACE_IMUX16" ], [ "CLK_BUFG_IMUX17_3", "INT_INTERFACE_IMUX17" ], [ "CLK_BUFG_IMUX18_3", "INT_INTERFACE_IMUX18" ], [ "CLK_BUFG_IMUX19_3", "INT_INTERFACE_IMUX19" ], [ "CLK_BUFG_IMUX20_3", "INT_INTERFACE_IMUX20" ], [ "CLK_BUFG_IMUX21_3", "INT_INTERFACE_IMUX21" ], [ "CLK_BUFG_IMUX22_3", "INT_INTERFACE_IMUX22" ], [ "CLK_BUFG_IMUX23_3", "INT_INTERFACE_IMUX23" ], [ "CLK_BUFG_IMUX24_3", "INT_INTERFACE_IMUX24" ], [ "CLK_BUFG_IMUX25_3", "INT_INTERFACE_IMUX25" ], [ "CLK_BUFG_IMUX26_3", "INT_INTERFACE_IMUX26" ], [ "CLK_BUFG_IMUX27_3", "INT_INTERFACE_IMUX27" ], [ "CLK_BUFG_IMUX28_3", "INT_INTERFACE_IMUX28" ], [ "CLK_BUFG_IMUX29_3", "INT_INTERFACE_IMUX29" ], [ "CLK_BUFG_IMUX30_3", "INT_INTERFACE_IMUX30" ], [ "CLK_BUFG_IMUX31_3", "INT_INTERFACE_IMUX31" ], [ "CLK_BUFG_IMUX32_3", "INT_INTERFACE_IMUX32" ], [ "CLK_BUFG_IMUX33_3", "INT_INTERFACE_IMUX33" ], [ "CLK_BUFG_IMUX34_3", "INT_INTERFACE_IMUX34" ], [ "CLK_BUFG_IMUX35_3", "INT_INTERFACE_IMUX35" ], [ "CLK_BUFG_IMUX36_3", "INT_INTERFACE_IMUX36" ], [ "CLK_BUFG_IMUX37_3", "INT_INTERFACE_IMUX37" ], [ "CLK_BUFG_IMUX38_3", "INT_INTERFACE_IMUX38" ], [ "CLK_BUFG_IMUX39_3", "INT_INTERFACE_IMUX39" ], [ "CLK_BUFG_IMUX40_3", "INT_INTERFACE_IMUX40" ], [ "CLK_BUFG_IMUX41_3", "INT_INTERFACE_IMUX41" ], [ "CLK_BUFG_IMUX42_3", "INT_INTERFACE_IMUX42" ], [ "CLK_BUFG_IMUX43_3", "INT_INTERFACE_IMUX43" ], [ "CLK_BUFG_IMUX44_3", "INT_INTERFACE_IMUX44" ], [ "CLK_BUFG_IMUX45_3", "INT_INTERFACE_IMUX45" ], [ "CLK_BUFG_IMUX46_3", "INT_INTERFACE_IMUX46" ], [ "CLK_BUFG_IMUX47_3", "INT_INTERFACE_IMUX47" ], [ "CLK_BUFG_LOGIC_OUTS_B0_3", "INT_INTERFACE_LOGIC_OUTS_B0" ], [ "CLK_BUFG_LOGIC_OUTS_B1_3", "INT_INTERFACE_LOGIC_OUTS_B1" ], [ "CLK_BUFG_LOGIC_OUTS_B2_3", "INT_INTERFACE_LOGIC_OUTS_B2" ], [ "CLK_BUFG_LOGIC_OUTS_B3_3", "INT_INTERFACE_LOGIC_OUTS_B3" ], [ "CLK_BUFG_LOGIC_OUTS_B4_3", "INT_INTERFACE_LOGIC_OUTS_B4" ], [ "CLK_BUFG_LOGIC_OUTS_B5_3", "INT_INTERFACE_LOGIC_OUTS_B5" ], [ "CLK_BUFG_LOGIC_OUTS_B6_3", "INT_INTERFACE_LOGIC_OUTS_B6" ], [ "CLK_BUFG_LOGIC_OUTS_B7_3", "INT_INTERFACE_LOGIC_OUTS_B7" ], [ "CLK_HROW_BYP0_3", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_3", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_3", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_3", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_3", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_3", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_3", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_3", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_3", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_3", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_3", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_3", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_3", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_3", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_3", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_3", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_3", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_3", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_3", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_3", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_3", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_3", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_3", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_3", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_3", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_3", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_3", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_3", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_3", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_3", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_3", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_3", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_3", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_3", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_3", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_3", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_3", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_3", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_3", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_3", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_3", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_3", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_3", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_3", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_3", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_3", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_3", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_3", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_3", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_3", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_3", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_3", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_LH1_3", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_3", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_3", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_3", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_3", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_3", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_3", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_3", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_3", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_3", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_3", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_3", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_3", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_3", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_3", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_3", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_3", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_3", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_3", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_3", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_3", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_3", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_3", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_3", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_3", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_3", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_3", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_3", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_3", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_3", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_3", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_3", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_3", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_3", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_3", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_3", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_3", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_3", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_3", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_3", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_3", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_3", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_3", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_3", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_3", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_3", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_3", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_3", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_3", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_3", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_3", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_3", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_3", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_3", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_3", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_3", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_3", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_3", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_3", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_3", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_3", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_3", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_3", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_3", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_3", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_3", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_3", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_3", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_3", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_3", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_3", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_3", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_3", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_3", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_3", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_3", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_3", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_3", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_3", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_3", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_3", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_3", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_3", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_3", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_3", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_3", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_3", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_3", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_3", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_3", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_3", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_3", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -2 ], "tile_types": [ "CLK_BUFG_BOT_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_BUFG_IMUX0_2", "INT_INTERFACE_IMUX0" ], [ "CLK_BUFG_IMUX1_2", "INT_INTERFACE_IMUX1" ], [ "CLK_BUFG_IMUX2_2", "INT_INTERFACE_IMUX2" ], [ "CLK_BUFG_IMUX3_2", "INT_INTERFACE_IMUX3" ], [ "CLK_BUFG_IMUX4_2", "INT_INTERFACE_IMUX4" ], [ "CLK_BUFG_IMUX5_2", "INT_INTERFACE_IMUX5" ], [ "CLK_BUFG_IMUX6_2", "INT_INTERFACE_IMUX6" ], [ "CLK_BUFG_IMUX7_2", "INT_INTERFACE_IMUX7" ], [ "CLK_BUFG_IMUX8_2", "INT_INTERFACE_IMUX8" ], [ "CLK_BUFG_IMUX9_2", "INT_INTERFACE_IMUX9" ], [ "CLK_BUFG_IMUX10_2", "INT_INTERFACE_IMUX10" ], [ "CLK_BUFG_IMUX11_2", "INT_INTERFACE_IMUX11" ], [ "CLK_BUFG_IMUX12_2", "INT_INTERFACE_IMUX12" ], [ "CLK_BUFG_IMUX13_2", "INT_INTERFACE_IMUX13" ], [ "CLK_BUFG_IMUX14_2", "INT_INTERFACE_IMUX14" ], [ "CLK_BUFG_IMUX15_2", "INT_INTERFACE_IMUX15" ], [ "CLK_BUFG_IMUX16_2", "INT_INTERFACE_IMUX16" ], [ "CLK_BUFG_IMUX17_2", "INT_INTERFACE_IMUX17" ], [ "CLK_BUFG_IMUX18_2", "INT_INTERFACE_IMUX18" ], [ "CLK_BUFG_IMUX19_2", "INT_INTERFACE_IMUX19" ], [ "CLK_BUFG_IMUX20_2", "INT_INTERFACE_IMUX20" ], [ "CLK_BUFG_IMUX21_2", "INT_INTERFACE_IMUX21" ], [ "CLK_BUFG_IMUX22_2", "INT_INTERFACE_IMUX22" ], [ "CLK_BUFG_IMUX23_2", "INT_INTERFACE_IMUX23" ], [ "CLK_BUFG_IMUX24_2", "INT_INTERFACE_IMUX24" ], [ "CLK_BUFG_IMUX25_2", "INT_INTERFACE_IMUX25" ], [ "CLK_BUFG_IMUX26_2", "INT_INTERFACE_IMUX26" ], [ "CLK_BUFG_IMUX27_2", "INT_INTERFACE_IMUX27" ], [ "CLK_BUFG_IMUX28_2", "INT_INTERFACE_IMUX28" ], [ "CLK_BUFG_IMUX29_2", "INT_INTERFACE_IMUX29" ], [ "CLK_BUFG_IMUX30_2", "INT_INTERFACE_IMUX30" ], [ "CLK_BUFG_IMUX31_2", "INT_INTERFACE_IMUX31" ], [ "CLK_BUFG_IMUX32_2", "INT_INTERFACE_IMUX32" ], [ "CLK_BUFG_IMUX33_2", "INT_INTERFACE_IMUX33" ], [ "CLK_BUFG_IMUX34_2", "INT_INTERFACE_IMUX34" ], [ "CLK_BUFG_IMUX35_2", "INT_INTERFACE_IMUX35" ], [ "CLK_BUFG_IMUX36_2", "INT_INTERFACE_IMUX36" ], [ "CLK_BUFG_IMUX37_2", "INT_INTERFACE_IMUX37" ], [ "CLK_BUFG_IMUX38_2", "INT_INTERFACE_IMUX38" ], [ "CLK_BUFG_IMUX39_2", "INT_INTERFACE_IMUX39" ], [ "CLK_BUFG_IMUX40_2", "INT_INTERFACE_IMUX40" ], [ "CLK_BUFG_IMUX41_2", "INT_INTERFACE_IMUX41" ], [ "CLK_BUFG_IMUX42_2", "INT_INTERFACE_IMUX42" ], [ "CLK_BUFG_IMUX43_2", "INT_INTERFACE_IMUX43" ], [ "CLK_BUFG_IMUX44_2", "INT_INTERFACE_IMUX44" ], [ "CLK_BUFG_IMUX45_2", "INT_INTERFACE_IMUX45" ], [ "CLK_BUFG_IMUX46_2", "INT_INTERFACE_IMUX46" ], [ "CLK_BUFG_IMUX47_2", "INT_INTERFACE_IMUX47" ], [ "CLK_BUFG_LOGIC_OUTS_B0_2", "INT_INTERFACE_LOGIC_OUTS_B0" ], [ "CLK_BUFG_LOGIC_OUTS_B1_2", "INT_INTERFACE_LOGIC_OUTS_B1" ], [ "CLK_BUFG_LOGIC_OUTS_B2_2", "INT_INTERFACE_LOGIC_OUTS_B2" ], [ "CLK_BUFG_LOGIC_OUTS_B3_2", "INT_INTERFACE_LOGIC_OUTS_B3" ], [ "CLK_BUFG_LOGIC_OUTS_B4_2", "INT_INTERFACE_LOGIC_OUTS_B4" ], [ "CLK_BUFG_LOGIC_OUTS_B5_2", "INT_INTERFACE_LOGIC_OUTS_B5" ], [ "CLK_BUFG_LOGIC_OUTS_B6_2", "INT_INTERFACE_LOGIC_OUTS_B6" ], [ "CLK_BUFG_LOGIC_OUTS_B7_2", "INT_INTERFACE_LOGIC_OUTS_B7" ], [ "CLK_HROW_BYP0_2", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_2", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_2", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_2", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_2", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_2", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_2", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_2", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_2", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_2", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_2", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_2", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_2", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_2", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_2", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_2", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_2", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_2", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_2", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_2", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_2", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_2", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_2", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_2", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_2", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_2", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_2", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_2", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_2", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_2", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_2", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_2", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_2", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_2", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_2", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_2", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_2", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_2", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_2", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_2", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_2", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_2", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_2", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_2", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_2", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_2", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_2", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_2", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_2", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_2", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_2", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_2", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_LH1_2", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_2", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_2", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_2", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_2", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_2", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_2", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_2", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_2", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_2", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_2", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_2", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_2", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_2", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_2", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_2", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_2", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_2", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_2", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_2", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_2", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_2", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_2", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_2", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_2", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_2", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_2", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_2", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_2", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_2", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_2", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_2", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_2", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_2", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_2", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_2", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_2", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_2", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_2", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_2", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_2", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_2", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_2", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_2", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_2", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_2", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_2", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_2", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_2", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_2", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_2", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_2", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_2", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_2", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_2", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_2", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_2", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_2", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_2", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_2", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_2", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_2", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_2", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_2", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_2", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_2", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_2", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_2", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_2", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_2", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_2", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_2", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_2", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_2", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_2", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_2", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_2", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_2", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_2", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_2", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_2", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_2", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_2", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_2", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_2", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_2", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_2", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_2", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_2", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_2", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_2", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_2", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -1 ], "tile_types": [ "CLK_BUFG_BOT_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_BUFG_IMUX0_1", "INT_INTERFACE_IMUX0" ], [ "CLK_BUFG_IMUX1_1", "INT_INTERFACE_IMUX1" ], [ "CLK_BUFG_IMUX2_1", "INT_INTERFACE_IMUX2" ], [ "CLK_BUFG_IMUX3_1", "INT_INTERFACE_IMUX3" ], [ "CLK_BUFG_IMUX4_1", "INT_INTERFACE_IMUX4" ], [ "CLK_BUFG_IMUX5_1", "INT_INTERFACE_IMUX5" ], [ "CLK_BUFG_IMUX6_1", "INT_INTERFACE_IMUX6" ], [ "CLK_BUFG_IMUX7_1", "INT_INTERFACE_IMUX7" ], [ "CLK_BUFG_IMUX8_1", "INT_INTERFACE_IMUX8" ], [ "CLK_BUFG_IMUX9_1", "INT_INTERFACE_IMUX9" ], [ "CLK_BUFG_IMUX10_1", "INT_INTERFACE_IMUX10" ], [ "CLK_BUFG_IMUX11_1", "INT_INTERFACE_IMUX11" ], [ "CLK_BUFG_IMUX12_1", "INT_INTERFACE_IMUX12" ], [ "CLK_BUFG_IMUX13_1", "INT_INTERFACE_IMUX13" ], [ "CLK_BUFG_IMUX14_1", "INT_INTERFACE_IMUX14" ], [ "CLK_BUFG_IMUX15_1", "INT_INTERFACE_IMUX15" ], [ "CLK_BUFG_IMUX16_1", "INT_INTERFACE_IMUX16" ], [ "CLK_BUFG_IMUX17_1", "INT_INTERFACE_IMUX17" ], [ "CLK_BUFG_IMUX18_1", "INT_INTERFACE_IMUX18" ], [ "CLK_BUFG_IMUX19_1", "INT_INTERFACE_IMUX19" ], [ "CLK_BUFG_IMUX20_1", "INT_INTERFACE_IMUX20" ], [ "CLK_BUFG_IMUX21_1", "INT_INTERFACE_IMUX21" ], [ "CLK_BUFG_IMUX22_1", "INT_INTERFACE_IMUX22" ], [ "CLK_BUFG_IMUX23_1", "INT_INTERFACE_IMUX23" ], [ "CLK_BUFG_IMUX24_1", "INT_INTERFACE_IMUX24" ], [ "CLK_BUFG_IMUX25_1", "INT_INTERFACE_IMUX25" ], [ "CLK_BUFG_IMUX26_1", "INT_INTERFACE_IMUX26" ], [ "CLK_BUFG_IMUX27_1", "INT_INTERFACE_IMUX27" ], [ "CLK_BUFG_IMUX28_1", "INT_INTERFACE_IMUX28" ], [ "CLK_BUFG_IMUX29_1", "INT_INTERFACE_IMUX29" ], [ "CLK_BUFG_IMUX30_1", "INT_INTERFACE_IMUX30" ], [ "CLK_BUFG_IMUX31_1", "INT_INTERFACE_IMUX31" ], [ "CLK_BUFG_IMUX32_1", "INT_INTERFACE_IMUX32" ], [ "CLK_BUFG_IMUX33_1", "INT_INTERFACE_IMUX33" ], [ "CLK_BUFG_IMUX34_1", "INT_INTERFACE_IMUX34" ], [ "CLK_BUFG_IMUX35_1", "INT_INTERFACE_IMUX35" ], [ "CLK_BUFG_IMUX36_1", "INT_INTERFACE_IMUX36" ], [ "CLK_BUFG_IMUX37_1", "INT_INTERFACE_IMUX37" ], [ "CLK_BUFG_IMUX38_1", "INT_INTERFACE_IMUX38" ], [ "CLK_BUFG_IMUX39_1", "INT_INTERFACE_IMUX39" ], [ "CLK_BUFG_IMUX40_1", "INT_INTERFACE_IMUX40" ], [ "CLK_BUFG_IMUX41_1", "INT_INTERFACE_IMUX41" ], [ "CLK_BUFG_IMUX42_1", "INT_INTERFACE_IMUX42" ], [ "CLK_BUFG_IMUX43_1", "INT_INTERFACE_IMUX43" ], [ "CLK_BUFG_IMUX44_1", "INT_INTERFACE_IMUX44" ], [ "CLK_BUFG_IMUX45_1", "INT_INTERFACE_IMUX45" ], [ "CLK_BUFG_IMUX46_1", "INT_INTERFACE_IMUX46" ], [ "CLK_BUFG_IMUX47_1", "INT_INTERFACE_IMUX47" ], [ "CLK_BUFG_LOGIC_OUTS_B0_1", "INT_INTERFACE_LOGIC_OUTS_B0" ], [ "CLK_BUFG_LOGIC_OUTS_B1_1", "INT_INTERFACE_LOGIC_OUTS_B1" ], [ "CLK_BUFG_LOGIC_OUTS_B2_1", "INT_INTERFACE_LOGIC_OUTS_B2" ], [ "CLK_BUFG_LOGIC_OUTS_B3_1", "INT_INTERFACE_LOGIC_OUTS_B3" ], [ "CLK_BUFG_LOGIC_OUTS_B4_1", "INT_INTERFACE_LOGIC_OUTS_B4" ], [ "CLK_BUFG_LOGIC_OUTS_B5_1", "INT_INTERFACE_LOGIC_OUTS_B5" ], [ "CLK_BUFG_LOGIC_OUTS_B6_1", "INT_INTERFACE_LOGIC_OUTS_B6" ], [ "CLK_BUFG_LOGIC_OUTS_B7_1", "INT_INTERFACE_LOGIC_OUTS_B7" ], [ "CLK_HROW_BYP0_1", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_1", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_1", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_1", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_1", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_1", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_1", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_1", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_1", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_1", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_1", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_1", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_1", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_1", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_1", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_1", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_1", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_1", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_1", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_1", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_1", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_1", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_1", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_1", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_1", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_1", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_1", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_1", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_1", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_1", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_1", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_1", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_1", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_1", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_1", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_1", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_1", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_1", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_1", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_1", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_1", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_1", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_1", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_1", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_1", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_1", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_1", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_1", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_1", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_1", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_1", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_1", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_LH1_1", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_1", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_1", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_1", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_1", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_1", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_1", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_1", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_1", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_1", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_1", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_1", "INT_INTERFACE_LH12" ], [ "CLK_HROW_MONITOR_N_1", "INT_INTERFACE_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_1", "INT_INTERFACE_MONITOR_P" ], [ "CLK_HROW_NE2A0_1", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_1", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_1", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_1", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_1", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_1", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_1", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_1", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_1", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_1", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_1", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_1", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_1", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_1", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_1", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_1", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_1", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_1", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_1", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_1", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_1", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_1", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_1", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_1", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_1", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_1", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_1", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_1", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_1", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_1", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_1", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_1", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_1", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_1", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_1", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_1", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_1", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_1", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_1", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_1", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_1", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_1", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_1", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_1", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_1", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_1", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_1", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_1", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_1", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_1", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_1", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_1", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_1", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_1", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_1", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_1", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_1", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_1", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_1", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_1", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_1", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_1", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_1", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_1", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_1", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_1", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_1", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_1", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_1", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_1", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_1", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_1", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_1", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_1", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_1", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_1", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_1", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_1", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_1", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_1", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "CLK_BUFG_BOT_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_BUFG_IMUX0_0", "INT_INTERFACE_IMUX0" ], [ "CLK_BUFG_IMUX1_0", "INT_INTERFACE_IMUX1" ], [ "CLK_BUFG_IMUX2_0", "INT_INTERFACE_IMUX2" ], [ "CLK_BUFG_IMUX3_0", "INT_INTERFACE_IMUX3" ], [ "CLK_BUFG_IMUX4_0", "INT_INTERFACE_IMUX4" ], [ "CLK_BUFG_IMUX5_0", "INT_INTERFACE_IMUX5" ], [ "CLK_BUFG_IMUX6_0", "INT_INTERFACE_IMUX6" ], [ "CLK_BUFG_IMUX7_0", "INT_INTERFACE_IMUX7" ], [ "CLK_BUFG_IMUX8_0", "INT_INTERFACE_IMUX8" ], [ "CLK_BUFG_IMUX9_0", "INT_INTERFACE_IMUX9" ], [ "CLK_BUFG_IMUX10_0", "INT_INTERFACE_IMUX10" ], [ "CLK_BUFG_IMUX11_0", "INT_INTERFACE_IMUX11" ], [ "CLK_BUFG_IMUX12_0", "INT_INTERFACE_IMUX12" ], [ "CLK_BUFG_IMUX13_0", "INT_INTERFACE_IMUX13" ], [ "CLK_BUFG_IMUX14_0", "INT_INTERFACE_IMUX14" ], [ "CLK_BUFG_IMUX15_0", "INT_INTERFACE_IMUX15" ], [ "CLK_BUFG_IMUX16_0", "INT_INTERFACE_IMUX16" ], [ "CLK_BUFG_IMUX17_0", "INT_INTERFACE_IMUX17" ], [ "CLK_BUFG_IMUX18_0", "INT_INTERFACE_IMUX18" ], [ "CLK_BUFG_IMUX19_0", "INT_INTERFACE_IMUX19" ], [ "CLK_BUFG_IMUX20_0", "INT_INTERFACE_IMUX20" ], [ "CLK_BUFG_IMUX21_0", "INT_INTERFACE_IMUX21" ], [ "CLK_BUFG_IMUX22_0", "INT_INTERFACE_IMUX22" ], [ "CLK_BUFG_IMUX23_0", "INT_INTERFACE_IMUX23" ], [ "CLK_BUFG_IMUX24_0", "INT_INTERFACE_IMUX24" ], [ "CLK_BUFG_IMUX25_0", "INT_INTERFACE_IMUX25" ], [ "CLK_BUFG_IMUX26_0", "INT_INTERFACE_IMUX26" ], [ "CLK_BUFG_IMUX27_0", "INT_INTERFACE_IMUX27" ], [ "CLK_BUFG_IMUX28_0", "INT_INTERFACE_IMUX28" ], [ "CLK_BUFG_IMUX29_0", "INT_INTERFACE_IMUX29" ], [ "CLK_BUFG_IMUX30_0", "INT_INTERFACE_IMUX30" ], [ "CLK_BUFG_IMUX31_0", "INT_INTERFACE_IMUX31" ], [ "CLK_BUFG_IMUX32_0", "INT_INTERFACE_IMUX32" ], [ "CLK_BUFG_IMUX33_0", "INT_INTERFACE_IMUX33" ], [ "CLK_BUFG_IMUX34_0", "INT_INTERFACE_IMUX34" ], [ "CLK_BUFG_IMUX35_0", "INT_INTERFACE_IMUX35" ], [ "CLK_BUFG_IMUX36_0", "INT_INTERFACE_IMUX36" ], [ "CLK_BUFG_IMUX37_0", "INT_INTERFACE_IMUX37" ], [ "CLK_BUFG_IMUX38_0", "INT_INTERFACE_IMUX38" ], [ "CLK_BUFG_IMUX39_0", "INT_INTERFACE_IMUX39" ], [ "CLK_BUFG_IMUX40_0", "INT_INTERFACE_IMUX40" ], [ "CLK_BUFG_IMUX41_0", "INT_INTERFACE_IMUX41" ], [ "CLK_BUFG_IMUX42_0", "INT_INTERFACE_IMUX42" ], [ "CLK_BUFG_IMUX43_0", "INT_INTERFACE_IMUX43" ], [ "CLK_BUFG_IMUX44_0", "INT_INTERFACE_IMUX44" ], [ "CLK_BUFG_IMUX45_0", "INT_INTERFACE_IMUX45" ], [ "CLK_BUFG_IMUX46_0", "INT_INTERFACE_IMUX46" ], [ "CLK_BUFG_IMUX47_0", "INT_INTERFACE_IMUX47" ], [ "CLK_BUFG_LOGIC_OUTS_B0_0", "INT_INTERFACE_LOGIC_OUTS_B0" ], [ "CLK_BUFG_LOGIC_OUTS_B1_0", "INT_INTERFACE_LOGIC_OUTS_B1" ], [ "CLK_BUFG_LOGIC_OUTS_B2_0", "INT_INTERFACE_LOGIC_OUTS_B2" ], [ "CLK_BUFG_LOGIC_OUTS_B3_0", "INT_INTERFACE_LOGIC_OUTS_B3" ], [ "CLK_BUFG_LOGIC_OUTS_B4_0", "INT_INTERFACE_LOGIC_OUTS_B4" ], [ "CLK_BUFG_LOGIC_OUTS_B5_0", "INT_INTERFACE_LOGIC_OUTS_B5" ], [ "CLK_BUFG_LOGIC_OUTS_B6_0", "INT_INTERFACE_LOGIC_OUTS_B6" ], [ "CLK_BUFG_LOGIC_OUTS_B7_0", "INT_INTERFACE_LOGIC_OUTS_B7" ], [ "CLK_HROW_BYP0_0", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_0", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_0", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_0", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_0", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_0", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_0", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_0", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_0", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_0", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_0", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_0", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_0", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_0", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_0", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_0", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_0", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_0", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_0", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_0", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_0", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_0", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_0", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_0", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_0", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_0", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_0", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_0", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_0", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_0", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_0", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_0", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_0", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_0", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_0", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_0", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_0", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_0", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_0", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_0", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_0", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_0", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_0", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_0", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_0", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_0", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_0", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_0", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_0", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_0", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_0", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_0", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_LH1_0", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_0", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_0", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_0", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_0", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_0", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_0", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_0", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_0", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_0", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_0", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_0", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_0", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_0", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_0", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_0", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_0", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_0", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_0", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_0", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_0", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_0", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_0", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_0", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_0", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_0", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_0", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_0", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_0", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_0", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_0", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_0", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_0", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_0", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_0", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_0", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_0", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_0", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_0", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_0", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_0", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_0", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_0", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_0", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_0", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_0", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_0", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_0", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_0", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_0", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_0", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_0", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_0", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_0", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_0", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_0", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_0", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_0", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_0", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_0", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_0", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_0", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_0", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_0", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_0", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_0", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_0", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_0", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_0", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_0", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_0", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_0", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_0", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_0", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_0", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_0", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_0", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_0", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_0", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_0", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_0", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_0", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_0", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_0", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_0", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_0", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_0", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_0", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_0", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_0", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_0", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_0", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ 1, -3 ], "tile_types": [ "CLK_BUFG_BOT_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_3", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_3", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_3", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_3", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_3", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_3", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_3", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_3", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_3", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_3", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_3", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_3", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_3", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_3", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_3", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_3", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_3", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_3", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_3", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_3", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_3", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_3", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_3", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_3", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_3", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_3", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_3", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_3", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_3", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_3", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_3", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_3", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_3", "VBRK_LH1" ], [ "CLK_HROW_LH2_3", "VBRK_LH2" ], [ "CLK_HROW_LH3_3", "VBRK_LH3" ], [ "CLK_HROW_LH4_3", "VBRK_LH4" ], [ "CLK_HROW_LH5_3", "VBRK_LH5" ], [ "CLK_HROW_LH6_3", "VBRK_LH6" ], [ "CLK_HROW_LH7_3", "VBRK_LH7" ], [ "CLK_HROW_LH8_3", "VBRK_LH8" ], [ "CLK_HROW_LH9_3", "VBRK_LH9" ], [ "CLK_HROW_LH10_3", "VBRK_LH10" ], [ "CLK_HROW_LH11_3", "VBRK_LH11" ], [ "CLK_HROW_LH12_3", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_3", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_3", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_3", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_3", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_3", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_3", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_3", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_3", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_3", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_3", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_3", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_3", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_3", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_3", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_3", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_3", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_3", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_3", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_3", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_3", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_3", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_3", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_3", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_3", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_3", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_3", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_3", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_3", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_3", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_3", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_3", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_3", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_3", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_3", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_3", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_3", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_3", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_3", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_3", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_3", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_3", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_3", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_3", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_3", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_3", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_3", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_3", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_3", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_3", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_3", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_3", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_3", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_3", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_3", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_3", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_3", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_3", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_3", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_3", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_3", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_3", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_3", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_3", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_3", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_3", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_3", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_3", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_3", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_3", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_3", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_3", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_3", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_3", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_3", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_3", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_3", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_3", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_3", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_3", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -2 ], "tile_types": [ "CLK_BUFG_BOT_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_2", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_2", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_2", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_2", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_2", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_2", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_2", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_2", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_2", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_2", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_2", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_2", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_2", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_2", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_2", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_2", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_2", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_2", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_2", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_2", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_2", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_2", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_2", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_2", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_2", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_2", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_2", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_2", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_2", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_2", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_2", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_2", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_2", "VBRK_LH1" ], [ "CLK_HROW_LH2_2", "VBRK_LH2" ], [ "CLK_HROW_LH3_2", "VBRK_LH3" ], [ "CLK_HROW_LH4_2", "VBRK_LH4" ], [ "CLK_HROW_LH5_2", "VBRK_LH5" ], [ "CLK_HROW_LH6_2", "VBRK_LH6" ], [ "CLK_HROW_LH7_2", "VBRK_LH7" ], [ "CLK_HROW_LH8_2", "VBRK_LH8" ], [ "CLK_HROW_LH9_2", "VBRK_LH9" ], [ "CLK_HROW_LH10_2", "VBRK_LH10" ], [ "CLK_HROW_LH11_2", "VBRK_LH11" ], [ "CLK_HROW_LH12_2", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_2", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_2", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_2", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_2", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_2", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_2", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_2", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_2", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_2", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_2", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_2", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_2", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_2", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_2", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_2", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_2", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_2", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_2", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_2", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_2", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_2", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_2", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_2", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_2", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_2", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_2", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_2", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_2", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_2", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_2", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_2", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_2", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_2", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_2", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_2", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_2", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_2", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_2", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_2", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_2", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_2", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_2", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_2", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_2", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_2", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_2", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_2", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_2", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_2", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_2", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_2", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_2", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_2", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_2", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_2", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_2", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_2", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_2", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_2", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_2", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_2", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_2", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_2", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_2", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_2", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_2", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_2", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_2", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_2", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_2", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_2", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_2", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_2", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_2", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_2", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_2", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_2", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_2", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_2", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_2", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -1 ], "tile_types": [ "CLK_BUFG_BOT_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_1", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_1", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_1", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_1", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_1", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_1", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_1", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_1", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_1", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_1", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_1", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_1", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_1", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_1", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_1", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_1", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_1", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_1", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_1", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_1", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_1", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_1", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_1", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_1", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_1", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_1", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_1", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_1", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_1", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_1", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_1", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_1", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_1", "VBRK_LH1" ], [ "CLK_HROW_LH2_1", "VBRK_LH2" ], [ "CLK_HROW_LH3_1", "VBRK_LH3" ], [ "CLK_HROW_LH4_1", "VBRK_LH4" ], [ "CLK_HROW_LH5_1", "VBRK_LH5" ], [ "CLK_HROW_LH6_1", "VBRK_LH6" ], [ "CLK_HROW_LH7_1", "VBRK_LH7" ], [ "CLK_HROW_LH8_1", "VBRK_LH8" ], [ "CLK_HROW_LH9_1", "VBRK_LH9" ], [ "CLK_HROW_LH10_1", "VBRK_LH10" ], [ "CLK_HROW_LH11_1", "VBRK_LH11" ], [ "CLK_HROW_LH12_1", "VBRK_LH12" ], [ "CLK_HROW_MONITOR_N_1", "VBRK_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_1", "VBRK_MONITOR_P" ], [ "CLK_HROW_NE2A0_1", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_1", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_1", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_1", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_1", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_1", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_1", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_1", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_1", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_1", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_1", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_1", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_1", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_1", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_1", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_1", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_1", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_1", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_1", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_1", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_1", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_1", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_1", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_1", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_1", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_1", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_1", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_1", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_1", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_1", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_1", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_1", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_1", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_1", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_1", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_1", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_1", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_1", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_1", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_1", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_1", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_1", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_1", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_1", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_1", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_1", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_1", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_1", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_1", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_1", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_1", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_1", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_1", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_1", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_1", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_1", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_1", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_1", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_1", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_1", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_1", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_1", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_1", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_1", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_1", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_1", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_1", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_1", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_1", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_1", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_1", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_1", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_1", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_1", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_1", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_1", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_1", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_1", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_1", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_1", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLK_BUFG_BOT_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_0", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_0", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_0", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_0", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_0", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_0", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_0", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_0", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_0", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_0", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_0", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_0", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_0", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_0", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_0", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_0", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_0", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_0", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_0", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_0", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_0", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_0", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_0", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_0", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_0", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_0", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_0", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_0", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_0", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_0", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_0", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_0", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_0", "VBRK_LH1" ], [ "CLK_HROW_LH2_0", "VBRK_LH2" ], [ "CLK_HROW_LH3_0", "VBRK_LH3" ], [ "CLK_HROW_LH4_0", "VBRK_LH4" ], [ "CLK_HROW_LH5_0", "VBRK_LH5" ], [ "CLK_HROW_LH6_0", "VBRK_LH6" ], [ "CLK_HROW_LH7_0", "VBRK_LH7" ], [ "CLK_HROW_LH8_0", "VBRK_LH8" ], [ "CLK_HROW_LH9_0", "VBRK_LH9" ], [ "CLK_HROW_LH10_0", "VBRK_LH10" ], [ "CLK_HROW_LH11_0", "VBRK_LH11" ], [ "CLK_HROW_LH12_0", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_0", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_0", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_0", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_0", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_0", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_0", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_0", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_0", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_0", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_0", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_0", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_0", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_0", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_0", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_0", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_0", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_0", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_0", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_0", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_0", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_0", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_0", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_0", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_0", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_0", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_0", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_0", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_0", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_0", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_0", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_0", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_0", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_0", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_0", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_0", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_0", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_0", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_0", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_0", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_0", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_0", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_0", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_0", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_0", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_0", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_0", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_0", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_0", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_0", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_0", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_0", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_0", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_0", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_0", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_0", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_0", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_0", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_0", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_0", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_0", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_0", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_0", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_0", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_0", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_0", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_0", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_0", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_0", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_0", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_0", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_0", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_0", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_0", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_0", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_0", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_0", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_0", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_0", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_0", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_0", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 0, -2 ], "tile_types": [ "CLK_BUFG_REBUF", "CLK_FEED" ], "wire_pairs": [ [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", "CLK_FEED_R_CK_BUFG_CASC1" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", "CLK_FEED_R_CK_BUFG_CASC2" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", "CLK_FEED_R_CK_BUFG_CASC3" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", "CLK_FEED_R_CK_BUFG_CASC4" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", "CLK_FEED_R_CK_BUFG_CASC5" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", "CLK_FEED_R_CK_BUFG_CASC6" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", "CLK_FEED_R_CK_BUFG_CASC7" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", "CLK_FEED_R_CK_BUFG_CASC8" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", "CLK_FEED_R_CK_BUFG_CASC9" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", "CLK_FEED_R_CK_BUFG_CASC10" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", "CLK_FEED_R_CK_BUFG_CASC11" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", "CLK_FEED_R_CK_BUFG_CASC12" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", "CLK_FEED_R_CK_BUFG_CASC13" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", "CLK_FEED_R_CK_BUFG_CASC14" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", "CLK_FEED_R_CK_BUFG_CASC15" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", "CLK_FEED_R_CK_BUFG_CASC16" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", "CLK_FEED_R_CK_BUFG_CASC17" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", "CLK_FEED_R_CK_BUFG_CASC18" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", "CLK_FEED_R_CK_BUFG_CASC19" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", "CLK_FEED_R_CK_BUFG_CASC20" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", "CLK_FEED_R_CK_BUFG_CASC21" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", "CLK_FEED_R_CK_BUFG_CASC22" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", "CLK_FEED_R_CK_BUFG_CASC23" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", "CLK_FEED_R_CK_BUFG_CASC24" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", "CLK_FEED_R_CK_BUFG_CASC25" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", "CLK_FEED_R_CK_BUFG_CASC26" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", "CLK_FEED_R_CK_BUFG_CASC27" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", "CLK_FEED_R_CK_BUFG_CASC28" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", "CLK_FEED_R_CK_BUFG_CASC29" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", "CLK_FEED_R_CK_BUFG_CASC30" ], [ "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", "CLK_FEED_R_CK_BUFG_CASC31" ], [ "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", "CLK_FEED_R_CK_GCLK0" ], [ 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"CLK_BUFG_REBUF_R_CK_GCLK13_BOT", "CLK_FEED_R_CK_GCLK13" ], [ "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", "CLK_FEED_R_CK_GCLK14" ], [ "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", "CLK_FEED_R_CK_GCLK15" ], [ "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", "CLK_FEED_R_CK_GCLK16" ], [ "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", "CLK_FEED_R_CK_GCLK17" ], [ "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", "CLK_FEED_R_CK_GCLK18" ], [ "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", "CLK_FEED_R_CK_GCLK19" ], [ "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", "CLK_FEED_R_CK_GCLK20" ], [ "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", "CLK_FEED_R_CK_GCLK21" ], [ "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", "CLK_FEED_R_CK_GCLK22" ], [ "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", "CLK_FEED_R_CK_GCLK23" ], [ "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", "CLK_FEED_R_CK_GCLK24" ], [ "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", "CLK_FEED_R_CK_GCLK25" ], [ "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", "CLK_FEED_R_CK_GCLK26" ], [ "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", "CLK_FEED_R_CK_GCLK27" ], [ "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", "CLK_FEED_R_CK_GCLK28" ], [ "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", "CLK_FEED_R_CK_GCLK29" ], [ "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", "CLK_FEED_R_CK_GCLK30" ], [ "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", "CLK_FEED_R_CK_GCLK31" ] ] }, { "grid_deltas": [ -1, -1 ], "tile_types": [ "CLK_BUFG_REBUF", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_BUFG_REBUF_EE2A0_1", "INT_INTERFACE_EE2A0" ], [ "CLK_BUFG_REBUF_EE2A1_1", "INT_INTERFACE_EE2A1" ], [ "CLK_BUFG_REBUF_EE2A2_1", "INT_INTERFACE_EE2A2" ], [ "CLK_BUFG_REBUF_EE2A3_1", "INT_INTERFACE_EE2A3" ], [ "CLK_BUFG_REBUF_EE2BEG0_1", "INT_INTERFACE_EE2BEG0" ], [ "CLK_BUFG_REBUF_EE2BEG1_1", "INT_INTERFACE_EE2BEG1" ], [ "CLK_BUFG_REBUF_EE2BEG2_1", "INT_INTERFACE_EE2BEG2" ], [ "CLK_BUFG_REBUF_EE2BEG3_1", "INT_INTERFACE_EE2BEG3" ], [ "CLK_BUFG_REBUF_EE4A0_1", "INT_INTERFACE_EE4A0" ], [ "CLK_BUFG_REBUF_EE4A1_1", "INT_INTERFACE_EE4A1" ], [ "CLK_BUFG_REBUF_EE4A2_1", "INT_INTERFACE_EE4A2" ], [ "CLK_BUFG_REBUF_EE4A3_1", "INT_INTERFACE_EE4A3" ], [ "CLK_BUFG_REBUF_EE4B0_1", "INT_INTERFACE_EE4B0" ], [ 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"CLK_BUFG_REBUF_LH8_1", "VBRK_LH8" ], [ "CLK_BUFG_REBUF_LH9_1", "VBRK_LH9" ], [ "CLK_BUFG_REBUF_LH10_1", "VBRK_LH10" ], [ "CLK_BUFG_REBUF_LH11_1", "VBRK_LH11" ], [ "CLK_BUFG_REBUF_LH12_1", "VBRK_LH12" ], [ "CLK_BUFG_REBUF_MONITOR_N_1", "VBRK_MONITOR_N" ], [ "CLK_BUFG_REBUF_MONITOR_P_1", "VBRK_MONITOR_P" ], [ "CLK_BUFG_REBUF_NE2A0_1", "VBRK_NE2A0" ], [ "CLK_BUFG_REBUF_NE2A1_1", "VBRK_NE2A1" ], [ "CLK_BUFG_REBUF_NE2A2_1", "VBRK_NE2A2" ], [ "CLK_BUFG_REBUF_NE2A3_1", "VBRK_NE2A3" ], [ "CLK_BUFG_REBUF_NE4BEG0_1", "VBRK_NE4BEG0" ], [ "CLK_BUFG_REBUF_NE4BEG1_1", "VBRK_NE4BEG1" ], [ "CLK_BUFG_REBUF_NE4BEG2_1", "VBRK_NE4BEG2" ], [ "CLK_BUFG_REBUF_NE4BEG3_1", "VBRK_NE4BEG3" ], [ "CLK_BUFG_REBUF_NE4C0_1", "VBRK_NE4C0" ], [ "CLK_BUFG_REBUF_NE4C1_1", "VBRK_NE4C1" ], [ "CLK_BUFG_REBUF_NE4C2_1", "VBRK_NE4C2" ], [ "CLK_BUFG_REBUF_NE4C3_1", "VBRK_NE4C3" ], [ "CLK_BUFG_REBUF_NW2A0_1", "VBRK_NW2A0" ], [ "CLK_BUFG_REBUF_NW2A1_1", "VBRK_NW2A1" ], [ "CLK_BUFG_REBUF_NW2A2_1", "VBRK_NW2A2" ], [ "CLK_BUFG_REBUF_NW2A3_1", "VBRK_NW2A3" ], [ "CLK_BUFG_REBUF_NW4A0_1", "VBRK_NW4A0" ], [ "CLK_BUFG_REBUF_NW4A1_1", "VBRK_NW4A1" ], [ "CLK_BUFG_REBUF_NW4A2_1", "VBRK_NW4A2" ], [ "CLK_BUFG_REBUF_NW4A3_1", "VBRK_NW4A3" ], [ "CLK_BUFG_REBUF_NW4END0_1", "VBRK_NW4END0" ], [ "CLK_BUFG_REBUF_NW4END1_1", "VBRK_NW4END1" ], [ "CLK_BUFG_REBUF_NW4END2_1", "VBRK_NW4END2" ], [ "CLK_BUFG_REBUF_NW4END3_1", "VBRK_NW4END3" ], [ "CLK_BUFG_REBUF_SE2A0_1", "VBRK_SE2A0" ], [ "CLK_BUFG_REBUF_SE2A1_1", "VBRK_SE2A1" ], [ "CLK_BUFG_REBUF_SE2A2_1", "VBRK_SE2A2" ], [ "CLK_BUFG_REBUF_SE2A3_1", "VBRK_SE2A3" ], [ "CLK_BUFG_REBUF_SE4BEG0_1", "VBRK_SE4BEG0" ], [ "CLK_BUFG_REBUF_SE4BEG1_1", "VBRK_SE4BEG1" ], [ "CLK_BUFG_REBUF_SE4BEG2_1", "VBRK_SE4BEG2" ], [ "CLK_BUFG_REBUF_SE4BEG3_1", "VBRK_SE4BEG3" ], [ "CLK_BUFG_REBUF_SE4C0_1", "VBRK_SE4C0" ], [ "CLK_BUFG_REBUF_SE4C1_1", "VBRK_SE4C1" ], [ "CLK_BUFG_REBUF_SE4C2_1", "VBRK_SE4C2" ], [ "CLK_BUFG_REBUF_SE4C3_1", "VBRK_SE4C3" ], [ "CLK_BUFG_REBUF_SW2A0_1", "VBRK_SW2A0" ], [ "CLK_BUFG_REBUF_SW2A1_1", "VBRK_SW2A1" ], [ "CLK_BUFG_REBUF_SW2A2_1", "VBRK_SW2A2" ], [ "CLK_BUFG_REBUF_SW2A3_1", "VBRK_SW2A3" ], [ "CLK_BUFG_REBUF_SW4A0_1", "VBRK_SW4A0" ], [ "CLK_BUFG_REBUF_SW4A1_1", "VBRK_SW4A1" ], [ "CLK_BUFG_REBUF_SW4A2_1", "VBRK_SW4A2" ], [ "CLK_BUFG_REBUF_SW4A3_1", "VBRK_SW4A3" ], [ "CLK_BUFG_REBUF_SW4END0_1", "VBRK_SW4END0" ], [ "CLK_BUFG_REBUF_SW4END1_1", "VBRK_SW4END1" ], [ "CLK_BUFG_REBUF_SW4END2_1", "VBRK_SW4END2" ], [ "CLK_BUFG_REBUF_SW4END3_1", "VBRK_SW4END3" ], [ "CLK_BUFG_REBUF_WL1END0_1", "VBRK_WL1END0" ], [ "CLK_BUFG_REBUF_WL1END1_1", "VBRK_WL1END1" ], [ "CLK_BUFG_REBUF_WL1END2_1", "VBRK_WL1END2" ], [ "CLK_BUFG_REBUF_WL1END3_1", "VBRK_WL1END3" ], [ "CLK_BUFG_REBUF_WR1END0_1", "VBRK_WR1END0" ], [ "CLK_BUFG_REBUF_WR1END1_1", "VBRK_WR1END1" ], [ "CLK_BUFG_REBUF_WR1END2_1", "VBRK_WR1END2" ], [ "CLK_BUFG_REBUF_WR1END3_1", "VBRK_WR1END3" ], [ "CLK_BUFG_REBUF_WW2A0_1", "VBRK_WW2A0" ], [ "CLK_BUFG_REBUF_WW2A1_1", "VBRK_WW2A1" ], [ "CLK_BUFG_REBUF_WW2A2_1", "VBRK_WW2A2" ], [ "CLK_BUFG_REBUF_WW2A3_1", "VBRK_WW2A3" ], [ "CLK_BUFG_REBUF_WW2END0_1", "VBRK_WW2END0" ], [ "CLK_BUFG_REBUF_WW2END1_1", "VBRK_WW2END1" ], [ "CLK_BUFG_REBUF_WW2END2_1", "VBRK_WW2END2" ], [ "CLK_BUFG_REBUF_WW2END3_1", "VBRK_WW2END3" ], [ "CLK_BUFG_REBUF_WW4A0_1", "VBRK_WW4A0" ], [ "CLK_BUFG_REBUF_WW4A1_1", "VBRK_WW4A1" ], [ "CLK_BUFG_REBUF_WW4A2_1", "VBRK_WW4A2" ], [ "CLK_BUFG_REBUF_WW4A3_1", "VBRK_WW4A3" ], [ "CLK_BUFG_REBUF_WW4B0_1", "VBRK_WW4B0" ], [ "CLK_BUFG_REBUF_WW4B1_1", "VBRK_WW4B1" ], [ "CLK_BUFG_REBUF_WW4B2_1", "VBRK_WW4B2" ], [ "CLK_BUFG_REBUF_WW4B3_1", "VBRK_WW4B3" ], [ "CLK_BUFG_REBUF_WW4C0_1", "VBRK_WW4C0" ], [ "CLK_BUFG_REBUF_WW4C1_1", "VBRK_WW4C1" ], [ "CLK_BUFG_REBUF_WW4C2_1", "VBRK_WW4C2" ], [ "CLK_BUFG_REBUF_WW4C3_1", "VBRK_WW4C3" ], [ "CLK_BUFG_REBUF_WW4END0_1", "VBRK_WW4END0" ], [ "CLK_BUFG_REBUF_WW4END1_1", "VBRK_WW4END1" ], [ "CLK_BUFG_REBUF_WW4END2_1", "VBRK_WW4END2" ], [ "CLK_BUFG_REBUF_WW4END3_1", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLK_BUFG_REBUF", "VBRK" ], "wire_pairs": [ [ "CLK_BUFG_REBUF_EE2A0_0", "VBRK_EE2A0" ], [ "CLK_BUFG_REBUF_EE2A1_0", "VBRK_EE2A1" ], [ "CLK_BUFG_REBUF_EE2A2_0", "VBRK_EE2A2" ], [ "CLK_BUFG_REBUF_EE2A3_0", "VBRK_EE2A3" ], [ "CLK_BUFG_REBUF_EE2BEG0_0", "VBRK_EE2BEG0" ], [ "CLK_BUFG_REBUF_EE2BEG1_0", "VBRK_EE2BEG1" ], [ "CLK_BUFG_REBUF_EE2BEG2_0", "VBRK_EE2BEG2" ], [ "CLK_BUFG_REBUF_EE2BEG3_0", "VBRK_EE2BEG3" ], [ "CLK_BUFG_REBUF_EE4A0_0", "VBRK_EE4A0" ], [ "CLK_BUFG_REBUF_EE4A1_0", "VBRK_EE4A1" ], [ "CLK_BUFG_REBUF_EE4A2_0", "VBRK_EE4A2" ], [ "CLK_BUFG_REBUF_EE4A3_0", "VBRK_EE4A3" ], [ "CLK_BUFG_REBUF_EE4B0_0", "VBRK_EE4B0" ], [ "CLK_BUFG_REBUF_EE4B1_0", "VBRK_EE4B1" ], [ "CLK_BUFG_REBUF_EE4B2_0", "VBRK_EE4B2" ], [ "CLK_BUFG_REBUF_EE4B3_0", "VBRK_EE4B3" ], [ "CLK_BUFG_REBUF_EE4BEG0_0", "VBRK_EE4BEG0" ], [ "CLK_BUFG_REBUF_EE4BEG1_0", "VBRK_EE4BEG1" ], [ "CLK_BUFG_REBUF_EE4BEG2_0", "VBRK_EE4BEG2" ], [ "CLK_BUFG_REBUF_EE4BEG3_0", "VBRK_EE4BEG3" ], [ "CLK_BUFG_REBUF_EE4C0_0", "VBRK_EE4C0" ], [ "CLK_BUFG_REBUF_EE4C1_0", "VBRK_EE4C1" ], [ "CLK_BUFG_REBUF_EE4C2_0", "VBRK_EE4C2" ], [ "CLK_BUFG_REBUF_EE4C3_0", "VBRK_EE4C3" ], [ "CLK_BUFG_REBUF_EL1BEG0_0", "VBRK_EL1BEG0" ], [ "CLK_BUFG_REBUF_EL1BEG1_0", "VBRK_EL1BEG1" ], [ "CLK_BUFG_REBUF_EL1BEG2_0", "VBRK_EL1BEG2" ], [ "CLK_BUFG_REBUF_EL1BEG3_0", "VBRK_EL1BEG3" ], [ "CLK_BUFG_REBUF_ER1BEG0_0", "VBRK_ER1BEG0" ], [ "CLK_BUFG_REBUF_ER1BEG1_0", "VBRK_ER1BEG1" ], [ "CLK_BUFG_REBUF_ER1BEG2_0", "VBRK_ER1BEG2" ], [ "CLK_BUFG_REBUF_ER1BEG3_0", "VBRK_ER1BEG3" ], [ "CLK_BUFG_REBUF_LH1_0", "VBRK_LH1" ], [ "CLK_BUFG_REBUF_LH2_0", "VBRK_LH2" ], [ "CLK_BUFG_REBUF_LH3_0", "VBRK_LH3" ], [ "CLK_BUFG_REBUF_LH4_0", "VBRK_LH4" ], [ "CLK_BUFG_REBUF_LH5_0", "VBRK_LH5" ], [ "CLK_BUFG_REBUF_LH6_0", "VBRK_LH6" ], [ "CLK_BUFG_REBUF_LH7_0", "VBRK_LH7" ], [ "CLK_BUFG_REBUF_LH8_0", "VBRK_LH8" ], [ "CLK_BUFG_REBUF_LH9_0", "VBRK_LH9" ], [ "CLK_BUFG_REBUF_LH10_0", "VBRK_LH10" ], [ "CLK_BUFG_REBUF_LH11_0", "VBRK_LH11" ], [ "CLK_BUFG_REBUF_LH12_0", "VBRK_LH12" ], [ "CLK_BUFG_REBUF_NE2A0_0", "VBRK_NE2A0" ], [ "CLK_BUFG_REBUF_NE2A1_0", "VBRK_NE2A1" ], [ "CLK_BUFG_REBUF_NE2A2_0", "VBRK_NE2A2" ], [ "CLK_BUFG_REBUF_NE2A3_0", "VBRK_NE2A3" ], [ "CLK_BUFG_REBUF_NE4BEG0_0", "VBRK_NE4BEG0" ], [ "CLK_BUFG_REBUF_NE4BEG1_0", "VBRK_NE4BEG1" ], [ "CLK_BUFG_REBUF_NE4BEG2_0", "VBRK_NE4BEG2" ], [ "CLK_BUFG_REBUF_NE4BEG3_0", "VBRK_NE4BEG3" ], [ "CLK_BUFG_REBUF_NE4C0_0", "VBRK_NE4C0" ], [ "CLK_BUFG_REBUF_NE4C1_0", "VBRK_NE4C1" ], [ "CLK_BUFG_REBUF_NE4C2_0", "VBRK_NE4C2" ], [ "CLK_BUFG_REBUF_NE4C3_0", "VBRK_NE4C3" ], [ "CLK_BUFG_REBUF_NW2A0_0", "VBRK_NW2A0" ], [ "CLK_BUFG_REBUF_NW2A1_0", "VBRK_NW2A1" ], [ "CLK_BUFG_REBUF_NW2A2_0", "VBRK_NW2A2" ], [ "CLK_BUFG_REBUF_NW2A3_0", "VBRK_NW2A3" ], [ "CLK_BUFG_REBUF_NW4A0_0", "VBRK_NW4A0" ], [ "CLK_BUFG_REBUF_NW4A1_0", "VBRK_NW4A1" ], [ "CLK_BUFG_REBUF_NW4A2_0", "VBRK_NW4A2" ], [ "CLK_BUFG_REBUF_NW4A3_0", "VBRK_NW4A3" ], [ "CLK_BUFG_REBUF_NW4END0_0", "VBRK_NW4END0" ], [ "CLK_BUFG_REBUF_NW4END1_0", "VBRK_NW4END1" ], [ "CLK_BUFG_REBUF_NW4END2_0", "VBRK_NW4END2" ], [ "CLK_BUFG_REBUF_NW4END3_0", "VBRK_NW4END3" ], [ "CLK_BUFG_REBUF_SE2A0_0", "VBRK_SE2A0" ], [ "CLK_BUFG_REBUF_SE2A1_0", "VBRK_SE2A1" ], [ "CLK_BUFG_REBUF_SE2A2_0", "VBRK_SE2A2" ], [ "CLK_BUFG_REBUF_SE2A3_0", "VBRK_SE2A3" ], [ "CLK_BUFG_REBUF_SE4BEG0_0", "VBRK_SE4BEG0" ], [ "CLK_BUFG_REBUF_SE4BEG1_0", "VBRK_SE4BEG1" ], [ "CLK_BUFG_REBUF_SE4BEG2_0", "VBRK_SE4BEG2" ], [ "CLK_BUFG_REBUF_SE4BEG3_0", "VBRK_SE4BEG3" ], [ "CLK_BUFG_REBUF_SE4C0_0", "VBRK_SE4C0" ], [ "CLK_BUFG_REBUF_SE4C1_0", "VBRK_SE4C1" ], [ "CLK_BUFG_REBUF_SE4C2_0", "VBRK_SE4C2" ], [ "CLK_BUFG_REBUF_SE4C3_0", "VBRK_SE4C3" ], [ "CLK_BUFG_REBUF_SW2A0_0", "VBRK_SW2A0" ], [ "CLK_BUFG_REBUF_SW2A1_0", "VBRK_SW2A1" ], [ "CLK_BUFG_REBUF_SW2A2_0", "VBRK_SW2A2" ], [ "CLK_BUFG_REBUF_SW2A3_0", "VBRK_SW2A3" ], [ "CLK_BUFG_REBUF_SW4A0_0", "VBRK_SW4A0" ], [ "CLK_BUFG_REBUF_SW4A1_0", "VBRK_SW4A1" ], [ "CLK_BUFG_REBUF_SW4A2_0", "VBRK_SW4A2" ], [ "CLK_BUFG_REBUF_SW4A3_0", "VBRK_SW4A3" ], [ "CLK_BUFG_REBUF_SW4END0_0", "VBRK_SW4END0" ], [ "CLK_BUFG_REBUF_SW4END1_0", "VBRK_SW4END1" ], [ "CLK_BUFG_REBUF_SW4END2_0", "VBRK_SW4END2" ], [ "CLK_BUFG_REBUF_SW4END3_0", "VBRK_SW4END3" ], [ "CLK_BUFG_REBUF_WL1END0_0", "VBRK_WL1END0" ], [ "CLK_BUFG_REBUF_WL1END1_0", "VBRK_WL1END1" ], [ "CLK_BUFG_REBUF_WL1END2_0", "VBRK_WL1END2" ], [ "CLK_BUFG_REBUF_WL1END3_0", "VBRK_WL1END3" ], [ "CLK_BUFG_REBUF_WR1END0_0", "VBRK_WR1END0" ], [ "CLK_BUFG_REBUF_WR1END1_0", "VBRK_WR1END1" ], [ "CLK_BUFG_REBUF_WR1END2_0", "VBRK_WR1END2" ], [ "CLK_BUFG_REBUF_WR1END3_0", "VBRK_WR1END3" ], [ "CLK_BUFG_REBUF_WW2A0_0", "VBRK_WW2A0" ], [ "CLK_BUFG_REBUF_WW2A1_0", "VBRK_WW2A1" ], [ "CLK_BUFG_REBUF_WW2A2_0", "VBRK_WW2A2" ], [ "CLK_BUFG_REBUF_WW2A3_0", "VBRK_WW2A3" ], [ "CLK_BUFG_REBUF_WW2END0_0", "VBRK_WW2END0" ], [ "CLK_BUFG_REBUF_WW2END1_0", "VBRK_WW2END1" ], [ "CLK_BUFG_REBUF_WW2END2_0", "VBRK_WW2END2" ], [ "CLK_BUFG_REBUF_WW2END3_0", "VBRK_WW2END3" ], [ "CLK_BUFG_REBUF_WW4A0_0", "VBRK_WW4A0" ], [ "CLK_BUFG_REBUF_WW4A1_0", "VBRK_WW4A1" ], [ "CLK_BUFG_REBUF_WW4A2_0", "VBRK_WW4A2" ], [ "CLK_BUFG_REBUF_WW4A3_0", "VBRK_WW4A3" ], [ "CLK_BUFG_REBUF_WW4B0_0", "VBRK_WW4B0" ], [ "CLK_BUFG_REBUF_WW4B1_0", "VBRK_WW4B1" ], [ "CLK_BUFG_REBUF_WW4B2_0", "VBRK_WW4B2" ], [ "CLK_BUFG_REBUF_WW4B3_0", "VBRK_WW4B3" ], [ "CLK_BUFG_REBUF_WW4C0_0", "VBRK_WW4C0" ], [ "CLK_BUFG_REBUF_WW4C1_0", "VBRK_WW4C1" ], [ "CLK_BUFG_REBUF_WW4C2_0", "VBRK_WW4C2" ], [ "CLK_BUFG_REBUF_WW4C3_0", "VBRK_WW4C3" ], [ "CLK_BUFG_REBUF_WW4END0_0", "VBRK_WW4END0" ], [ "CLK_BUFG_REBUF_WW4END1_0", "VBRK_WW4END1" ], [ "CLK_BUFG_REBUF_WW4END2_0", "VBRK_WW4END2" ], [ "CLK_BUFG_REBUF_WW4END3_0", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 0, -4 ], "tile_types": [ "CLK_BUFG_TOP_R", "CLK_FEED" ], "wire_pairs": [ [ "CLK_BUFG_CK_GCLK0", "CLK_FEED_R_CK_GCLK0" ], [ "CLK_BUFG_CK_GCLK1", "CLK_FEED_R_CK_GCLK1" ], [ "CLK_BUFG_CK_GCLK2", "CLK_FEED_R_CK_GCLK2" ], [ "CLK_BUFG_CK_GCLK3", "CLK_FEED_R_CK_GCLK3" ], [ "CLK_BUFG_CK_GCLK4", "CLK_FEED_R_CK_GCLK4" ], [ "CLK_BUFG_CK_GCLK5", "CLK_FEED_R_CK_GCLK5" ], [ "CLK_BUFG_CK_GCLK6", "CLK_FEED_R_CK_GCLK6" ], [ "CLK_BUFG_CK_GCLK7", "CLK_FEED_R_CK_GCLK7" ], [ "CLK_BUFG_CK_GCLK8", "CLK_FEED_R_CK_GCLK8" ], [ "CLK_BUFG_CK_GCLK9", "CLK_FEED_R_CK_GCLK9" ], [ "CLK_BUFG_CK_GCLK10", "CLK_FEED_R_CK_GCLK10" ], [ "CLK_BUFG_CK_GCLK11", "CLK_FEED_R_CK_GCLK11" ], [ "CLK_BUFG_CK_GCLK12", "CLK_FEED_R_CK_GCLK12" ], [ "CLK_BUFG_CK_GCLK13", "CLK_FEED_R_CK_GCLK13" ], [ "CLK_BUFG_CK_GCLK14", "CLK_FEED_R_CK_GCLK14" ], [ "CLK_BUFG_CK_GCLK15", "CLK_FEED_R_CK_GCLK15" ], [ "CLK_BUFG_CK_GCLK16", "CLK_FEED_R_CK_GCLK16" ], [ "CLK_BUFG_CK_GCLK17", "CLK_FEED_R_CK_GCLK17" ], [ "CLK_BUFG_CK_GCLK18", "CLK_FEED_R_CK_GCLK18" ], [ "CLK_BUFG_CK_GCLK19", "CLK_FEED_R_CK_GCLK19" ], [ "CLK_BUFG_CK_GCLK20", "CLK_FEED_R_CK_GCLK20" ], [ "CLK_BUFG_CK_GCLK21", "CLK_FEED_R_CK_GCLK21" ], [ "CLK_BUFG_CK_GCLK22", "CLK_FEED_R_CK_GCLK22" ], [ "CLK_BUFG_CK_GCLK23", "CLK_FEED_R_CK_GCLK23" ], [ "CLK_BUFG_CK_GCLK24", "CLK_FEED_R_CK_GCLK24" ], [ "CLK_BUFG_CK_GCLK25", "CLK_FEED_R_CK_GCLK25" ], [ "CLK_BUFG_CK_GCLK26", "CLK_FEED_R_CK_GCLK26" ], [ "CLK_BUFG_CK_GCLK27", "CLK_FEED_R_CK_GCLK27" ], [ "CLK_BUFG_CK_GCLK28", "CLK_FEED_R_CK_GCLK28" ], [ "CLK_BUFG_CK_GCLK29", "CLK_FEED_R_CK_GCLK29" ], [ "CLK_BUFG_CK_GCLK30", "CLK_FEED_R_CK_GCLK30" ], [ "CLK_BUFG_CK_GCLK31", "CLK_FEED_R_CK_GCLK31" ], [ "CLK_BUFG_TOP_R_CK_MUXED0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ "CLK_BUFG_TOP_R_CK_MUXED1", "CLK_FEED_R_CK_BUFG_CASC1" ], [ "CLK_BUFG_TOP_R_CK_MUXED2", "CLK_FEED_R_CK_BUFG_CASC2" ], [ "CLK_BUFG_TOP_R_CK_MUXED3", "CLK_FEED_R_CK_BUFG_CASC3" ], [ "CLK_BUFG_TOP_R_CK_MUXED4", "CLK_FEED_R_CK_BUFG_CASC4" ], [ "CLK_BUFG_TOP_R_CK_MUXED5", "CLK_FEED_R_CK_BUFG_CASC5" ], [ "CLK_BUFG_TOP_R_CK_MUXED6", "CLK_FEED_R_CK_BUFG_CASC6" ], [ "CLK_BUFG_TOP_R_CK_MUXED7", "CLK_FEED_R_CK_BUFG_CASC7" ], [ "CLK_BUFG_TOP_R_CK_MUXED8", "CLK_FEED_R_CK_BUFG_CASC8" ], [ "CLK_BUFG_TOP_R_CK_MUXED9", "CLK_FEED_R_CK_BUFG_CASC9" ], [ "CLK_BUFG_TOP_R_CK_MUXED10", "CLK_FEED_R_CK_BUFG_CASC10" ], [ "CLK_BUFG_TOP_R_CK_MUXED11", "CLK_FEED_R_CK_BUFG_CASC11" ], [ "CLK_BUFG_TOP_R_CK_MUXED12", "CLK_FEED_R_CK_BUFG_CASC12" ], [ "CLK_BUFG_TOP_R_CK_MUXED13", "CLK_FEED_R_CK_BUFG_CASC13" ], [ "CLK_BUFG_TOP_R_CK_MUXED14", "CLK_FEED_R_CK_BUFG_CASC14" ], [ "CLK_BUFG_TOP_R_CK_MUXED15", "CLK_FEED_R_CK_BUFG_CASC15" ], [ "CLK_BUFG_TOP_R_CK_MUXED16", "CLK_FEED_R_CK_BUFG_CASC16" ], [ "CLK_BUFG_TOP_R_CK_MUXED17", "CLK_FEED_R_CK_BUFG_CASC17" ], [ "CLK_BUFG_TOP_R_CK_MUXED18", "CLK_FEED_R_CK_BUFG_CASC18" ], [ "CLK_BUFG_TOP_R_CK_MUXED19", "CLK_FEED_R_CK_BUFG_CASC19" ], [ "CLK_BUFG_TOP_R_CK_MUXED20", "CLK_FEED_R_CK_BUFG_CASC20" ], [ "CLK_BUFG_TOP_R_CK_MUXED21", "CLK_FEED_R_CK_BUFG_CASC21" ], [ "CLK_BUFG_TOP_R_CK_MUXED22", "CLK_FEED_R_CK_BUFG_CASC22" ], [ "CLK_BUFG_TOP_R_CK_MUXED23", "CLK_FEED_R_CK_BUFG_CASC23" ], [ "CLK_BUFG_TOP_R_CK_MUXED24", "CLK_FEED_R_CK_BUFG_CASC24" ], [ "CLK_BUFG_TOP_R_CK_MUXED25", "CLK_FEED_R_CK_BUFG_CASC25" ], [ "CLK_BUFG_TOP_R_CK_MUXED26", "CLK_FEED_R_CK_BUFG_CASC26" ], [ "CLK_BUFG_TOP_R_CK_MUXED27", "CLK_FEED_R_CK_BUFG_CASC27" ], [ "CLK_BUFG_TOP_R_CK_MUXED28", "CLK_FEED_R_CK_BUFG_CASC28" ], [ "CLK_BUFG_TOP_R_CK_MUXED29", "CLK_FEED_R_CK_BUFG_CASC29" ], [ "CLK_BUFG_TOP_R_CK_MUXED30", "CLK_FEED_R_CK_BUFG_CASC30" ], [ "CLK_BUFG_TOP_R_CK_MUXED31", "CLK_FEED_R_CK_BUFG_CASC31" ] ] }, { "grid_deltas": [ -1, -3 ], "tile_types": [ "CLK_BUFG_TOP_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_BUFG_IMUX0_3", "INT_INTERFACE_IMUX0" ], [ "CLK_BUFG_IMUX1_3", "INT_INTERFACE_IMUX1" ], [ "CLK_BUFG_IMUX2_3", "INT_INTERFACE_IMUX2" ], [ "CLK_BUFG_IMUX3_3", "INT_INTERFACE_IMUX3" ], [ "CLK_BUFG_IMUX4_3", "INT_INTERFACE_IMUX4" ], [ "CLK_BUFG_IMUX5_3", "INT_INTERFACE_IMUX5" ], [ "CLK_BUFG_IMUX6_3", "INT_INTERFACE_IMUX6" ], [ "CLK_BUFG_IMUX7_3", "INT_INTERFACE_IMUX7" ], [ "CLK_BUFG_IMUX8_3", "INT_INTERFACE_IMUX8" ], [ "CLK_BUFG_IMUX9_3", "INT_INTERFACE_IMUX9" ], [ "CLK_BUFG_IMUX10_3", "INT_INTERFACE_IMUX10" ], [ "CLK_BUFG_IMUX11_3", "INT_INTERFACE_IMUX11" ], [ "CLK_BUFG_IMUX12_3", "INT_INTERFACE_IMUX12" ], [ "CLK_BUFG_IMUX13_3", "INT_INTERFACE_IMUX13" ], [ "CLK_BUFG_IMUX14_3", "INT_INTERFACE_IMUX14" ], [ "CLK_BUFG_IMUX15_3", "INT_INTERFACE_IMUX15" ], [ "CLK_BUFG_IMUX16_3", "INT_INTERFACE_IMUX16" ], [ "CLK_BUFG_IMUX17_3", "INT_INTERFACE_IMUX17" ], [ "CLK_BUFG_IMUX18_3", "INT_INTERFACE_IMUX18" ], [ "CLK_BUFG_IMUX19_3", "INT_INTERFACE_IMUX19" ], [ "CLK_BUFG_IMUX20_3", "INT_INTERFACE_IMUX20" ], [ "CLK_BUFG_IMUX21_3", "INT_INTERFACE_IMUX21" ], [ "CLK_BUFG_IMUX22_3", "INT_INTERFACE_IMUX22" ], [ "CLK_BUFG_IMUX23_3", "INT_INTERFACE_IMUX23" ], [ "CLK_BUFG_IMUX24_3", "INT_INTERFACE_IMUX24" ], [ "CLK_BUFG_IMUX25_3", "INT_INTERFACE_IMUX25" ], [ "CLK_BUFG_IMUX26_3", "INT_INTERFACE_IMUX26" ], [ "CLK_BUFG_IMUX27_3", "INT_INTERFACE_IMUX27" ], [ "CLK_BUFG_IMUX28_3", "INT_INTERFACE_IMUX28" ], [ "CLK_BUFG_IMUX29_3", "INT_INTERFACE_IMUX29" ], [ "CLK_BUFG_IMUX30_3", "INT_INTERFACE_IMUX30" ], [ "CLK_BUFG_IMUX31_3", "INT_INTERFACE_IMUX31" ], [ "CLK_BUFG_IMUX32_3", "INT_INTERFACE_IMUX32" ], [ "CLK_BUFG_IMUX33_3", "INT_INTERFACE_IMUX33" ], [ "CLK_BUFG_IMUX34_3", "INT_INTERFACE_IMUX34" ], [ "CLK_BUFG_IMUX35_3", "INT_INTERFACE_IMUX35" ], [ "CLK_BUFG_IMUX36_3", "INT_INTERFACE_IMUX36" ], [ "CLK_BUFG_IMUX37_3", "INT_INTERFACE_IMUX37" ], [ "CLK_BUFG_IMUX38_3", "INT_INTERFACE_IMUX38" ], [ "CLK_BUFG_IMUX39_3", "INT_INTERFACE_IMUX39" ], [ "CLK_BUFG_IMUX40_3", "INT_INTERFACE_IMUX40" ], [ "CLK_BUFG_IMUX41_3", "INT_INTERFACE_IMUX41" ], [ "CLK_BUFG_IMUX42_3", "INT_INTERFACE_IMUX42" ], [ "CLK_BUFG_IMUX43_3", "INT_INTERFACE_IMUX43" ], [ "CLK_BUFG_IMUX44_3", "INT_INTERFACE_IMUX44" ], [ "CLK_BUFG_IMUX45_3", "INT_INTERFACE_IMUX45" ], [ "CLK_BUFG_IMUX46_3", "INT_INTERFACE_IMUX46" ], [ "CLK_BUFG_IMUX47_3", "INT_INTERFACE_IMUX47" ], [ "CLK_BUFG_LOGIC_OUTS_B0_3", "INT_INTERFACE_LOGIC_OUTS_B0" ], [ "CLK_BUFG_LOGIC_OUTS_B1_3", "INT_INTERFACE_LOGIC_OUTS_B1" ], [ "CLK_BUFG_LOGIC_OUTS_B2_3", "INT_INTERFACE_LOGIC_OUTS_B2" ], [ "CLK_BUFG_LOGIC_OUTS_B3_3", "INT_INTERFACE_LOGIC_OUTS_B3" ], [ "CLK_BUFG_LOGIC_OUTS_B4_3", "INT_INTERFACE_LOGIC_OUTS_B4" ], [ "CLK_BUFG_LOGIC_OUTS_B5_3", "INT_INTERFACE_LOGIC_OUTS_B5" ], [ "CLK_BUFG_LOGIC_OUTS_B6_3", "INT_INTERFACE_LOGIC_OUTS_B6" ], [ "CLK_BUFG_LOGIC_OUTS_B7_3", "INT_INTERFACE_LOGIC_OUTS_B7" ], [ "CLK_HROW_BYP0_3", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_3", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_3", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_3", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_3", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_3", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_3", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_3", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_3", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_3", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_3", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_3", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_3", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_3", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_3", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_3", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_3", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_3", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_3", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_3", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_3", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_3", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_3", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_3", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_3", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_3", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_3", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_3", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_3", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_3", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_3", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_3", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_3", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_3", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_3", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_3", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_3", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_3", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_3", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_3", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_3", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_3", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_3", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_3", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_3", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_3", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_3", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_3", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_3", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_3", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_3", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_3", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_LH1_3", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_3", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_3", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_3", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_3", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_3", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_3", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_3", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_3", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_3", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_3", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_3", "INT_INTERFACE_LH12" ], [ "CLK_HROW_MONITOR_N_3", "INT_INTERFACE_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_3", "INT_INTERFACE_MONITOR_P" ], [ "CLK_HROW_NE2A0_3", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_3", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_3", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_3", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_3", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_3", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_3", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_3", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_3", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_3", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_3", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_3", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_3", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_3", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_3", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_3", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_3", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_3", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_3", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_3", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_3", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_3", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_3", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_3", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_3", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_3", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_3", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_3", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_3", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_3", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_3", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_3", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_3", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_3", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_3", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_3", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_3", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_3", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_3", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_3", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_3", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_3", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_3", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_3", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_3", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_3", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_3", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_3", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_3", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_3", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_3", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_3", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_3", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_3", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_3", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_3", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_3", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_3", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_3", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_3", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_3", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_3", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_3", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_3", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_3", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_3", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_3", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_3", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_3", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_3", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_3", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_3", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_3", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_3", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_3", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_3", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_3", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_3", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_3", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_3", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -2 ], "tile_types": [ "CLK_BUFG_TOP_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_BUFG_IMUX0_2", "INT_INTERFACE_IMUX0" ], [ "CLK_BUFG_IMUX1_2", "INT_INTERFACE_IMUX1" ], [ "CLK_BUFG_IMUX2_2", "INT_INTERFACE_IMUX2" ], [ "CLK_BUFG_IMUX3_2", "INT_INTERFACE_IMUX3" ], [ "CLK_BUFG_IMUX4_2", "INT_INTERFACE_IMUX4" ], [ "CLK_BUFG_IMUX5_2", "INT_INTERFACE_IMUX5" ], [ "CLK_BUFG_IMUX6_2", "INT_INTERFACE_IMUX6" ], [ "CLK_BUFG_IMUX7_2", "INT_INTERFACE_IMUX7" ], [ "CLK_BUFG_IMUX8_2", "INT_INTERFACE_IMUX8" ], [ "CLK_BUFG_IMUX9_2", "INT_INTERFACE_IMUX9" ], [ "CLK_BUFG_IMUX10_2", "INT_INTERFACE_IMUX10" ], [ "CLK_BUFG_IMUX11_2", "INT_INTERFACE_IMUX11" ], [ "CLK_BUFG_IMUX12_2", "INT_INTERFACE_IMUX12" ], [ "CLK_BUFG_IMUX13_2", "INT_INTERFACE_IMUX13" ], [ "CLK_BUFG_IMUX14_2", "INT_INTERFACE_IMUX14" ], [ "CLK_BUFG_IMUX15_2", "INT_INTERFACE_IMUX15" ], [ "CLK_BUFG_IMUX16_2", "INT_INTERFACE_IMUX16" ], [ "CLK_BUFG_IMUX17_2", "INT_INTERFACE_IMUX17" ], [ "CLK_BUFG_IMUX18_2", "INT_INTERFACE_IMUX18" ], [ "CLK_BUFG_IMUX19_2", "INT_INTERFACE_IMUX19" ], [ "CLK_BUFG_IMUX20_2", "INT_INTERFACE_IMUX20" ], [ "CLK_BUFG_IMUX21_2", "INT_INTERFACE_IMUX21" ], [ "CLK_BUFG_IMUX22_2", "INT_INTERFACE_IMUX22" ], [ "CLK_BUFG_IMUX23_2", "INT_INTERFACE_IMUX23" ], [ "CLK_BUFG_IMUX24_2", "INT_INTERFACE_IMUX24" ], [ "CLK_BUFG_IMUX25_2", "INT_INTERFACE_IMUX25" ], [ "CLK_BUFG_IMUX26_2", "INT_INTERFACE_IMUX26" ], [ "CLK_BUFG_IMUX27_2", "INT_INTERFACE_IMUX27" ], [ "CLK_BUFG_IMUX28_2", "INT_INTERFACE_IMUX28" ], [ "CLK_BUFG_IMUX29_2", "INT_INTERFACE_IMUX29" ], [ "CLK_BUFG_IMUX30_2", "INT_INTERFACE_IMUX30" ], [ "CLK_BUFG_IMUX31_2", "INT_INTERFACE_IMUX31" ], [ "CLK_BUFG_IMUX32_2", "INT_INTERFACE_IMUX32" ], [ "CLK_BUFG_IMUX33_2", "INT_INTERFACE_IMUX33" ], [ "CLK_BUFG_IMUX34_2", "INT_INTERFACE_IMUX34" ], [ "CLK_BUFG_IMUX35_2", "INT_INTERFACE_IMUX35" ], [ "CLK_BUFG_IMUX36_2", "INT_INTERFACE_IMUX36" ], [ "CLK_BUFG_IMUX37_2", "INT_INTERFACE_IMUX37" ], [ "CLK_BUFG_IMUX38_2", "INT_INTERFACE_IMUX38" ], [ "CLK_BUFG_IMUX39_2", "INT_INTERFACE_IMUX39" ], [ "CLK_BUFG_IMUX40_2", "INT_INTERFACE_IMUX40" ], [ "CLK_BUFG_IMUX41_2", "INT_INTERFACE_IMUX41" ], [ "CLK_BUFG_IMUX42_2", "INT_INTERFACE_IMUX42" ], [ "CLK_BUFG_IMUX43_2", "INT_INTERFACE_IMUX43" ], [ "CLK_BUFG_IMUX44_2", "INT_INTERFACE_IMUX44" ], [ "CLK_BUFG_IMUX45_2", "INT_INTERFACE_IMUX45" ], [ "CLK_BUFG_IMUX46_2", "INT_INTERFACE_IMUX46" ], [ "CLK_BUFG_IMUX47_2", "INT_INTERFACE_IMUX47" ], [ "CLK_BUFG_LOGIC_OUTS_B0_2", "INT_INTERFACE_LOGIC_OUTS_B0" ], [ "CLK_BUFG_LOGIC_OUTS_B1_2", "INT_INTERFACE_LOGIC_OUTS_B1" ], [ "CLK_BUFG_LOGIC_OUTS_B2_2", "INT_INTERFACE_LOGIC_OUTS_B2" ], [ "CLK_BUFG_LOGIC_OUTS_B3_2", "INT_INTERFACE_LOGIC_OUTS_B3" ], [ "CLK_BUFG_LOGIC_OUTS_B4_2", "INT_INTERFACE_LOGIC_OUTS_B4" ], [ "CLK_BUFG_LOGIC_OUTS_B5_2", "INT_INTERFACE_LOGIC_OUTS_B5" ], [ "CLK_BUFG_LOGIC_OUTS_B6_2", "INT_INTERFACE_LOGIC_OUTS_B6" ], [ "CLK_BUFG_LOGIC_OUTS_B7_2", "INT_INTERFACE_LOGIC_OUTS_B7" ], [ "CLK_HROW_BYP0_2", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_2", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_2", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_2", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_2", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_2", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_2", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_2", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_2", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_2", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_2", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_2", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_2", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_2", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_2", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_2", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_2", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_2", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_2", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_2", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_2", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_2", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_2", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_2", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_2", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_2", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_2", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_2", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_2", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_2", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_2", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_2", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_2", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_2", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_2", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_2", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_2", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_2", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_2", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_2", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_2", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_2", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_2", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_2", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_2", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_2", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_2", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_2", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_2", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_2", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_2", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_2", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_LH1_2", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_2", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_2", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_2", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_2", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_2", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_2", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_2", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_2", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_2", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_2", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_2", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_2", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_2", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_2", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_2", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_2", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_2", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_2", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_2", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_2", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_2", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_2", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_2", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_2", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_2", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_2", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_2", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_2", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_2", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_2", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_2", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_2", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_2", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_2", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_2", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_2", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_2", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_2", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_2", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_2", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_2", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_2", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_2", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_2", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_2", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_2", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_2", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_2", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_2", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_2", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_2", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_2", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_2", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_2", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_2", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_2", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_2", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_2", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_2", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_2", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_2", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_2", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_2", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_2", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_2", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_2", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_2", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_2", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_2", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_2", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_2", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_2", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_2", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_2", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_2", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_2", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_2", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_2", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_2", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_2", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_2", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_2", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_2", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_2", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_2", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_2", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_2", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_2", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_2", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_2", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_2", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -1 ], "tile_types": [ "CLK_BUFG_TOP_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_BUFG_IMUX0_1", "INT_INTERFACE_IMUX0" ], [ "CLK_BUFG_IMUX1_1", "INT_INTERFACE_IMUX1" ], [ "CLK_BUFG_IMUX2_1", "INT_INTERFACE_IMUX2" ], [ "CLK_BUFG_IMUX3_1", "INT_INTERFACE_IMUX3" ], [ "CLK_BUFG_IMUX4_1", "INT_INTERFACE_IMUX4" ], [ "CLK_BUFG_IMUX5_1", "INT_INTERFACE_IMUX5" ], [ "CLK_BUFG_IMUX6_1", "INT_INTERFACE_IMUX6" ], [ "CLK_BUFG_IMUX7_1", "INT_INTERFACE_IMUX7" ], [ "CLK_BUFG_IMUX8_1", "INT_INTERFACE_IMUX8" ], [ "CLK_BUFG_IMUX9_1", "INT_INTERFACE_IMUX9" ], [ "CLK_BUFG_IMUX10_1", "INT_INTERFACE_IMUX10" ], [ "CLK_BUFG_IMUX11_1", "INT_INTERFACE_IMUX11" ], [ "CLK_BUFG_IMUX12_1", "INT_INTERFACE_IMUX12" ], [ "CLK_BUFG_IMUX13_1", "INT_INTERFACE_IMUX13" ], [ "CLK_BUFG_IMUX14_1", "INT_INTERFACE_IMUX14" ], [ "CLK_BUFG_IMUX15_1", "INT_INTERFACE_IMUX15" ], [ "CLK_BUFG_IMUX16_1", "INT_INTERFACE_IMUX16" ], [ "CLK_BUFG_IMUX17_1", "INT_INTERFACE_IMUX17" ], [ "CLK_BUFG_IMUX18_1", "INT_INTERFACE_IMUX18" ], [ "CLK_BUFG_IMUX19_1", "INT_INTERFACE_IMUX19" ], [ "CLK_BUFG_IMUX20_1", "INT_INTERFACE_IMUX20" ], [ "CLK_BUFG_IMUX21_1", "INT_INTERFACE_IMUX21" ], [ "CLK_BUFG_IMUX22_1", "INT_INTERFACE_IMUX22" ], [ "CLK_BUFG_IMUX23_1", "INT_INTERFACE_IMUX23" ], [ "CLK_BUFG_IMUX24_1", "INT_INTERFACE_IMUX24" ], [ "CLK_BUFG_IMUX25_1", "INT_INTERFACE_IMUX25" ], [ "CLK_BUFG_IMUX26_1", "INT_INTERFACE_IMUX26" ], [ "CLK_BUFG_IMUX27_1", "INT_INTERFACE_IMUX27" ], [ "CLK_BUFG_IMUX28_1", "INT_INTERFACE_IMUX28" ], [ "CLK_BUFG_IMUX29_1", "INT_INTERFACE_IMUX29" ], [ "CLK_BUFG_IMUX30_1", "INT_INTERFACE_IMUX30" ], [ "CLK_BUFG_IMUX31_1", "INT_INTERFACE_IMUX31" ], [ "CLK_BUFG_IMUX32_1", "INT_INTERFACE_IMUX32" ], [ "CLK_BUFG_IMUX33_1", "INT_INTERFACE_IMUX33" ], [ "CLK_BUFG_IMUX34_1", "INT_INTERFACE_IMUX34" ], [ "CLK_BUFG_IMUX35_1", "INT_INTERFACE_IMUX35" ], [ "CLK_BUFG_IMUX36_1", "INT_INTERFACE_IMUX36" ], [ "CLK_BUFG_IMUX37_1", "INT_INTERFACE_IMUX37" ], [ "CLK_BUFG_IMUX38_1", "INT_INTERFACE_IMUX38" ], [ "CLK_BUFG_IMUX39_1", "INT_INTERFACE_IMUX39" ], [ "CLK_BUFG_IMUX40_1", "INT_INTERFACE_IMUX40" ], [ "CLK_BUFG_IMUX41_1", "INT_INTERFACE_IMUX41" ], [ "CLK_BUFG_IMUX42_1", "INT_INTERFACE_IMUX42" ], [ "CLK_BUFG_IMUX43_1", "INT_INTERFACE_IMUX43" ], [ "CLK_BUFG_IMUX44_1", "INT_INTERFACE_IMUX44" ], [ "CLK_BUFG_IMUX45_1", "INT_INTERFACE_IMUX45" ], [ "CLK_BUFG_IMUX46_1", "INT_INTERFACE_IMUX46" ], [ "CLK_BUFG_IMUX47_1", "INT_INTERFACE_IMUX47" ], [ "CLK_BUFG_LOGIC_OUTS_B0_1", "INT_INTERFACE_LOGIC_OUTS_B0" ], [ "CLK_BUFG_LOGIC_OUTS_B1_1", "INT_INTERFACE_LOGIC_OUTS_B1" ], [ "CLK_BUFG_LOGIC_OUTS_B2_1", "INT_INTERFACE_LOGIC_OUTS_B2" ], [ "CLK_BUFG_LOGIC_OUTS_B3_1", "INT_INTERFACE_LOGIC_OUTS_B3" ], [ "CLK_BUFG_LOGIC_OUTS_B4_1", "INT_INTERFACE_LOGIC_OUTS_B4" ], [ "CLK_BUFG_LOGIC_OUTS_B5_1", "INT_INTERFACE_LOGIC_OUTS_B5" ], [ "CLK_BUFG_LOGIC_OUTS_B6_1", "INT_INTERFACE_LOGIC_OUTS_B6" ], [ "CLK_BUFG_LOGIC_OUTS_B7_1", "INT_INTERFACE_LOGIC_OUTS_B7" ], [ "CLK_HROW_BYP0_1", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_1", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_1", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_1", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_1", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_1", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_1", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_1", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_1", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_1", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_1", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_1", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_1", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_1", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_1", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_1", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_1", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_1", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_1", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_1", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_1", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_1", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_1", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_1", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_1", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_1", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_1", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_1", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_1", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_1", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_1", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_1", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_1", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_1", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_1", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_1", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_1", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_1", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_1", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_1", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_1", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_1", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_1", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_1", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_1", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_1", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_1", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_1", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_1", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_1", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_1", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_1", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_LH1_1", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_1", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_1", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_1", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_1", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_1", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_1", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_1", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_1", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_1", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_1", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_1", "INT_INTERFACE_LH12" ], [ "CLK_HROW_MONITOR_N_1", "INT_INTERFACE_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_1", "INT_INTERFACE_MONITOR_P" ], [ "CLK_HROW_NE2A0_1", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_1", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_1", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_1", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_1", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_1", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_1", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_1", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_1", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_1", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_1", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_1", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_1", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_1", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_1", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_1", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_1", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_1", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_1", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_1", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_1", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_1", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_1", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_1", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_1", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_1", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_1", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_1", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_1", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_1", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_1", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_1", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_1", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_1", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_1", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_1", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_1", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_1", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_1", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_1", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_1", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_1", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_1", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_1", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_1", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_1", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_1", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_1", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_1", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_1", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_1", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_1", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_1", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_1", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_1", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_1", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_1", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_1", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_1", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_1", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_1", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_1", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_1", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_1", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_1", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_1", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_1", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_1", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_1", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_1", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_1", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_1", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_1", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_1", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_1", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_1", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_1", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_1", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_1", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_1", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "CLK_BUFG_TOP_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_BUFG_IMUX0_0", "INT_INTERFACE_IMUX0" ], [ "CLK_BUFG_IMUX1_0", "INT_INTERFACE_IMUX1" ], [ "CLK_BUFG_IMUX2_0", "INT_INTERFACE_IMUX2" ], [ "CLK_BUFG_IMUX3_0", "INT_INTERFACE_IMUX3" ], [ "CLK_BUFG_IMUX4_0", "INT_INTERFACE_IMUX4" ], [ "CLK_BUFG_IMUX5_0", "INT_INTERFACE_IMUX5" ], [ "CLK_BUFG_IMUX6_0", "INT_INTERFACE_IMUX6" ], [ "CLK_BUFG_IMUX7_0", "INT_INTERFACE_IMUX7" ], [ "CLK_BUFG_IMUX8_0", "INT_INTERFACE_IMUX8" ], [ "CLK_BUFG_IMUX9_0", "INT_INTERFACE_IMUX9" ], [ "CLK_BUFG_IMUX10_0", "INT_INTERFACE_IMUX10" ], [ "CLK_BUFG_IMUX11_0", "INT_INTERFACE_IMUX11" ], [ "CLK_BUFG_IMUX12_0", "INT_INTERFACE_IMUX12" ], [ "CLK_BUFG_IMUX13_0", "INT_INTERFACE_IMUX13" ], [ "CLK_BUFG_IMUX14_0", "INT_INTERFACE_IMUX14" ], [ "CLK_BUFG_IMUX15_0", "INT_INTERFACE_IMUX15" ], [ "CLK_BUFG_IMUX16_0", "INT_INTERFACE_IMUX16" ], [ "CLK_BUFG_IMUX17_0", "INT_INTERFACE_IMUX17" ], [ "CLK_BUFG_IMUX18_0", "INT_INTERFACE_IMUX18" ], [ "CLK_BUFG_IMUX19_0", "INT_INTERFACE_IMUX19" ], [ "CLK_BUFG_IMUX20_0", "INT_INTERFACE_IMUX20" ], [ "CLK_BUFG_IMUX21_0", "INT_INTERFACE_IMUX21" ], [ "CLK_BUFG_IMUX22_0", "INT_INTERFACE_IMUX22" ], [ "CLK_BUFG_IMUX23_0", "INT_INTERFACE_IMUX23" ], [ "CLK_BUFG_IMUX24_0", "INT_INTERFACE_IMUX24" ], [ "CLK_BUFG_IMUX25_0", "INT_INTERFACE_IMUX25" ], [ "CLK_BUFG_IMUX26_0", "INT_INTERFACE_IMUX26" ], [ "CLK_BUFG_IMUX27_0", "INT_INTERFACE_IMUX27" ], [ "CLK_BUFG_IMUX28_0", "INT_INTERFACE_IMUX28" ], [ "CLK_BUFG_IMUX29_0", "INT_INTERFACE_IMUX29" ], [ "CLK_BUFG_IMUX30_0", "INT_INTERFACE_IMUX30" ], [ "CLK_BUFG_IMUX31_0", "INT_INTERFACE_IMUX31" ], [ "CLK_BUFG_IMUX32_0", "INT_INTERFACE_IMUX32" ], [ "CLK_BUFG_IMUX33_0", "INT_INTERFACE_IMUX33" ], [ "CLK_BUFG_IMUX34_0", "INT_INTERFACE_IMUX34" ], [ "CLK_BUFG_IMUX35_0", "INT_INTERFACE_IMUX35" ], [ "CLK_BUFG_IMUX36_0", "INT_INTERFACE_IMUX36" ], [ "CLK_BUFG_IMUX37_0", "INT_INTERFACE_IMUX37" ], [ "CLK_BUFG_IMUX38_0", "INT_INTERFACE_IMUX38" ], [ "CLK_BUFG_IMUX39_0", "INT_INTERFACE_IMUX39" ], [ "CLK_BUFG_IMUX40_0", "INT_INTERFACE_IMUX40" ], [ "CLK_BUFG_IMUX41_0", "INT_INTERFACE_IMUX41" ], [ "CLK_BUFG_IMUX42_0", "INT_INTERFACE_IMUX42" ], [ "CLK_BUFG_IMUX43_0", "INT_INTERFACE_IMUX43" ], [ "CLK_BUFG_IMUX44_0", "INT_INTERFACE_IMUX44" ], [ "CLK_BUFG_IMUX45_0", "INT_INTERFACE_IMUX45" ], [ "CLK_BUFG_IMUX46_0", "INT_INTERFACE_IMUX46" ], [ "CLK_BUFG_IMUX47_0", "INT_INTERFACE_IMUX47" ], [ "CLK_BUFG_LOGIC_OUTS_B0_0", "INT_INTERFACE_LOGIC_OUTS_B0" ], [ "CLK_BUFG_LOGIC_OUTS_B1_0", "INT_INTERFACE_LOGIC_OUTS_B1" ], [ "CLK_BUFG_LOGIC_OUTS_B2_0", "INT_INTERFACE_LOGIC_OUTS_B2" ], [ "CLK_BUFG_LOGIC_OUTS_B3_0", "INT_INTERFACE_LOGIC_OUTS_B3" ], [ "CLK_BUFG_LOGIC_OUTS_B4_0", "INT_INTERFACE_LOGIC_OUTS_B4" ], [ "CLK_BUFG_LOGIC_OUTS_B5_0", "INT_INTERFACE_LOGIC_OUTS_B5" ], [ "CLK_BUFG_LOGIC_OUTS_B6_0", "INT_INTERFACE_LOGIC_OUTS_B6" ], [ "CLK_BUFG_LOGIC_OUTS_B7_0", "INT_INTERFACE_LOGIC_OUTS_B7" ], [ "CLK_HROW_BYP0_0", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_0", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_0", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_0", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_0", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_0", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_0", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_0", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_0", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_0", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_0", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_0", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_0", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_0", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_0", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_0", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_0", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_0", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_0", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_0", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_0", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_0", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_0", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_0", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_0", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_0", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_0", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_0", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_0", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_0", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_0", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_0", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_0", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_0", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_0", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_0", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_0", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_0", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_0", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_0", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_0", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_0", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_0", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_0", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_0", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_0", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_0", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_0", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_0", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_0", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_0", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_0", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_LH1_0", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_0", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_0", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_0", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_0", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_0", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_0", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_0", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_0", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_0", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_0", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_0", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_0", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_0", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_0", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_0", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_0", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_0", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_0", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_0", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_0", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_0", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_0", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_0", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_0", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_0", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_0", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_0", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_0", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_0", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_0", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_0", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_0", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_0", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_0", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_0", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_0", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_0", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_0", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_0", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_0", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_0", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_0", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_0", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_0", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_0", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_0", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_0", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_0", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_0", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_0", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_0", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_0", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_0", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_0", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_0", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_0", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_0", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_0", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_0", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_0", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_0", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_0", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_0", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_0", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_0", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_0", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_0", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_0", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_0", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_0", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_0", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_0", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_0", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_0", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_0", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_0", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_0", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_0", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_0", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_0", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_0", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_0", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_0", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_0", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_0", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_0", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_0", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_0", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_0", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_0", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_0", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ 1, -3 ], "tile_types": [ "CLK_BUFG_TOP_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_3", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_3", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_3", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_3", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_3", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_3", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_3", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_3", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_3", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_3", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_3", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_3", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_3", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_3", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_3", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_3", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_3", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_3", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_3", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_3", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_3", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_3", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_3", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_3", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_3", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_3", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_3", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_3", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_3", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_3", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_3", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_3", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_3", "VBRK_LH1" ], [ "CLK_HROW_LH2_3", "VBRK_LH2" ], [ "CLK_HROW_LH3_3", "VBRK_LH3" ], [ "CLK_HROW_LH4_3", "VBRK_LH4" ], [ "CLK_HROW_LH5_3", "VBRK_LH5" ], [ "CLK_HROW_LH6_3", "VBRK_LH6" ], [ "CLK_HROW_LH7_3", "VBRK_LH7" ], [ "CLK_HROW_LH8_3", "VBRK_LH8" ], [ "CLK_HROW_LH9_3", "VBRK_LH9" ], [ "CLK_HROW_LH10_3", "VBRK_LH10" ], [ "CLK_HROW_LH11_3", "VBRK_LH11" ], [ "CLK_HROW_LH12_3", "VBRK_LH12" ], [ "CLK_HROW_MONITOR_N_3", "VBRK_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_3", "VBRK_MONITOR_P" ], [ "CLK_HROW_NE2A0_3", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_3", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_3", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_3", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_3", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_3", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_3", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_3", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_3", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_3", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_3", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_3", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_3", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_3", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_3", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_3", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_3", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_3", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_3", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_3", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_3", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_3", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_3", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_3", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_3", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_3", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_3", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_3", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_3", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_3", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_3", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_3", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_3", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_3", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_3", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_3", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_3", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_3", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_3", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_3", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_3", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_3", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_3", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_3", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_3", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_3", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_3", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_3", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_3", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_3", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_3", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_3", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_3", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_3", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_3", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_3", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_3", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_3", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_3", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_3", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_3", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_3", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_3", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_3", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_3", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_3", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_3", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_3", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_3", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_3", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_3", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_3", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_3", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_3", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_3", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_3", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_3", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_3", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_3", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -2 ], "tile_types": [ "CLK_BUFG_TOP_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_2", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_2", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_2", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_2", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_2", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_2", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_2", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_2", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_2", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_2", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_2", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_2", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_2", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_2", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_2", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_2", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_2", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_2", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_2", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_2", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_2", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_2", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_2", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_2", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_2", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_2", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_2", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_2", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_2", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_2", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_2", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_2", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_2", "VBRK_LH1" ], [ "CLK_HROW_LH2_2", "VBRK_LH2" ], [ "CLK_HROW_LH3_2", "VBRK_LH3" ], [ "CLK_HROW_LH4_2", "VBRK_LH4" ], [ "CLK_HROW_LH5_2", "VBRK_LH5" ], [ "CLK_HROW_LH6_2", "VBRK_LH6" ], [ "CLK_HROW_LH7_2", "VBRK_LH7" ], [ "CLK_HROW_LH8_2", "VBRK_LH8" ], [ "CLK_HROW_LH9_2", "VBRK_LH9" ], [ "CLK_HROW_LH10_2", "VBRK_LH10" ], [ "CLK_HROW_LH11_2", "VBRK_LH11" ], [ "CLK_HROW_LH12_2", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_2", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_2", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_2", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_2", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_2", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_2", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_2", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_2", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_2", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_2", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_2", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_2", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_2", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_2", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_2", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_2", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_2", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_2", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_2", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_2", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_2", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_2", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_2", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_2", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_2", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_2", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_2", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_2", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_2", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_2", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_2", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_2", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_2", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_2", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_2", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_2", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_2", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_2", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_2", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_2", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_2", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_2", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_2", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_2", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_2", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_2", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_2", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_2", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_2", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_2", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_2", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_2", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_2", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_2", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_2", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_2", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_2", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_2", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_2", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_2", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_2", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_2", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_2", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_2", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_2", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_2", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_2", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_2", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_2", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_2", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_2", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_2", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_2", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_2", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_2", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_2", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_2", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_2", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_2", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_2", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -1 ], "tile_types": [ "CLK_BUFG_TOP_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_1", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_1", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_1", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_1", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_1", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_1", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_1", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_1", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_1", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_1", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_1", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_1", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_1", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_1", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_1", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_1", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_1", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_1", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_1", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_1", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_1", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_1", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_1", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_1", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_1", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_1", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_1", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_1", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_1", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_1", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_1", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_1", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_1", "VBRK_LH1" ], [ "CLK_HROW_LH2_1", "VBRK_LH2" ], [ "CLK_HROW_LH3_1", "VBRK_LH3" ], [ "CLK_HROW_LH4_1", "VBRK_LH4" ], [ "CLK_HROW_LH5_1", "VBRK_LH5" ], [ "CLK_HROW_LH6_1", "VBRK_LH6" ], [ "CLK_HROW_LH7_1", "VBRK_LH7" ], [ "CLK_HROW_LH8_1", "VBRK_LH8" ], [ "CLK_HROW_LH9_1", "VBRK_LH9" ], [ "CLK_HROW_LH10_1", "VBRK_LH10" ], [ "CLK_HROW_LH11_1", "VBRK_LH11" ], [ "CLK_HROW_LH12_1", "VBRK_LH12" ], [ "CLK_HROW_MONITOR_N_1", "VBRK_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_1", "VBRK_MONITOR_P" ], [ "CLK_HROW_NE2A0_1", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_1", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_1", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_1", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_1", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_1", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_1", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_1", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_1", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_1", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_1", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_1", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_1", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_1", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_1", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_1", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_1", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_1", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_1", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_1", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_1", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_1", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_1", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_1", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_1", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_1", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_1", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_1", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_1", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_1", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_1", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_1", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_1", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_1", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_1", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_1", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_1", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_1", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_1", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_1", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_1", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_1", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_1", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_1", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_1", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_1", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_1", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_1", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_1", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_1", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_1", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_1", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_1", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_1", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_1", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_1", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_1", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_1", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_1", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_1", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_1", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_1", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_1", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_1", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_1", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_1", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_1", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_1", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_1", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_1", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_1", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_1", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_1", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_1", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_1", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_1", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_1", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_1", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_1", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_1", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLK_BUFG_TOP_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_0", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_0", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_0", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_0", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_0", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_0", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_0", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_0", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_0", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_0", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_0", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_0", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_0", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_0", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_0", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_0", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_0", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_0", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_0", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_0", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_0", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_0", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_0", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_0", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_0", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_0", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_0", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_0", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_0", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_0", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_0", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_0", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_0", "VBRK_LH1" ], [ "CLK_HROW_LH2_0", "VBRK_LH2" ], [ "CLK_HROW_LH3_0", "VBRK_LH3" ], [ "CLK_HROW_LH4_0", "VBRK_LH4" ], [ "CLK_HROW_LH5_0", "VBRK_LH5" ], [ "CLK_HROW_LH6_0", "VBRK_LH6" ], [ "CLK_HROW_LH7_0", "VBRK_LH7" ], [ "CLK_HROW_LH8_0", "VBRK_LH8" ], [ "CLK_HROW_LH9_0", "VBRK_LH9" ], [ "CLK_HROW_LH10_0", "VBRK_LH10" ], [ "CLK_HROW_LH11_0", "VBRK_LH11" ], [ "CLK_HROW_LH12_0", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_0", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_0", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_0", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_0", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_0", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_0", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_0", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_0", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_0", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_0", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_0", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_0", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_0", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_0", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_0", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_0", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_0", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_0", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_0", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_0", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_0", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_0", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_0", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_0", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_0", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_0", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_0", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_0", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_0", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_0", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_0", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_0", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_0", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_0", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_0", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_0", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_0", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_0", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_0", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_0", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_0", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_0", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_0", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_0", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_0", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_0", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_0", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_0", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_0", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_0", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_0", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_0", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_0", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_0", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_0", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_0", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_0", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_0", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_0", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_0", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_0", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_0", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_0", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_0", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_0", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_0", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_0", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_0", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_0", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_0", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_0", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_0", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_0", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_0", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_0", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_0", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_0", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_0", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_0", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_0", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "CLK_FEED", "CLK_FEED" ], "wire_pairs": [ [ "CLK_FEED_R_CK_BUFG_CASC0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ "CLK_FEED_R_CK_BUFG_CASC1", "CLK_FEED_R_CK_BUFG_CASC1" ], [ "CLK_FEED_R_CK_BUFG_CASC2", "CLK_FEED_R_CK_BUFG_CASC2" ], [ "CLK_FEED_R_CK_BUFG_CASC3", "CLK_FEED_R_CK_BUFG_CASC3" ], [ "CLK_FEED_R_CK_BUFG_CASC4", "CLK_FEED_R_CK_BUFG_CASC4" ], [ "CLK_FEED_R_CK_BUFG_CASC5", "CLK_FEED_R_CK_BUFG_CASC5" ], [ "CLK_FEED_R_CK_BUFG_CASC6", "CLK_FEED_R_CK_BUFG_CASC6" ], [ "CLK_FEED_R_CK_BUFG_CASC7", "CLK_FEED_R_CK_BUFG_CASC7" ], [ "CLK_FEED_R_CK_BUFG_CASC8", "CLK_FEED_R_CK_BUFG_CASC8" ], [ "CLK_FEED_R_CK_BUFG_CASC9", "CLK_FEED_R_CK_BUFG_CASC9" ], [ "CLK_FEED_R_CK_BUFG_CASC10", "CLK_FEED_R_CK_BUFG_CASC10" ], [ "CLK_FEED_R_CK_BUFG_CASC11", "CLK_FEED_R_CK_BUFG_CASC11" ], [ "CLK_FEED_R_CK_BUFG_CASC12", "CLK_FEED_R_CK_BUFG_CASC12" ], [ "CLK_FEED_R_CK_BUFG_CASC13", "CLK_FEED_R_CK_BUFG_CASC13" ], [ "CLK_FEED_R_CK_BUFG_CASC14", "CLK_FEED_R_CK_BUFG_CASC14" ], [ "CLK_FEED_R_CK_BUFG_CASC15", "CLK_FEED_R_CK_BUFG_CASC15" ], [ "CLK_FEED_R_CK_BUFG_CASC16", "CLK_FEED_R_CK_BUFG_CASC16" ], [ "CLK_FEED_R_CK_BUFG_CASC17", "CLK_FEED_R_CK_BUFG_CASC17" ], [ "CLK_FEED_R_CK_BUFG_CASC18", "CLK_FEED_R_CK_BUFG_CASC18" ], [ "CLK_FEED_R_CK_BUFG_CASC19", "CLK_FEED_R_CK_BUFG_CASC19" ], [ "CLK_FEED_R_CK_BUFG_CASC20", "CLK_FEED_R_CK_BUFG_CASC20" ], [ "CLK_FEED_R_CK_BUFG_CASC21", "CLK_FEED_R_CK_BUFG_CASC21" ], [ "CLK_FEED_R_CK_BUFG_CASC22", "CLK_FEED_R_CK_BUFG_CASC22" ], [ "CLK_FEED_R_CK_BUFG_CASC23", "CLK_FEED_R_CK_BUFG_CASC23" ], [ "CLK_FEED_R_CK_BUFG_CASC24", "CLK_FEED_R_CK_BUFG_CASC24" ], [ "CLK_FEED_R_CK_BUFG_CASC25", "CLK_FEED_R_CK_BUFG_CASC25" ], [ "CLK_FEED_R_CK_BUFG_CASC26", "CLK_FEED_R_CK_BUFG_CASC26" ], [ "CLK_FEED_R_CK_BUFG_CASC27", "CLK_FEED_R_CK_BUFG_CASC27" ], [ "CLK_FEED_R_CK_BUFG_CASC28", "CLK_FEED_R_CK_BUFG_CASC28" ], [ "CLK_FEED_R_CK_BUFG_CASC29", "CLK_FEED_R_CK_BUFG_CASC29" ], [ "CLK_FEED_R_CK_BUFG_CASC30", "CLK_FEED_R_CK_BUFG_CASC30" ], [ "CLK_FEED_R_CK_BUFG_CASC31", "CLK_FEED_R_CK_BUFG_CASC31" ], [ "CLK_FEED_R_CK_GCLK0", "CLK_FEED_R_CK_GCLK0" ], [ "CLK_FEED_R_CK_GCLK1", "CLK_FEED_R_CK_GCLK1" ], [ "CLK_FEED_R_CK_GCLK2", "CLK_FEED_R_CK_GCLK2" ], [ "CLK_FEED_R_CK_GCLK3", "CLK_FEED_R_CK_GCLK3" ], [ "CLK_FEED_R_CK_GCLK4", "CLK_FEED_R_CK_GCLK4" ], [ "CLK_FEED_R_CK_GCLK5", "CLK_FEED_R_CK_GCLK5" ], [ "CLK_FEED_R_CK_GCLK6", "CLK_FEED_R_CK_GCLK6" ], [ "CLK_FEED_R_CK_GCLK7", "CLK_FEED_R_CK_GCLK7" ], [ "CLK_FEED_R_CK_GCLK8", "CLK_FEED_R_CK_GCLK8" ], [ "CLK_FEED_R_CK_GCLK9", "CLK_FEED_R_CK_GCLK9" ], [ "CLK_FEED_R_CK_GCLK10", "CLK_FEED_R_CK_GCLK10" ], [ "CLK_FEED_R_CK_GCLK11", "CLK_FEED_R_CK_GCLK11" ], [ "CLK_FEED_R_CK_GCLK12", "CLK_FEED_R_CK_GCLK12" ], [ "CLK_FEED_R_CK_GCLK13", "CLK_FEED_R_CK_GCLK13" ], [ "CLK_FEED_R_CK_GCLK14", "CLK_FEED_R_CK_GCLK14" ], [ "CLK_FEED_R_CK_GCLK15", "CLK_FEED_R_CK_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_FEED_R_CK_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_FEED_R_CK_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_FEED_R_CK_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_FEED_R_CK_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_FEED_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_FEED_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_FEED_R_CK_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_FEED_R_CK_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_FEED_R_CK_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_FEED_R_CK_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_FEED_R_CK_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_FEED_R_CK_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_FEED_R_CK_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_FEED_R_CK_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_FEED_R_CK_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_FEED_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, -5 ], "tile_types": [ "CLK_FEED", "CLK_HROW_BOT_R" ], "wire_pairs": [ [ "CLK_FEED_R_CK_BUFG_CASC0", "CLK_HROW_BOT_R_CK_BUFG_CASCIN0" ], [ "CLK_FEED_R_CK_BUFG_CASC1", "CLK_HROW_BOT_R_CK_BUFG_CASCIN1" ], [ "CLK_FEED_R_CK_BUFG_CASC2", "CLK_HROW_BOT_R_CK_BUFG_CASCIN2" ], [ "CLK_FEED_R_CK_BUFG_CASC3", "CLK_HROW_BOT_R_CK_BUFG_CASCIN3" ], [ "CLK_FEED_R_CK_BUFG_CASC4", "CLK_HROW_BOT_R_CK_BUFG_CASCIN4" ], [ "CLK_FEED_R_CK_BUFG_CASC5", "CLK_HROW_BOT_R_CK_BUFG_CASCIN5" ], [ "CLK_FEED_R_CK_BUFG_CASC6", "CLK_HROW_BOT_R_CK_BUFG_CASCIN6" ], [ "CLK_FEED_R_CK_BUFG_CASC7", "CLK_HROW_BOT_R_CK_BUFG_CASCIN7" ], [ "CLK_FEED_R_CK_BUFG_CASC8", "CLK_HROW_BOT_R_CK_BUFG_CASCIN8" ], [ "CLK_FEED_R_CK_BUFG_CASC9", "CLK_HROW_BOT_R_CK_BUFG_CASCIN9" ], [ "CLK_FEED_R_CK_BUFG_CASC10", "CLK_HROW_BOT_R_CK_BUFG_CASCIN10" ], [ "CLK_FEED_R_CK_BUFG_CASC11", "CLK_HROW_BOT_R_CK_BUFG_CASCIN11" ], [ "CLK_FEED_R_CK_BUFG_CASC12", "CLK_HROW_BOT_R_CK_BUFG_CASCIN12" ], [ "CLK_FEED_R_CK_BUFG_CASC13", "CLK_HROW_BOT_R_CK_BUFG_CASCIN13" ], [ "CLK_FEED_R_CK_BUFG_CASC14", "CLK_HROW_BOT_R_CK_BUFG_CASCIN14" ], [ "CLK_FEED_R_CK_BUFG_CASC15", "CLK_HROW_BOT_R_CK_BUFG_CASCIN15" ], [ "CLK_FEED_R_CK_BUFG_CASC16", "CLK_HROW_BOT_R_CK_BUFG_CASCIN16" ], [ "CLK_FEED_R_CK_BUFG_CASC17", "CLK_HROW_BOT_R_CK_BUFG_CASCIN17" ], [ "CLK_FEED_R_CK_BUFG_CASC18", "CLK_HROW_BOT_R_CK_BUFG_CASCIN18" ], [ "CLK_FEED_R_CK_BUFG_CASC19", "CLK_HROW_BOT_R_CK_BUFG_CASCIN19" ], [ "CLK_FEED_R_CK_BUFG_CASC20", "CLK_HROW_BOT_R_CK_BUFG_CASCIN20" ], [ "CLK_FEED_R_CK_BUFG_CASC21", "CLK_HROW_BOT_R_CK_BUFG_CASCIN21" ], [ "CLK_FEED_R_CK_BUFG_CASC22", "CLK_HROW_BOT_R_CK_BUFG_CASCIN22" ], [ "CLK_FEED_R_CK_BUFG_CASC23", "CLK_HROW_BOT_R_CK_BUFG_CASCIN23" ], [ "CLK_FEED_R_CK_BUFG_CASC24", "CLK_HROW_BOT_R_CK_BUFG_CASCIN24" ], [ "CLK_FEED_R_CK_BUFG_CASC25", "CLK_HROW_BOT_R_CK_BUFG_CASCIN25" ], [ "CLK_FEED_R_CK_BUFG_CASC26", "CLK_HROW_BOT_R_CK_BUFG_CASCIN26" ], [ "CLK_FEED_R_CK_BUFG_CASC27", "CLK_HROW_BOT_R_CK_BUFG_CASCIN27" ], [ "CLK_FEED_R_CK_BUFG_CASC28", "CLK_HROW_BOT_R_CK_BUFG_CASCIN28" ], [ "CLK_FEED_R_CK_BUFG_CASC29", "CLK_HROW_BOT_R_CK_BUFG_CASCIN29" ], [ "CLK_FEED_R_CK_BUFG_CASC30", "CLK_HROW_BOT_R_CK_BUFG_CASCIN30" ], [ "CLK_FEED_R_CK_BUFG_CASC31", "CLK_HROW_BOT_R_CK_BUFG_CASCIN31" ], [ "CLK_FEED_R_CK_GCLK0", "CLK_HROW_R_CK_GCLK0" ], [ "CLK_FEED_R_CK_GCLK1", "CLK_HROW_R_CK_GCLK1" ], [ "CLK_FEED_R_CK_GCLK2", "CLK_HROW_R_CK_GCLK2" ], [ "CLK_FEED_R_CK_GCLK3", "CLK_HROW_R_CK_GCLK3" ], [ "CLK_FEED_R_CK_GCLK4", "CLK_HROW_R_CK_GCLK4" ], [ "CLK_FEED_R_CK_GCLK5", "CLK_HROW_R_CK_GCLK5" ], [ "CLK_FEED_R_CK_GCLK6", "CLK_HROW_R_CK_GCLK6" ], [ "CLK_FEED_R_CK_GCLK7", "CLK_HROW_R_CK_GCLK7" ], [ "CLK_FEED_R_CK_GCLK8", "CLK_HROW_R_CK_GCLK8" ], [ "CLK_FEED_R_CK_GCLK9", "CLK_HROW_R_CK_GCLK9" ], [ "CLK_FEED_R_CK_GCLK10", "CLK_HROW_R_CK_GCLK10" ], [ "CLK_FEED_R_CK_GCLK11", "CLK_HROW_R_CK_GCLK11" ], [ "CLK_FEED_R_CK_GCLK12", "CLK_HROW_R_CK_GCLK12" ], [ "CLK_FEED_R_CK_GCLK13", "CLK_HROW_R_CK_GCLK13" ], [ "CLK_FEED_R_CK_GCLK14", "CLK_HROW_R_CK_GCLK14" ], [ "CLK_FEED_R_CK_GCLK15", "CLK_HROW_R_CK_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_HROW_R_CK_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_HROW_R_CK_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_HROW_R_CK_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_HROW_R_CK_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_HROW_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_HROW_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_HROW_R_CK_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_HROW_R_CK_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_HROW_R_CK_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_HROW_R_CK_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_HROW_R_CK_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_HROW_R_CK_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_HROW_R_CK_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_HROW_R_CK_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_HROW_R_CK_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_HROW_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, 5 ], "tile_types": [ "CLK_FEED", "CLK_HROW_BOT_R" ], "wire_pairs": [ [ "CLK_FEED_R_CK_BUFG_CASC0", "CLK_HROW_BOT_R_CK_BUFG_CASCO0" ], [ "CLK_FEED_R_CK_BUFG_CASC1", "CLK_HROW_BOT_R_CK_BUFG_CASCO1" ], [ "CLK_FEED_R_CK_BUFG_CASC2", "CLK_HROW_BOT_R_CK_BUFG_CASCO2" ], [ "CLK_FEED_R_CK_BUFG_CASC3", "CLK_HROW_BOT_R_CK_BUFG_CASCO3" ], [ "CLK_FEED_R_CK_BUFG_CASC4", "CLK_HROW_BOT_R_CK_BUFG_CASCO4" ], [ "CLK_FEED_R_CK_BUFG_CASC5", "CLK_HROW_BOT_R_CK_BUFG_CASCO5" ], [ "CLK_FEED_R_CK_BUFG_CASC6", "CLK_HROW_BOT_R_CK_BUFG_CASCO6" ], [ "CLK_FEED_R_CK_BUFG_CASC7", "CLK_HROW_BOT_R_CK_BUFG_CASCO7" ], [ "CLK_FEED_R_CK_BUFG_CASC8", "CLK_HROW_BOT_R_CK_BUFG_CASCO8" ], [ "CLK_FEED_R_CK_BUFG_CASC9", "CLK_HROW_BOT_R_CK_BUFG_CASCO9" ], [ "CLK_FEED_R_CK_BUFG_CASC10", "CLK_HROW_BOT_R_CK_BUFG_CASCO10" ], [ "CLK_FEED_R_CK_BUFG_CASC11", "CLK_HROW_BOT_R_CK_BUFG_CASCO11" ], [ "CLK_FEED_R_CK_BUFG_CASC12", "CLK_HROW_BOT_R_CK_BUFG_CASCO12" ], [ "CLK_FEED_R_CK_BUFG_CASC13", "CLK_HROW_BOT_R_CK_BUFG_CASCO13" ], [ "CLK_FEED_R_CK_BUFG_CASC14", "CLK_HROW_BOT_R_CK_BUFG_CASCO14" ], [ "CLK_FEED_R_CK_BUFG_CASC15", "CLK_HROW_BOT_R_CK_BUFG_CASCO15" ], [ "CLK_FEED_R_CK_BUFG_CASC16", "CLK_HROW_BOT_R_CK_BUFG_CASCO16" ], [ "CLK_FEED_R_CK_BUFG_CASC17", "CLK_HROW_BOT_R_CK_BUFG_CASCO17" ], [ "CLK_FEED_R_CK_BUFG_CASC18", "CLK_HROW_BOT_R_CK_BUFG_CASCO18" ], [ "CLK_FEED_R_CK_BUFG_CASC19", "CLK_HROW_BOT_R_CK_BUFG_CASCO19" ], [ "CLK_FEED_R_CK_BUFG_CASC20", "CLK_HROW_BOT_R_CK_BUFG_CASCO20" ], [ "CLK_FEED_R_CK_BUFG_CASC21", "CLK_HROW_BOT_R_CK_BUFG_CASCO21" ], [ "CLK_FEED_R_CK_BUFG_CASC22", "CLK_HROW_BOT_R_CK_BUFG_CASCO22" ], [ "CLK_FEED_R_CK_BUFG_CASC23", "CLK_HROW_BOT_R_CK_BUFG_CASCO23" ], [ "CLK_FEED_R_CK_BUFG_CASC24", "CLK_HROW_BOT_R_CK_BUFG_CASCO24" ], [ "CLK_FEED_R_CK_BUFG_CASC25", "CLK_HROW_BOT_R_CK_BUFG_CASCO25" ], [ "CLK_FEED_R_CK_BUFG_CASC26", "CLK_HROW_BOT_R_CK_BUFG_CASCO26" ], [ "CLK_FEED_R_CK_BUFG_CASC27", "CLK_HROW_BOT_R_CK_BUFG_CASCO27" ], [ "CLK_FEED_R_CK_BUFG_CASC28", "CLK_HROW_BOT_R_CK_BUFG_CASCO28" ], [ "CLK_FEED_R_CK_BUFG_CASC29", "CLK_HROW_BOT_R_CK_BUFG_CASCO29" ], [ "CLK_FEED_R_CK_BUFG_CASC30", "CLK_HROW_BOT_R_CK_BUFG_CASCO30" ], [ "CLK_FEED_R_CK_BUFG_CASC31", "CLK_HROW_BOT_R_CK_BUFG_CASCO31" ], [ "CLK_FEED_R_CK_GCLK0", "CLK_HROW_R_CK_GCLK0" ], [ "CLK_FEED_R_CK_GCLK1", "CLK_HROW_R_CK_GCLK1" ], [ "CLK_FEED_R_CK_GCLK2", "CLK_HROW_R_CK_GCLK2" ], [ "CLK_FEED_R_CK_GCLK3", "CLK_HROW_R_CK_GCLK3" ], [ "CLK_FEED_R_CK_GCLK4", "CLK_HROW_R_CK_GCLK4" ], [ "CLK_FEED_R_CK_GCLK5", "CLK_HROW_R_CK_GCLK5" ], [ "CLK_FEED_R_CK_GCLK6", "CLK_HROW_R_CK_GCLK6" ], [ "CLK_FEED_R_CK_GCLK7", "CLK_HROW_R_CK_GCLK7" ], [ "CLK_FEED_R_CK_GCLK8", "CLK_HROW_R_CK_GCLK8" ], [ "CLK_FEED_R_CK_GCLK9", "CLK_HROW_R_CK_GCLK9" ], [ "CLK_FEED_R_CK_GCLK10", "CLK_HROW_R_CK_GCLK10" ], [ "CLK_FEED_R_CK_GCLK11", "CLK_HROW_R_CK_GCLK11" ], [ "CLK_FEED_R_CK_GCLK12", "CLK_HROW_R_CK_GCLK12" ], [ "CLK_FEED_R_CK_GCLK13", "CLK_HROW_R_CK_GCLK13" ], [ "CLK_FEED_R_CK_GCLK14", "CLK_HROW_R_CK_GCLK14" ], [ "CLK_FEED_R_CK_GCLK15", "CLK_HROW_R_CK_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_HROW_R_CK_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_HROW_R_CK_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_HROW_R_CK_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_HROW_R_CK_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_HROW_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_HROW_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_HROW_R_CK_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_HROW_R_CK_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_HROW_R_CK_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_HROW_R_CK_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_HROW_R_CK_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_HROW_R_CK_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_HROW_R_CK_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_HROW_R_CK_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_HROW_R_CK_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_HROW_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, -5 ], "tile_types": [ "CLK_FEED", "CLK_HROW_TOP_R" ], "wire_pairs": [ [ "CLK_FEED_R_CK_BUFG_CASC0", "CLK_HROW_TOP_R_CK_BUFG_CASCO0" ], [ "CLK_FEED_R_CK_BUFG_CASC1", "CLK_HROW_TOP_R_CK_BUFG_CASCO1" ], [ "CLK_FEED_R_CK_BUFG_CASC2", "CLK_HROW_TOP_R_CK_BUFG_CASCO2" ], [ "CLK_FEED_R_CK_BUFG_CASC3", "CLK_HROW_TOP_R_CK_BUFG_CASCO3" ], [ "CLK_FEED_R_CK_BUFG_CASC4", "CLK_HROW_TOP_R_CK_BUFG_CASCO4" ], [ "CLK_FEED_R_CK_BUFG_CASC5", "CLK_HROW_TOP_R_CK_BUFG_CASCO5" ], [ "CLK_FEED_R_CK_BUFG_CASC6", "CLK_HROW_TOP_R_CK_BUFG_CASCO6" ], [ "CLK_FEED_R_CK_BUFG_CASC7", "CLK_HROW_TOP_R_CK_BUFG_CASCO7" ], [ "CLK_FEED_R_CK_BUFG_CASC8", "CLK_HROW_TOP_R_CK_BUFG_CASCO8" ], [ "CLK_FEED_R_CK_BUFG_CASC9", "CLK_HROW_TOP_R_CK_BUFG_CASCO9" ], [ "CLK_FEED_R_CK_BUFG_CASC10", "CLK_HROW_TOP_R_CK_BUFG_CASCO10" ], [ "CLK_FEED_R_CK_BUFG_CASC11", "CLK_HROW_TOP_R_CK_BUFG_CASCO11" ], [ "CLK_FEED_R_CK_BUFG_CASC12", "CLK_HROW_TOP_R_CK_BUFG_CASCO12" ], [ "CLK_FEED_R_CK_BUFG_CASC13", "CLK_HROW_TOP_R_CK_BUFG_CASCO13" ], [ "CLK_FEED_R_CK_BUFG_CASC14", "CLK_HROW_TOP_R_CK_BUFG_CASCO14" ], [ "CLK_FEED_R_CK_BUFG_CASC15", "CLK_HROW_TOP_R_CK_BUFG_CASCO15" ], [ "CLK_FEED_R_CK_BUFG_CASC16", "CLK_HROW_TOP_R_CK_BUFG_CASCO16" ], [ "CLK_FEED_R_CK_BUFG_CASC17", "CLK_HROW_TOP_R_CK_BUFG_CASCO17" ], [ "CLK_FEED_R_CK_BUFG_CASC18", "CLK_HROW_TOP_R_CK_BUFG_CASCO18" ], [ "CLK_FEED_R_CK_BUFG_CASC19", "CLK_HROW_TOP_R_CK_BUFG_CASCO19" ], [ "CLK_FEED_R_CK_BUFG_CASC20", "CLK_HROW_TOP_R_CK_BUFG_CASCO20" ], [ "CLK_FEED_R_CK_BUFG_CASC21", "CLK_HROW_TOP_R_CK_BUFG_CASCO21" ], [ "CLK_FEED_R_CK_BUFG_CASC22", "CLK_HROW_TOP_R_CK_BUFG_CASCO22" ], [ "CLK_FEED_R_CK_BUFG_CASC23", "CLK_HROW_TOP_R_CK_BUFG_CASCO23" ], [ "CLK_FEED_R_CK_BUFG_CASC24", "CLK_HROW_TOP_R_CK_BUFG_CASCO24" ], [ "CLK_FEED_R_CK_BUFG_CASC25", "CLK_HROW_TOP_R_CK_BUFG_CASCO25" ], [ "CLK_FEED_R_CK_BUFG_CASC26", "CLK_HROW_TOP_R_CK_BUFG_CASCO26" ], [ "CLK_FEED_R_CK_BUFG_CASC27", "CLK_HROW_TOP_R_CK_BUFG_CASCO27" ], [ "CLK_FEED_R_CK_BUFG_CASC28", "CLK_HROW_TOP_R_CK_BUFG_CASCO28" ], [ "CLK_FEED_R_CK_BUFG_CASC29", "CLK_HROW_TOP_R_CK_BUFG_CASCO29" ], [ "CLK_FEED_R_CK_BUFG_CASC30", "CLK_HROW_TOP_R_CK_BUFG_CASCO30" ], [ "CLK_FEED_R_CK_BUFG_CASC31", "CLK_HROW_TOP_R_CK_BUFG_CASCO31" ], [ "CLK_FEED_R_CK_GCLK0", "CLK_HROW_R_CK_GCLK0" ], [ "CLK_FEED_R_CK_GCLK1", "CLK_HROW_R_CK_GCLK1" ], [ "CLK_FEED_R_CK_GCLK2", "CLK_HROW_R_CK_GCLK2" ], [ "CLK_FEED_R_CK_GCLK3", "CLK_HROW_R_CK_GCLK3" ], [ "CLK_FEED_R_CK_GCLK4", "CLK_HROW_R_CK_GCLK4" ], [ "CLK_FEED_R_CK_GCLK5", "CLK_HROW_R_CK_GCLK5" ], [ "CLK_FEED_R_CK_GCLK6", "CLK_HROW_R_CK_GCLK6" ], [ "CLK_FEED_R_CK_GCLK7", "CLK_HROW_R_CK_GCLK7" ], [ "CLK_FEED_R_CK_GCLK8", "CLK_HROW_R_CK_GCLK8" ], [ "CLK_FEED_R_CK_GCLK9", "CLK_HROW_R_CK_GCLK9" ], [ "CLK_FEED_R_CK_GCLK10", "CLK_HROW_R_CK_GCLK10" ], [ "CLK_FEED_R_CK_GCLK11", "CLK_HROW_R_CK_GCLK11" ], [ "CLK_FEED_R_CK_GCLK12", "CLK_HROW_R_CK_GCLK12" ], [ "CLK_FEED_R_CK_GCLK13", "CLK_HROW_R_CK_GCLK13" ], [ "CLK_FEED_R_CK_GCLK14", "CLK_HROW_R_CK_GCLK14" ], [ "CLK_FEED_R_CK_GCLK15", "CLK_HROW_R_CK_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_HROW_R_CK_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_HROW_R_CK_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_HROW_R_CK_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_HROW_R_CK_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_HROW_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_HROW_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_HROW_R_CK_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_HROW_R_CK_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_HROW_R_CK_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_HROW_R_CK_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_HROW_R_CK_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_HROW_R_CK_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_HROW_R_CK_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_HROW_R_CK_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_HROW_R_CK_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_HROW_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, 5 ], "tile_types": [ "CLK_FEED", "CLK_HROW_TOP_R" ], "wire_pairs": [ [ "CLK_FEED_R_CK_BUFG_CASC0", "CLK_HROW_TOP_R_CK_BUFG_CASCIN0" ], [ "CLK_FEED_R_CK_BUFG_CASC1", "CLK_HROW_TOP_R_CK_BUFG_CASCIN1" ], [ "CLK_FEED_R_CK_BUFG_CASC2", "CLK_HROW_TOP_R_CK_BUFG_CASCIN2" ], [ "CLK_FEED_R_CK_BUFG_CASC3", "CLK_HROW_TOP_R_CK_BUFG_CASCIN3" ], [ "CLK_FEED_R_CK_BUFG_CASC4", "CLK_HROW_TOP_R_CK_BUFG_CASCIN4" ], [ "CLK_FEED_R_CK_BUFG_CASC5", "CLK_HROW_TOP_R_CK_BUFG_CASCIN5" ], [ "CLK_FEED_R_CK_BUFG_CASC6", "CLK_HROW_TOP_R_CK_BUFG_CASCIN6" ], [ "CLK_FEED_R_CK_BUFG_CASC7", "CLK_HROW_TOP_R_CK_BUFG_CASCIN7" ], [ "CLK_FEED_R_CK_BUFG_CASC8", "CLK_HROW_TOP_R_CK_BUFG_CASCIN8" ], [ "CLK_FEED_R_CK_BUFG_CASC9", "CLK_HROW_TOP_R_CK_BUFG_CASCIN9" ], [ "CLK_FEED_R_CK_BUFG_CASC10", "CLK_HROW_TOP_R_CK_BUFG_CASCIN10" ], [ "CLK_FEED_R_CK_BUFG_CASC11", "CLK_HROW_TOP_R_CK_BUFG_CASCIN11" ], [ "CLK_FEED_R_CK_BUFG_CASC12", "CLK_HROW_TOP_R_CK_BUFG_CASCIN12" ], [ "CLK_FEED_R_CK_BUFG_CASC13", "CLK_HROW_TOP_R_CK_BUFG_CASCIN13" ], [ "CLK_FEED_R_CK_BUFG_CASC14", "CLK_HROW_TOP_R_CK_BUFG_CASCIN14" ], [ "CLK_FEED_R_CK_BUFG_CASC15", "CLK_HROW_TOP_R_CK_BUFG_CASCIN15" ], [ "CLK_FEED_R_CK_BUFG_CASC16", "CLK_HROW_TOP_R_CK_BUFG_CASCIN16" ], [ "CLK_FEED_R_CK_BUFG_CASC17", "CLK_HROW_TOP_R_CK_BUFG_CASCIN17" ], [ "CLK_FEED_R_CK_BUFG_CASC18", "CLK_HROW_TOP_R_CK_BUFG_CASCIN18" ], [ "CLK_FEED_R_CK_BUFG_CASC19", "CLK_HROW_TOP_R_CK_BUFG_CASCIN19" ], [ "CLK_FEED_R_CK_BUFG_CASC20", "CLK_HROW_TOP_R_CK_BUFG_CASCIN20" ], [ "CLK_FEED_R_CK_BUFG_CASC21", "CLK_HROW_TOP_R_CK_BUFG_CASCIN21" ], [ "CLK_FEED_R_CK_BUFG_CASC22", "CLK_HROW_TOP_R_CK_BUFG_CASCIN22" ], [ "CLK_FEED_R_CK_BUFG_CASC23", "CLK_HROW_TOP_R_CK_BUFG_CASCIN23" ], [ "CLK_FEED_R_CK_BUFG_CASC24", "CLK_HROW_TOP_R_CK_BUFG_CASCIN24" ], [ "CLK_FEED_R_CK_BUFG_CASC25", "CLK_HROW_TOP_R_CK_BUFG_CASCIN25" ], [ "CLK_FEED_R_CK_BUFG_CASC26", "CLK_HROW_TOP_R_CK_BUFG_CASCIN26" ], [ "CLK_FEED_R_CK_BUFG_CASC27", "CLK_HROW_TOP_R_CK_BUFG_CASCIN27" ], [ "CLK_FEED_R_CK_BUFG_CASC28", "CLK_HROW_TOP_R_CK_BUFG_CASCIN28" ], [ "CLK_FEED_R_CK_BUFG_CASC29", "CLK_HROW_TOP_R_CK_BUFG_CASCIN29" ], [ "CLK_FEED_R_CK_BUFG_CASC30", "CLK_HROW_TOP_R_CK_BUFG_CASCIN30" ], [ "CLK_FEED_R_CK_BUFG_CASC31", "CLK_HROW_TOP_R_CK_BUFG_CASCIN31" ], [ "CLK_FEED_R_CK_GCLK0", "CLK_HROW_R_CK_GCLK0" ], [ "CLK_FEED_R_CK_GCLK1", "CLK_HROW_R_CK_GCLK1" ], [ "CLK_FEED_R_CK_GCLK2", "CLK_HROW_R_CK_GCLK2" ], [ "CLK_FEED_R_CK_GCLK3", "CLK_HROW_R_CK_GCLK3" ], [ "CLK_FEED_R_CK_GCLK4", "CLK_HROW_R_CK_GCLK4" ], [ "CLK_FEED_R_CK_GCLK5", "CLK_HROW_R_CK_GCLK5" ], [ "CLK_FEED_R_CK_GCLK6", "CLK_HROW_R_CK_GCLK6" ], [ "CLK_FEED_R_CK_GCLK7", "CLK_HROW_R_CK_GCLK7" ], [ "CLK_FEED_R_CK_GCLK8", "CLK_HROW_R_CK_GCLK8" ], [ "CLK_FEED_R_CK_GCLK9", "CLK_HROW_R_CK_GCLK9" ], [ "CLK_FEED_R_CK_GCLK10", "CLK_HROW_R_CK_GCLK10" ], [ "CLK_FEED_R_CK_GCLK11", "CLK_HROW_R_CK_GCLK11" ], [ "CLK_FEED_R_CK_GCLK12", "CLK_HROW_R_CK_GCLK12" ], [ "CLK_FEED_R_CK_GCLK13", "CLK_HROW_R_CK_GCLK13" ], [ "CLK_FEED_R_CK_GCLK14", "CLK_HROW_R_CK_GCLK14" ], [ "CLK_FEED_R_CK_GCLK15", "CLK_HROW_R_CK_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_HROW_R_CK_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_HROW_R_CK_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_HROW_R_CK_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_HROW_R_CK_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_HROW_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_HROW_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_HROW_R_CK_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_HROW_R_CK_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_HROW_R_CK_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_HROW_R_CK_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_HROW_R_CK_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_HROW_R_CK_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_HROW_R_CK_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_HROW_R_CK_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_HROW_R_CK_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_HROW_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "CLK_FEED", "CLK_MTBF2" ], "wire_pairs": [ [ "CLK_FEED_R_CK_BUFG_CASC0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ "CLK_FEED_R_CK_BUFG_CASC1", "CLK_FEED_R_CK_BUFG_CASC1" ], [ "CLK_FEED_R_CK_BUFG_CASC2", "CLK_FEED_R_CK_BUFG_CASC2" ], [ "CLK_FEED_R_CK_BUFG_CASC3", "CLK_FEED_R_CK_BUFG_CASC3" ], [ "CLK_FEED_R_CK_BUFG_CASC4", "CLK_FEED_R_CK_BUFG_CASC4" ], [ "CLK_FEED_R_CK_BUFG_CASC5", "CLK_FEED_R_CK_BUFG_CASC5" ], [ "CLK_FEED_R_CK_BUFG_CASC6", "CLK_FEED_R_CK_BUFG_CASC6" ], [ "CLK_FEED_R_CK_BUFG_CASC7", "CLK_FEED_R_CK_BUFG_CASC7" ], [ "CLK_FEED_R_CK_BUFG_CASC8", "CLK_FEED_R_CK_BUFG_CASC8" ], [ "CLK_FEED_R_CK_BUFG_CASC9", "CLK_FEED_R_CK_BUFG_CASC9" ], [ "CLK_FEED_R_CK_BUFG_CASC10", "CLK_FEED_R_CK_BUFG_CASC10" ], [ "CLK_FEED_R_CK_BUFG_CASC11", "CLK_FEED_R_CK_BUFG_CASC11" ], [ "CLK_FEED_R_CK_BUFG_CASC12", "CLK_FEED_R_CK_BUFG_CASC12" ], [ "CLK_FEED_R_CK_BUFG_CASC13", "CLK_FEED_R_CK_BUFG_CASC13" ], [ "CLK_FEED_R_CK_BUFG_CASC14", "CLK_FEED_R_CK_BUFG_CASC14" ], [ "CLK_FEED_R_CK_BUFG_CASC15", "CLK_FEED_R_CK_BUFG_CASC15" ], [ "CLK_FEED_R_CK_BUFG_CASC16", "CLK_FEED_R_CK_BUFG_CASC16" ], [ "CLK_FEED_R_CK_BUFG_CASC17", "CLK_FEED_R_CK_BUFG_CASC17" ], [ "CLK_FEED_R_CK_BUFG_CASC18", "CLK_FEED_R_CK_BUFG_CASC18" ], [ "CLK_FEED_R_CK_BUFG_CASC19", "CLK_FEED_R_CK_BUFG_CASC19" ], [ "CLK_FEED_R_CK_BUFG_CASC20", "CLK_FEED_R_CK_BUFG_CASC20" ], [ "CLK_FEED_R_CK_BUFG_CASC21", "CLK_FEED_R_CK_BUFG_CASC21" ], [ "CLK_FEED_R_CK_BUFG_CASC22", "CLK_FEED_R_CK_BUFG_CASC22" ], [ "CLK_FEED_R_CK_BUFG_CASC23", "CLK_FEED_R_CK_BUFG_CASC23" ], [ "CLK_FEED_R_CK_BUFG_CASC24", "CLK_FEED_R_CK_BUFG_CASC24" ], [ "CLK_FEED_R_CK_BUFG_CASC25", "CLK_FEED_R_CK_BUFG_CASC25" ], [ "CLK_FEED_R_CK_BUFG_CASC26", "CLK_FEED_R_CK_BUFG_CASC26" ], [ "CLK_FEED_R_CK_BUFG_CASC27", "CLK_FEED_R_CK_BUFG_CASC27" ], [ "CLK_FEED_R_CK_BUFG_CASC28", "CLK_FEED_R_CK_BUFG_CASC28" ], [ "CLK_FEED_R_CK_BUFG_CASC29", "CLK_FEED_R_CK_BUFG_CASC29" ], [ "CLK_FEED_R_CK_BUFG_CASC30", "CLK_FEED_R_CK_BUFG_CASC30" ], [ "CLK_FEED_R_CK_BUFG_CASC31", "CLK_FEED_R_CK_BUFG_CASC31" ], [ "CLK_FEED_R_CK_GCLK0", "CLK_FEED_R_CK_GCLK0" ], [ "CLK_FEED_R_CK_GCLK1", "CLK_FEED_R_CK_GCLK1" ], [ "CLK_FEED_R_CK_GCLK2", "CLK_FEED_R_CK_GCLK2" ], [ "CLK_FEED_R_CK_GCLK3", "CLK_FEED_R_CK_GCLK3" ], [ "CLK_FEED_R_CK_GCLK4", "CLK_FEED_R_CK_GCLK4" ], [ "CLK_FEED_R_CK_GCLK5", "CLK_FEED_R_CK_GCLK5" ], [ "CLK_FEED_R_CK_GCLK6", "CLK_FEED_R_CK_GCLK6" ], [ "CLK_FEED_R_CK_GCLK7", "CLK_FEED_R_CK_GCLK7" ], [ "CLK_FEED_R_CK_GCLK8", "CLK_FEED_R_CK_GCLK8" ], [ "CLK_FEED_R_CK_GCLK9", "CLK_FEED_R_CK_GCLK9" ], [ "CLK_FEED_R_CK_GCLK10", "CLK_FEED_R_CK_GCLK10" ], [ "CLK_FEED_R_CK_GCLK11", "CLK_FEED_R_CK_GCLK11" ], [ "CLK_FEED_R_CK_GCLK12", "CLK_FEED_R_CK_GCLK12" ], [ "CLK_FEED_R_CK_GCLK13", "CLK_FEED_R_CK_GCLK13" ], [ "CLK_FEED_R_CK_GCLK14", "CLK_FEED_R_CK_GCLK14" ], [ "CLK_FEED_R_CK_GCLK15", "CLK_FEED_R_CK_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_FEED_R_CK_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_FEED_R_CK_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_FEED_R_CK_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_FEED_R_CK_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_FEED_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_FEED_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", 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"CLK_PMV_R_CK_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_PMV_R_CK_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_PMV_R_CK_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_PMV_R_CK_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_PMV_R_CK_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_PMV_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_PMV_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_PMV_R_CK_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_PMV_R_CK_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_PMV_R_CK_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_PMV_R_CK_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_PMV_R_CK_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_PMV_R_CK_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_PMV_R_CK_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_PMV_R_CK_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_PMV_R_CK_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_PMV_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "CLK_FEED", "CLK_PMV2" ], "wire_pairs": [ [ "CLK_FEED_R_CK_BUFG_CASC0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ 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"CLK_FEED_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_FEED_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_FEED_R_CK_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_FEED_R_CK_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_FEED_R_CK_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_FEED_R_CK_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_FEED_R_CK_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_FEED_R_CK_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_FEED_R_CK_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_FEED_R_CK_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_FEED_R_CK_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_FEED_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "CLK_FEED", "CLK_PMV2" ], "wire_pairs": [ [ "CLK_FEED_R_CK_BUFG_CASC0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ "CLK_FEED_R_CK_BUFG_CASC1", "CLK_FEED_R_CK_BUFG_CASC1" ], [ "CLK_FEED_R_CK_BUFG_CASC2", "CLK_FEED_R_CK_BUFG_CASC2" ], [ "CLK_FEED_R_CK_BUFG_CASC3", "CLK_FEED_R_CK_BUFG_CASC3" ], [ "CLK_FEED_R_CK_BUFG_CASC4", "CLK_FEED_R_CK_BUFG_CASC4" ], [ "CLK_FEED_R_CK_BUFG_CASC5", "CLK_FEED_R_CK_BUFG_CASC5" ], [ "CLK_FEED_R_CK_BUFG_CASC6", "CLK_FEED_R_CK_BUFG_CASC6" ], [ "CLK_FEED_R_CK_BUFG_CASC7", "CLK_FEED_R_CK_BUFG_CASC7" ], [ "CLK_FEED_R_CK_BUFG_CASC8", "CLK_FEED_R_CK_BUFG_CASC8" ], [ "CLK_FEED_R_CK_BUFG_CASC9", "CLK_FEED_R_CK_BUFG_CASC9" ], [ "CLK_FEED_R_CK_BUFG_CASC10", "CLK_FEED_R_CK_BUFG_CASC10" ], [ "CLK_FEED_R_CK_BUFG_CASC11", "CLK_FEED_R_CK_BUFG_CASC11" ], [ "CLK_FEED_R_CK_BUFG_CASC12", "CLK_FEED_R_CK_BUFG_CASC12" ], [ "CLK_FEED_R_CK_BUFG_CASC13", "CLK_FEED_R_CK_BUFG_CASC13" ], [ "CLK_FEED_R_CK_BUFG_CASC14", "CLK_FEED_R_CK_BUFG_CASC14" ], [ "CLK_FEED_R_CK_BUFG_CASC15", "CLK_FEED_R_CK_BUFG_CASC15" ], [ "CLK_FEED_R_CK_BUFG_CASC16", "CLK_FEED_R_CK_BUFG_CASC16" ], [ "CLK_FEED_R_CK_BUFG_CASC17", "CLK_FEED_R_CK_BUFG_CASC17" ], [ "CLK_FEED_R_CK_BUFG_CASC18", "CLK_FEED_R_CK_BUFG_CASC18" ], [ "CLK_FEED_R_CK_BUFG_CASC19", "CLK_FEED_R_CK_BUFG_CASC19" ], [ "CLK_FEED_R_CK_BUFG_CASC20", "CLK_FEED_R_CK_BUFG_CASC20" ], [ "CLK_FEED_R_CK_BUFG_CASC21", "CLK_FEED_R_CK_BUFG_CASC21" ], [ "CLK_FEED_R_CK_BUFG_CASC22", "CLK_FEED_R_CK_BUFG_CASC22" ], [ "CLK_FEED_R_CK_BUFG_CASC23", "CLK_FEED_R_CK_BUFG_CASC23" ], [ "CLK_FEED_R_CK_BUFG_CASC24", "CLK_FEED_R_CK_BUFG_CASC24" ], [ "CLK_FEED_R_CK_BUFG_CASC25", "CLK_FEED_R_CK_BUFG_CASC25" ], [ "CLK_FEED_R_CK_BUFG_CASC26", "CLK_FEED_R_CK_BUFG_CASC26" ], [ "CLK_FEED_R_CK_BUFG_CASC27", "CLK_FEED_R_CK_BUFG_CASC27" ], [ "CLK_FEED_R_CK_BUFG_CASC28", "CLK_FEED_R_CK_BUFG_CASC28" ], [ "CLK_FEED_R_CK_BUFG_CASC29", "CLK_FEED_R_CK_BUFG_CASC29" ], [ "CLK_FEED_R_CK_BUFG_CASC30", "CLK_FEED_R_CK_BUFG_CASC30" ], [ "CLK_FEED_R_CK_BUFG_CASC31", "CLK_FEED_R_CK_BUFG_CASC31" ], [ "CLK_FEED_R_CK_GCLK0", "CLK_FEED_R_CK_GCLK0" ], [ "CLK_FEED_R_CK_GCLK1", "CLK_FEED_R_CK_GCLK1" ], [ "CLK_FEED_R_CK_GCLK2", "CLK_FEED_R_CK_GCLK2" ], [ "CLK_FEED_R_CK_GCLK3", "CLK_FEED_R_CK_GCLK3" ], [ "CLK_FEED_R_CK_GCLK4", "CLK_FEED_R_CK_GCLK4" ], [ "CLK_FEED_R_CK_GCLK5", "CLK_FEED_R_CK_GCLK5" ], [ "CLK_FEED_R_CK_GCLK6", "CLK_FEED_R_CK_GCLK6" ], [ "CLK_FEED_R_CK_GCLK7", "CLK_FEED_R_CK_GCLK7" ], [ "CLK_FEED_R_CK_GCLK8", "CLK_FEED_R_CK_GCLK8" ], [ "CLK_FEED_R_CK_GCLK9", "CLK_FEED_R_CK_GCLK9" ], [ "CLK_FEED_R_CK_GCLK10", "CLK_FEED_R_CK_GCLK10" ], [ "CLK_FEED_R_CK_GCLK11", "CLK_FEED_R_CK_GCLK11" ], [ "CLK_FEED_R_CK_GCLK12", "CLK_FEED_R_CK_GCLK12" ], [ "CLK_FEED_R_CK_GCLK13", "CLK_FEED_R_CK_GCLK13" ], [ "CLK_FEED_R_CK_GCLK14", "CLK_FEED_R_CK_GCLK14" ], [ "CLK_FEED_R_CK_GCLK15", "CLK_FEED_R_CK_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_FEED_R_CK_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_FEED_R_CK_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_FEED_R_CK_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_FEED_R_CK_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_FEED_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_FEED_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_FEED_R_CK_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_FEED_R_CK_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_FEED_R_CK_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_FEED_R_CK_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_FEED_R_CK_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_FEED_R_CK_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_FEED_R_CK_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_FEED_R_CK_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_FEED_R_CK_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_FEED_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "CLK_FEED", "CLK_PMV2_SVT" ], "wire_pairs": [ [ "CLK_FEED_R_CK_BUFG_CASC0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ "CLK_FEED_R_CK_BUFG_CASC1", "CLK_FEED_R_CK_BUFG_CASC1" ], [ "CLK_FEED_R_CK_BUFG_CASC2", "CLK_FEED_R_CK_BUFG_CASC2" ], [ "CLK_FEED_R_CK_BUFG_CASC3", "CLK_FEED_R_CK_BUFG_CASC3" ], [ "CLK_FEED_R_CK_BUFG_CASC4", "CLK_FEED_R_CK_BUFG_CASC4" ], [ "CLK_FEED_R_CK_BUFG_CASC5", "CLK_FEED_R_CK_BUFG_CASC5" ], [ "CLK_FEED_R_CK_BUFG_CASC6", "CLK_FEED_R_CK_BUFG_CASC6" ], [ "CLK_FEED_R_CK_BUFG_CASC7", "CLK_FEED_R_CK_BUFG_CASC7" ], [ "CLK_FEED_R_CK_BUFG_CASC8", "CLK_FEED_R_CK_BUFG_CASC8" ], [ "CLK_FEED_R_CK_BUFG_CASC9", "CLK_FEED_R_CK_BUFG_CASC9" ], [ "CLK_FEED_R_CK_BUFG_CASC10", "CLK_FEED_R_CK_BUFG_CASC10" ], [ "CLK_FEED_R_CK_BUFG_CASC11", "CLK_FEED_R_CK_BUFG_CASC11" ], [ "CLK_FEED_R_CK_BUFG_CASC12", "CLK_FEED_R_CK_BUFG_CASC12" ], [ "CLK_FEED_R_CK_BUFG_CASC13", "CLK_FEED_R_CK_BUFG_CASC13" ], [ "CLK_FEED_R_CK_BUFG_CASC14", "CLK_FEED_R_CK_BUFG_CASC14" ], [ "CLK_FEED_R_CK_BUFG_CASC15", "CLK_FEED_R_CK_BUFG_CASC15" ], [ "CLK_FEED_R_CK_BUFG_CASC16", "CLK_FEED_R_CK_BUFG_CASC16" ], [ "CLK_FEED_R_CK_BUFG_CASC17", "CLK_FEED_R_CK_BUFG_CASC17" ], [ "CLK_FEED_R_CK_BUFG_CASC18", "CLK_FEED_R_CK_BUFG_CASC18" ], [ "CLK_FEED_R_CK_BUFG_CASC19", "CLK_FEED_R_CK_BUFG_CASC19" ], [ "CLK_FEED_R_CK_BUFG_CASC20", "CLK_FEED_R_CK_BUFG_CASC20" ], [ "CLK_FEED_R_CK_BUFG_CASC21", "CLK_FEED_R_CK_BUFG_CASC21" ], [ "CLK_FEED_R_CK_BUFG_CASC22", "CLK_FEED_R_CK_BUFG_CASC22" ], [ "CLK_FEED_R_CK_BUFG_CASC23", "CLK_FEED_R_CK_BUFG_CASC23" ], [ "CLK_FEED_R_CK_BUFG_CASC24", "CLK_FEED_R_CK_BUFG_CASC24" ], [ "CLK_FEED_R_CK_BUFG_CASC25", "CLK_FEED_R_CK_BUFG_CASC25" ], [ "CLK_FEED_R_CK_BUFG_CASC26", "CLK_FEED_R_CK_BUFG_CASC26" ], [ "CLK_FEED_R_CK_BUFG_CASC27", "CLK_FEED_R_CK_BUFG_CASC27" ], [ "CLK_FEED_R_CK_BUFG_CASC28", "CLK_FEED_R_CK_BUFG_CASC28" ], [ "CLK_FEED_R_CK_BUFG_CASC29", "CLK_FEED_R_CK_BUFG_CASC29" ], [ "CLK_FEED_R_CK_BUFG_CASC30", "CLK_FEED_R_CK_BUFG_CASC30" ], [ "CLK_FEED_R_CK_BUFG_CASC31", "CLK_FEED_R_CK_BUFG_CASC31" ], [ "CLK_FEED_R_CK_GCLK0", "CLK_FEED_R_CK_GCLK0" ], [ "CLK_FEED_R_CK_GCLK1", "CLK_FEED_R_CK_GCLK1" ], [ "CLK_FEED_R_CK_GCLK2", "CLK_FEED_R_CK_GCLK2" ], [ "CLK_FEED_R_CK_GCLK3", "CLK_FEED_R_CK_GCLK3" ], [ "CLK_FEED_R_CK_GCLK4", "CLK_FEED_R_CK_GCLK4" ], [ "CLK_FEED_R_CK_GCLK5", "CLK_FEED_R_CK_GCLK5" ], [ "CLK_FEED_R_CK_GCLK6", "CLK_FEED_R_CK_GCLK6" ], [ "CLK_FEED_R_CK_GCLK7", "CLK_FEED_R_CK_GCLK7" ], [ "CLK_FEED_R_CK_GCLK8", "CLK_FEED_R_CK_GCLK8" ], [ "CLK_FEED_R_CK_GCLK9", "CLK_FEED_R_CK_GCLK9" ], [ "CLK_FEED_R_CK_GCLK10", "CLK_FEED_R_CK_GCLK10" ], [ "CLK_FEED_R_CK_GCLK11", "CLK_FEED_R_CK_GCLK11" ], [ "CLK_FEED_R_CK_GCLK12", "CLK_FEED_R_CK_GCLK12" ], [ "CLK_FEED_R_CK_GCLK13", "CLK_FEED_R_CK_GCLK13" ], [ "CLK_FEED_R_CK_GCLK14", "CLK_FEED_R_CK_GCLK14" ], [ "CLK_FEED_R_CK_GCLK15", "CLK_FEED_R_CK_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_FEED_R_CK_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_FEED_R_CK_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_FEED_R_CK_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_FEED_R_CK_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_FEED_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_FEED_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_FEED_R_CK_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_FEED_R_CK_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_FEED_R_CK_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_FEED_R_CK_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_FEED_R_CK_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_FEED_R_CK_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_FEED_R_CK_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_FEED_R_CK_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_FEED_R_CK_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_FEED_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "CLK_FEED", "CLK_PMV2_SVT" ], "wire_pairs": [ [ "CLK_FEED_R_CK_BUFG_CASC0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ "CLK_FEED_R_CK_BUFG_CASC1", "CLK_FEED_R_CK_BUFG_CASC1" ], [ "CLK_FEED_R_CK_BUFG_CASC2", "CLK_FEED_R_CK_BUFG_CASC2" ], [ "CLK_FEED_R_CK_BUFG_CASC3", "CLK_FEED_R_CK_BUFG_CASC3" ], [ "CLK_FEED_R_CK_BUFG_CASC4", "CLK_FEED_R_CK_BUFG_CASC4" ], [ "CLK_FEED_R_CK_BUFG_CASC5", "CLK_FEED_R_CK_BUFG_CASC5" ], [ "CLK_FEED_R_CK_BUFG_CASC6", "CLK_FEED_R_CK_BUFG_CASC6" ], [ "CLK_FEED_R_CK_BUFG_CASC7", "CLK_FEED_R_CK_BUFG_CASC7" ], [ "CLK_FEED_R_CK_BUFG_CASC8", "CLK_FEED_R_CK_BUFG_CASC8" ], [ "CLK_FEED_R_CK_BUFG_CASC9", "CLK_FEED_R_CK_BUFG_CASC9" ], [ "CLK_FEED_R_CK_BUFG_CASC10", "CLK_FEED_R_CK_BUFG_CASC10" ], [ "CLK_FEED_R_CK_BUFG_CASC11", "CLK_FEED_R_CK_BUFG_CASC11" ], [ "CLK_FEED_R_CK_BUFG_CASC12", "CLK_FEED_R_CK_BUFG_CASC12" ], [ "CLK_FEED_R_CK_BUFG_CASC13", "CLK_FEED_R_CK_BUFG_CASC13" ], [ "CLK_FEED_R_CK_BUFG_CASC14", "CLK_FEED_R_CK_BUFG_CASC14" ], [ "CLK_FEED_R_CK_BUFG_CASC15", "CLK_FEED_R_CK_BUFG_CASC15" ], [ "CLK_FEED_R_CK_BUFG_CASC16", "CLK_FEED_R_CK_BUFG_CASC16" ], [ "CLK_FEED_R_CK_BUFG_CASC17", "CLK_FEED_R_CK_BUFG_CASC17" ], [ "CLK_FEED_R_CK_BUFG_CASC18", "CLK_FEED_R_CK_BUFG_CASC18" ], [ "CLK_FEED_R_CK_BUFG_CASC19", "CLK_FEED_R_CK_BUFG_CASC19" ], [ "CLK_FEED_R_CK_BUFG_CASC20", "CLK_FEED_R_CK_BUFG_CASC20" ], [ "CLK_FEED_R_CK_BUFG_CASC21", "CLK_FEED_R_CK_BUFG_CASC21" ], [ "CLK_FEED_R_CK_BUFG_CASC22", "CLK_FEED_R_CK_BUFG_CASC22" ], [ "CLK_FEED_R_CK_BUFG_CASC23", "CLK_FEED_R_CK_BUFG_CASC23" ], [ "CLK_FEED_R_CK_BUFG_CASC24", "CLK_FEED_R_CK_BUFG_CASC24" ], [ "CLK_FEED_R_CK_BUFG_CASC25", "CLK_FEED_R_CK_BUFG_CASC25" ], [ "CLK_FEED_R_CK_BUFG_CASC26", "CLK_FEED_R_CK_BUFG_CASC26" ], [ "CLK_FEED_R_CK_BUFG_CASC27", "CLK_FEED_R_CK_BUFG_CASC27" ], [ "CLK_FEED_R_CK_BUFG_CASC28", "CLK_FEED_R_CK_BUFG_CASC28" ], [ "CLK_FEED_R_CK_BUFG_CASC29", "CLK_FEED_R_CK_BUFG_CASC29" ], [ "CLK_FEED_R_CK_BUFG_CASC30", "CLK_FEED_R_CK_BUFG_CASC30" ], [ "CLK_FEED_R_CK_BUFG_CASC31", "CLK_FEED_R_CK_BUFG_CASC31" ], [ "CLK_FEED_R_CK_GCLK0", "CLK_FEED_R_CK_GCLK0" ], [ "CLK_FEED_R_CK_GCLK1", "CLK_FEED_R_CK_GCLK1" ], [ "CLK_FEED_R_CK_GCLK2", "CLK_FEED_R_CK_GCLK2" ], [ "CLK_FEED_R_CK_GCLK3", "CLK_FEED_R_CK_GCLK3" ], [ "CLK_FEED_R_CK_GCLK4", "CLK_FEED_R_CK_GCLK4" ], [ "CLK_FEED_R_CK_GCLK5", "CLK_FEED_R_CK_GCLK5" ], [ "CLK_FEED_R_CK_GCLK6", "CLK_FEED_R_CK_GCLK6" ], [ "CLK_FEED_R_CK_GCLK7", "CLK_FEED_R_CK_GCLK7" ], [ "CLK_FEED_R_CK_GCLK8", "CLK_FEED_R_CK_GCLK8" ], [ "CLK_FEED_R_CK_GCLK9", "CLK_FEED_R_CK_GCLK9" ], [ "CLK_FEED_R_CK_GCLK10", "CLK_FEED_R_CK_GCLK10" ], [ "CLK_FEED_R_CK_GCLK11", "CLK_FEED_R_CK_GCLK11" ], [ "CLK_FEED_R_CK_GCLK12", "CLK_FEED_R_CK_GCLK12" ], [ "CLK_FEED_R_CK_GCLK13", "CLK_FEED_R_CK_GCLK13" ], [ "CLK_FEED_R_CK_GCLK14", "CLK_FEED_R_CK_GCLK14" ], [ "CLK_FEED_R_CK_GCLK15", "CLK_FEED_R_CK_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_FEED_R_CK_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_FEED_R_CK_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_FEED_R_CK_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_FEED_R_CK_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_FEED_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_FEED_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_FEED_R_CK_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_FEED_R_CK_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_FEED_R_CK_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_FEED_R_CK_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_FEED_R_CK_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_FEED_R_CK_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_FEED_R_CK_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_FEED_R_CK_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_FEED_R_CK_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_FEED_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "CLK_FEED", "CLK_PMVIOB" ], "wire_pairs": [ [ "CLK_FEED_R_CK_BUFG_CASC0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ "CLK_FEED_R_CK_BUFG_CASC1", "CLK_FEED_R_CK_BUFG_CASC1" ], [ "CLK_FEED_R_CK_BUFG_CASC2", "CLK_FEED_R_CK_BUFG_CASC2" ], [ "CLK_FEED_R_CK_BUFG_CASC3", "CLK_FEED_R_CK_BUFG_CASC3" ], [ "CLK_FEED_R_CK_BUFG_CASC4", "CLK_FEED_R_CK_BUFG_CASC4" ], [ "CLK_FEED_R_CK_BUFG_CASC5", "CLK_FEED_R_CK_BUFG_CASC5" ], [ "CLK_FEED_R_CK_BUFG_CASC6", "CLK_FEED_R_CK_BUFG_CASC6" ], [ "CLK_FEED_R_CK_BUFG_CASC7", "CLK_FEED_R_CK_BUFG_CASC7" ], [ "CLK_FEED_R_CK_BUFG_CASC8", "CLK_FEED_R_CK_BUFG_CASC8" ], [ "CLK_FEED_R_CK_BUFG_CASC9", "CLK_FEED_R_CK_BUFG_CASC9" ], [ "CLK_FEED_R_CK_BUFG_CASC10", "CLK_FEED_R_CK_BUFG_CASC10" ], [ "CLK_FEED_R_CK_BUFG_CASC11", "CLK_FEED_R_CK_BUFG_CASC11" ], [ "CLK_FEED_R_CK_BUFG_CASC12", "CLK_FEED_R_CK_BUFG_CASC12" ], [ "CLK_FEED_R_CK_BUFG_CASC13", "CLK_FEED_R_CK_BUFG_CASC13" ], [ "CLK_FEED_R_CK_BUFG_CASC14", "CLK_FEED_R_CK_BUFG_CASC14" ], [ "CLK_FEED_R_CK_BUFG_CASC15", "CLK_FEED_R_CK_BUFG_CASC15" ], [ "CLK_FEED_R_CK_BUFG_CASC16", "CLK_FEED_R_CK_BUFG_CASC16" ], [ "CLK_FEED_R_CK_BUFG_CASC17", "CLK_FEED_R_CK_BUFG_CASC17" ], [ "CLK_FEED_R_CK_BUFG_CASC18", "CLK_FEED_R_CK_BUFG_CASC18" ], [ "CLK_FEED_R_CK_BUFG_CASC19", "CLK_FEED_R_CK_BUFG_CASC19" ], [ "CLK_FEED_R_CK_BUFG_CASC20", "CLK_FEED_R_CK_BUFG_CASC20" ], [ "CLK_FEED_R_CK_BUFG_CASC21", "CLK_FEED_R_CK_BUFG_CASC21" ], [ "CLK_FEED_R_CK_BUFG_CASC22", "CLK_FEED_R_CK_BUFG_CASC22" ], [ "CLK_FEED_R_CK_BUFG_CASC23", "CLK_FEED_R_CK_BUFG_CASC23" ], [ "CLK_FEED_R_CK_BUFG_CASC24", "CLK_FEED_R_CK_BUFG_CASC24" ], [ "CLK_FEED_R_CK_BUFG_CASC25", "CLK_FEED_R_CK_BUFG_CASC25" ], [ "CLK_FEED_R_CK_BUFG_CASC26", "CLK_FEED_R_CK_BUFG_CASC26" ], [ "CLK_FEED_R_CK_BUFG_CASC27", "CLK_FEED_R_CK_BUFG_CASC27" ], [ "CLK_FEED_R_CK_BUFG_CASC28", "CLK_FEED_R_CK_BUFG_CASC28" ], [ "CLK_FEED_R_CK_BUFG_CASC29", "CLK_FEED_R_CK_BUFG_CASC29" ], [ "CLK_FEED_R_CK_BUFG_CASC30", "CLK_FEED_R_CK_BUFG_CASC30" ], [ "CLK_FEED_R_CK_BUFG_CASC31", "CLK_FEED_R_CK_BUFG_CASC31" ], [ "CLK_FEED_R_CK_GCLK0", "CLK_FEED_R_CK_GCLK0" ], [ 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"CLK_FEED_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_FEED_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_FEED_R_CK_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_FEED_R_CK_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_FEED_R_CK_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_FEED_R_CK_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_FEED_R_CK_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_FEED_R_CK_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_FEED_R_CK_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_FEED_R_CK_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_FEED_R_CK_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_FEED_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "CLK_FEED", "CLK_PMVIOB" ], "wire_pairs": [ [ "CLK_FEED_R_CK_BUFG_CASC0", "CLK_FEED_R_CK_BUFG_CASC0" ], [ "CLK_FEED_R_CK_BUFG_CASC1", "CLK_FEED_R_CK_BUFG_CASC1" ], [ "CLK_FEED_R_CK_BUFG_CASC2", "CLK_FEED_R_CK_BUFG_CASC2" ], [ "CLK_FEED_R_CK_BUFG_CASC3", "CLK_FEED_R_CK_BUFG_CASC3" ], [ "CLK_FEED_R_CK_BUFG_CASC4", "CLK_FEED_R_CK_BUFG_CASC4" ], [ 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"CLK_FEED_R_CK_BUFG_CASC21", "CLK_FEED_R_CK_BUFG_CASC21" ], [ "CLK_FEED_R_CK_BUFG_CASC22", "CLK_FEED_R_CK_BUFG_CASC22" ], [ "CLK_FEED_R_CK_BUFG_CASC23", "CLK_FEED_R_CK_BUFG_CASC23" ], [ "CLK_FEED_R_CK_BUFG_CASC24", "CLK_FEED_R_CK_BUFG_CASC24" ], [ "CLK_FEED_R_CK_BUFG_CASC25", "CLK_FEED_R_CK_BUFG_CASC25" ], [ "CLK_FEED_R_CK_BUFG_CASC26", "CLK_FEED_R_CK_BUFG_CASC26" ], [ "CLK_FEED_R_CK_BUFG_CASC27", "CLK_FEED_R_CK_BUFG_CASC27" ], [ "CLK_FEED_R_CK_BUFG_CASC28", "CLK_FEED_R_CK_BUFG_CASC28" ], [ "CLK_FEED_R_CK_BUFG_CASC29", "CLK_FEED_R_CK_BUFG_CASC29" ], [ "CLK_FEED_R_CK_BUFG_CASC30", "CLK_FEED_R_CK_BUFG_CASC30" ], [ "CLK_FEED_R_CK_BUFG_CASC31", "CLK_FEED_R_CK_BUFG_CASC31" ], [ "CLK_FEED_R_CK_GCLK0", "CLK_FEED_R_CK_GCLK0" ], [ "CLK_FEED_R_CK_GCLK1", "CLK_FEED_R_CK_GCLK1" ], [ "CLK_FEED_R_CK_GCLK2", "CLK_FEED_R_CK_GCLK2" ], [ "CLK_FEED_R_CK_GCLK3", "CLK_FEED_R_CK_GCLK3" ], [ "CLK_FEED_R_CK_GCLK4", "CLK_FEED_R_CK_GCLK4" ], [ "CLK_FEED_R_CK_GCLK5", "CLK_FEED_R_CK_GCLK5" ], [ "CLK_FEED_R_CK_GCLK6", "CLK_FEED_R_CK_GCLK6" ], [ "CLK_FEED_R_CK_GCLK7", "CLK_FEED_R_CK_GCLK7" ], [ "CLK_FEED_R_CK_GCLK8", "CLK_FEED_R_CK_GCLK8" ], [ "CLK_FEED_R_CK_GCLK9", "CLK_FEED_R_CK_GCLK9" ], [ "CLK_FEED_R_CK_GCLK10", "CLK_FEED_R_CK_GCLK10" ], [ "CLK_FEED_R_CK_GCLK11", "CLK_FEED_R_CK_GCLK11" ], [ "CLK_FEED_R_CK_GCLK12", "CLK_FEED_R_CK_GCLK12" ], [ "CLK_FEED_R_CK_GCLK13", "CLK_FEED_R_CK_GCLK13" ], [ "CLK_FEED_R_CK_GCLK14", "CLK_FEED_R_CK_GCLK14" ], [ "CLK_FEED_R_CK_GCLK15", "CLK_FEED_R_CK_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_FEED_R_CK_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_FEED_R_CK_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_FEED_R_CK_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_FEED_R_CK_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_FEED_R_CK_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_FEED_R_CK_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_FEED_R_CK_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_FEED_R_CK_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_FEED_R_CK_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_FEED_R_CK_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_FEED_R_CK_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_FEED_R_CK_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_FEED_R_CK_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_FEED_R_CK_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_FEED_R_CK_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_FEED_R_CK_GCLK31" ] ] }, { "grid_deltas": [ 0, -1 ], "tile_types": [ "CLK_FEED", "CLK_TERM" ], "wire_pairs": [ [ "CLK_FEED_R_CK_GCLK0", "CLK_TERM_R_GCLK0" ], [ "CLK_FEED_R_CK_GCLK1", "CLK_TERM_R_GCLK1" ], [ "CLK_FEED_R_CK_GCLK2", "CLK_TERM_R_GCLK2" ], [ "CLK_FEED_R_CK_GCLK3", "CLK_TERM_R_GCLK3" ], [ "CLK_FEED_R_CK_GCLK4", "CLK_TERM_R_GCLK4" ], [ "CLK_FEED_R_CK_GCLK5", "CLK_TERM_R_GCLK5" ], [ "CLK_FEED_R_CK_GCLK6", "CLK_TERM_R_GCLK6" ], [ "CLK_FEED_R_CK_GCLK7", "CLK_TERM_R_GCLK7" ], [ "CLK_FEED_R_CK_GCLK8", "CLK_TERM_R_GCLK8" ], [ "CLK_FEED_R_CK_GCLK9", "CLK_TERM_R_GCLK9" ], [ "CLK_FEED_R_CK_GCLK10", "CLK_TERM_R_GCLK10" ], [ "CLK_FEED_R_CK_GCLK11", "CLK_TERM_R_GCLK11" ], [ "CLK_FEED_R_CK_GCLK12", "CLK_TERM_R_GCLK12" ], [ "CLK_FEED_R_CK_GCLK13", "CLK_TERM_R_GCLK13" ], [ "CLK_FEED_R_CK_GCLK14", "CLK_TERM_R_GCLK14" ], [ "CLK_FEED_R_CK_GCLK15", "CLK_TERM_R_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_TERM_R_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_TERM_R_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_TERM_R_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_TERM_R_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_TERM_R_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_TERM_R_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_TERM_R_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_TERM_R_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_TERM_R_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_TERM_R_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_TERM_R_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_TERM_R_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_TERM_R_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_TERM_R_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_TERM_R_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_TERM_R_GCLK31" ] ] }, { "grid_deltas": [ 0, 1 ], "tile_types": [ "CLK_FEED", "CLK_TERM" ], "wire_pairs": [ [ "CLK_FEED_R_CK_GCLK0", "CLK_TERM_R_GCLK0" ], [ "CLK_FEED_R_CK_GCLK1", "CLK_TERM_R_GCLK1" ], [ "CLK_FEED_R_CK_GCLK2", "CLK_TERM_R_GCLK2" ], [ "CLK_FEED_R_CK_GCLK3", "CLK_TERM_R_GCLK3" ], [ "CLK_FEED_R_CK_GCLK4", "CLK_TERM_R_GCLK4" ], [ "CLK_FEED_R_CK_GCLK5", "CLK_TERM_R_GCLK5" ], [ "CLK_FEED_R_CK_GCLK6", "CLK_TERM_R_GCLK6" ], [ "CLK_FEED_R_CK_GCLK7", "CLK_TERM_R_GCLK7" ], [ "CLK_FEED_R_CK_GCLK8", "CLK_TERM_R_GCLK8" ], [ "CLK_FEED_R_CK_GCLK9", "CLK_TERM_R_GCLK9" ], [ "CLK_FEED_R_CK_GCLK10", "CLK_TERM_R_GCLK10" ], [ "CLK_FEED_R_CK_GCLK11", "CLK_TERM_R_GCLK11" ], [ "CLK_FEED_R_CK_GCLK12", "CLK_TERM_R_GCLK12" ], [ "CLK_FEED_R_CK_GCLK13", "CLK_TERM_R_GCLK13" ], [ "CLK_FEED_R_CK_GCLK14", "CLK_TERM_R_GCLK14" ], [ "CLK_FEED_R_CK_GCLK15", "CLK_TERM_R_GCLK15" ], [ "CLK_FEED_R_CK_GCLK16", "CLK_TERM_R_GCLK16" ], [ "CLK_FEED_R_CK_GCLK17", "CLK_TERM_R_GCLK17" ], [ "CLK_FEED_R_CK_GCLK18", "CLK_TERM_R_GCLK18" ], [ "CLK_FEED_R_CK_GCLK19", "CLK_TERM_R_GCLK19" ], [ "CLK_FEED_R_CK_GCLK20", "CLK_TERM_R_GCLK20" ], [ "CLK_FEED_R_CK_GCLK21", "CLK_TERM_R_GCLK21" ], [ "CLK_FEED_R_CK_GCLK22", "CLK_TERM_R_GCLK22" ], [ "CLK_FEED_R_CK_GCLK23", "CLK_TERM_R_GCLK23" ], [ "CLK_FEED_R_CK_GCLK24", "CLK_TERM_R_GCLK24" ], [ "CLK_FEED_R_CK_GCLK25", "CLK_TERM_R_GCLK25" ], [ "CLK_FEED_R_CK_GCLK26", "CLK_TERM_R_GCLK26" ], [ "CLK_FEED_R_CK_GCLK27", "CLK_TERM_R_GCLK27" ], [ "CLK_FEED_R_CK_GCLK28", "CLK_TERM_R_GCLK28" ], [ "CLK_FEED_R_CK_GCLK29", "CLK_TERM_R_GCLK29" ], [ "CLK_FEED_R_CK_GCLK30", "CLK_TERM_R_GCLK30" ], [ "CLK_FEED_R_CK_GCLK31", "CLK_TERM_R_GCLK31" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "CLK_FEED", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_FEED_EE2A0", "INT_INTERFACE_EE2A0" ], [ "CLK_FEED_EE2A1", "INT_INTERFACE_EE2A1" ], [ "CLK_FEED_EE2A2", "INT_INTERFACE_EE2A2" ], [ "CLK_FEED_EE2A3", "INT_INTERFACE_EE2A3" ], [ "CLK_FEED_EE2BEG0", "INT_INTERFACE_EE2BEG0" ], [ "CLK_FEED_EE2BEG1", "INT_INTERFACE_EE2BEG1" ], [ "CLK_FEED_EE2BEG2", "INT_INTERFACE_EE2BEG2" ], [ "CLK_FEED_EE2BEG3", "INT_INTERFACE_EE2BEG3" ], [ "CLK_FEED_EE4A0", "INT_INTERFACE_EE4A0" ], [ "CLK_FEED_EE4A1", "INT_INTERFACE_EE4A1" ], [ "CLK_FEED_EE4A2", "INT_INTERFACE_EE4A2" ], [ "CLK_FEED_EE4A3", "INT_INTERFACE_EE4A3" ], [ "CLK_FEED_EE4B0", "INT_INTERFACE_EE4B0" ], [ "CLK_FEED_EE4B1", "INT_INTERFACE_EE4B1" ], [ "CLK_FEED_EE4B2", "INT_INTERFACE_EE4B2" ], [ "CLK_FEED_EE4B3", "INT_INTERFACE_EE4B3" ], [ "CLK_FEED_EE4BEG0", "INT_INTERFACE_EE4BEG0" ], [ "CLK_FEED_EE4BEG1", "INT_INTERFACE_EE4BEG1" ], [ "CLK_FEED_EE4BEG2", "INT_INTERFACE_EE4BEG2" ], [ "CLK_FEED_EE4BEG3", "INT_INTERFACE_EE4BEG3" ], [ "CLK_FEED_EE4C0", "INT_INTERFACE_EE4C0" ], [ "CLK_FEED_EE4C1", "INT_INTERFACE_EE4C1" ], [ "CLK_FEED_EE4C2", "INT_INTERFACE_EE4C2" ], [ "CLK_FEED_EE4C3", "INT_INTERFACE_EE4C3" ], [ "CLK_FEED_EL1BEG0", "INT_INTERFACE_EL1BEG0" ], [ "CLK_FEED_EL1BEG1", "INT_INTERFACE_EL1BEG1" ], [ "CLK_FEED_EL1BEG2", "INT_INTERFACE_EL1BEG2" ], [ "CLK_FEED_EL1BEG3", "INT_INTERFACE_EL1BEG3" ], [ "CLK_FEED_ER1BEG0", "INT_INTERFACE_ER1BEG0" ], [ "CLK_FEED_ER1BEG1", "INT_INTERFACE_ER1BEG1" ], [ "CLK_FEED_ER1BEG2", "INT_INTERFACE_ER1BEG2" ], [ "CLK_FEED_ER1BEG3", "INT_INTERFACE_ER1BEG3" ], [ "CLK_FEED_LH1", "INT_INTERFACE_LH1" ], [ "CLK_FEED_LH2", "INT_INTERFACE_LH2" ], [ "CLK_FEED_LH3", "INT_INTERFACE_LH3" ], [ "CLK_FEED_LH4", "INT_INTERFACE_LH4" ], [ "CLK_FEED_LH5", "INT_INTERFACE_LH5" ], [ "CLK_FEED_LH6", "INT_INTERFACE_LH6" ], [ "CLK_FEED_LH7", "INT_INTERFACE_LH7" ], [ "CLK_FEED_LH8", "INT_INTERFACE_LH8" ], [ "CLK_FEED_LH9", "INT_INTERFACE_LH9" ], [ "CLK_FEED_LH10", "INT_INTERFACE_LH10" ], [ "CLK_FEED_LH11", "INT_INTERFACE_LH11" ], [ "CLK_FEED_LH12", "INT_INTERFACE_LH12" ], [ "CLK_FEED_MONITOR_N", "INT_INTERFACE_MONITOR_N" ], [ "CLK_FEED_MONITOR_P", "INT_INTERFACE_MONITOR_P" ], [ "CLK_FEED_NE2A0", "INT_INTERFACE_NE2A0" ], [ "CLK_FEED_NE2A1", "INT_INTERFACE_NE2A1" ], [ "CLK_FEED_NE2A2", "INT_INTERFACE_NE2A2" ], [ "CLK_FEED_NE2A3", "INT_INTERFACE_NE2A3" ], [ "CLK_FEED_NE4BEG0", "INT_INTERFACE_NE4BEG0" ], [ "CLK_FEED_NE4BEG1", "INT_INTERFACE_NE4BEG1" ], [ "CLK_FEED_NE4BEG2", "INT_INTERFACE_NE4BEG2" ], [ "CLK_FEED_NE4BEG3", "INT_INTERFACE_NE4BEG3" ], [ "CLK_FEED_NE4C0", "INT_INTERFACE_NE4C0" ], [ "CLK_FEED_NE4C1", "INT_INTERFACE_NE4C1" ], [ "CLK_FEED_NE4C2", "INT_INTERFACE_NE4C2" ], [ "CLK_FEED_NE4C3", "INT_INTERFACE_NE4C3" ], [ "CLK_FEED_NW2A0", "INT_INTERFACE_NW2A0" ], [ "CLK_FEED_NW2A1", "INT_INTERFACE_NW2A1" ], [ "CLK_FEED_NW2A2", "INT_INTERFACE_NW2A2" ], [ "CLK_FEED_NW2A3", "INT_INTERFACE_NW2A3" ], [ "CLK_FEED_NW4A0", "INT_INTERFACE_NW4A0" ], [ "CLK_FEED_NW4A1", "INT_INTERFACE_NW4A1" ], [ "CLK_FEED_NW4A2", "INT_INTERFACE_NW4A2" ], [ "CLK_FEED_NW4A3", "INT_INTERFACE_NW4A3" ], [ "CLK_FEED_NW4END0", "INT_INTERFACE_NW4END0" ], [ "CLK_FEED_NW4END1", "INT_INTERFACE_NW4END1" ], [ "CLK_FEED_NW4END2", "INT_INTERFACE_NW4END2" ], [ "CLK_FEED_NW4END3", "INT_INTERFACE_NW4END3" ], [ "CLK_FEED_SE2A0", "INT_INTERFACE_SE2A0" ], [ "CLK_FEED_SE2A1", "INT_INTERFACE_SE2A1" ], [ "CLK_FEED_SE2A2", "INT_INTERFACE_SE2A2" ], [ "CLK_FEED_SE2A3", "INT_INTERFACE_SE2A3" ], [ "CLK_FEED_SE4BEG0", "INT_INTERFACE_SE4BEG0" ], [ "CLK_FEED_SE4BEG1", "INT_INTERFACE_SE4BEG1" ], [ "CLK_FEED_SE4BEG2", "INT_INTERFACE_SE4BEG2" ], [ "CLK_FEED_SE4BEG3", "INT_INTERFACE_SE4BEG3" ], [ "CLK_FEED_SE4C0", "INT_INTERFACE_SE4C0" ], [ "CLK_FEED_SE4C1", "INT_INTERFACE_SE4C1" ], [ "CLK_FEED_SE4C2", "INT_INTERFACE_SE4C2" ], [ "CLK_FEED_SE4C3", "INT_INTERFACE_SE4C3" ], [ "CLK_FEED_SW2A0", "INT_INTERFACE_SW2A0" ], [ "CLK_FEED_SW2A1", "INT_INTERFACE_SW2A1" ], [ "CLK_FEED_SW2A2", "INT_INTERFACE_SW2A2" ], [ "CLK_FEED_SW2A3", "INT_INTERFACE_SW2A3" ], [ "CLK_FEED_SW4A0", "INT_INTERFACE_SW4A0" ], [ "CLK_FEED_SW4A1", "INT_INTERFACE_SW4A1" ], [ "CLK_FEED_SW4A2", "INT_INTERFACE_SW4A2" ], [ "CLK_FEED_SW4A3", "INT_INTERFACE_SW4A3" ], [ "CLK_FEED_SW4END0", "INT_INTERFACE_SW4END0" ], [ "CLK_FEED_SW4END1", "INT_INTERFACE_SW4END1" ], [ "CLK_FEED_SW4END2", "INT_INTERFACE_SW4END2" ], [ "CLK_FEED_SW4END3", "INT_INTERFACE_SW4END3" ], [ "CLK_FEED_WL1END0", "INT_INTERFACE_WL1END0" ], [ "CLK_FEED_WL1END1", "INT_INTERFACE_WL1END1" ], [ "CLK_FEED_WL1END2", "INT_INTERFACE_WL1END2" ], [ "CLK_FEED_WL1END3", "INT_INTERFACE_WL1END3" ], [ "CLK_FEED_WR1END0", "INT_INTERFACE_WR1END0" ], [ "CLK_FEED_WR1END1", "INT_INTERFACE_WR1END1" ], [ "CLK_FEED_WR1END2", "INT_INTERFACE_WR1END2" ], [ "CLK_FEED_WR1END3", "INT_INTERFACE_WR1END3" ], [ "CLK_FEED_WW2A0", "INT_INTERFACE_WW2A0" ], [ "CLK_FEED_WW2A1", "INT_INTERFACE_WW2A1" ], [ "CLK_FEED_WW2A2", "INT_INTERFACE_WW2A2" ], [ "CLK_FEED_WW2A3", "INT_INTERFACE_WW2A3" ], [ "CLK_FEED_WW2END0", "INT_INTERFACE_WW2END0" ], [ "CLK_FEED_WW2END1", "INT_INTERFACE_WW2END1" ], [ "CLK_FEED_WW2END2", "INT_INTERFACE_WW2END2" ], [ "CLK_FEED_WW2END3", "INT_INTERFACE_WW2END3" ], [ "CLK_FEED_WW4A0", "INT_INTERFACE_WW4A0" ], [ "CLK_FEED_WW4A1", "INT_INTERFACE_WW4A1" ], [ "CLK_FEED_WW4A2", "INT_INTERFACE_WW4A2" ], [ "CLK_FEED_WW4A3", "INT_INTERFACE_WW4A3" ], [ "CLK_FEED_WW4B0", "INT_INTERFACE_WW4B0" ], [ "CLK_FEED_WW4B1", "INT_INTERFACE_WW4B1" ], [ "CLK_FEED_WW4B2", "INT_INTERFACE_WW4B2" ], [ "CLK_FEED_WW4B3", "INT_INTERFACE_WW4B3" ], [ "CLK_FEED_WW4C0", "INT_INTERFACE_WW4C0" ], [ "CLK_FEED_WW4C1", "INT_INTERFACE_WW4C1" ], [ "CLK_FEED_WW4C2", "INT_INTERFACE_WW4C2" ], [ "CLK_FEED_WW4C3", "INT_INTERFACE_WW4C3" ], [ "CLK_FEED_WW4END0", "INT_INTERFACE_WW4END0" ], [ "CLK_FEED_WW4END1", "INT_INTERFACE_WW4END1" ], [ "CLK_FEED_WW4END2", "INT_INTERFACE_WW4END2" ], [ "CLK_FEED_WW4END3", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLK_FEED", "VBRK" ], "wire_pairs": [ [ "CLK_FEED_EE2A0", "VBRK_EE2A0" ], [ "CLK_FEED_EE2A1", "VBRK_EE2A1" ], [ "CLK_FEED_EE2A2", "VBRK_EE2A2" ], [ "CLK_FEED_EE2A3", "VBRK_EE2A3" ], [ "CLK_FEED_EE2BEG0", "VBRK_EE2BEG0" ], [ "CLK_FEED_EE2BEG1", "VBRK_EE2BEG1" ], [ "CLK_FEED_EE2BEG2", "VBRK_EE2BEG2" ], [ "CLK_FEED_EE2BEG3", "VBRK_EE2BEG3" ], [ "CLK_FEED_EE4A0", "VBRK_EE4A0" ], [ "CLK_FEED_EE4A1", "VBRK_EE4A1" ], [ "CLK_FEED_EE4A2", "VBRK_EE4A2" ], [ "CLK_FEED_EE4A3", "VBRK_EE4A3" ], [ "CLK_FEED_EE4B0", "VBRK_EE4B0" ], [ "CLK_FEED_EE4B1", "VBRK_EE4B1" ], [ "CLK_FEED_EE4B2", "VBRK_EE4B2" ], [ "CLK_FEED_EE4B3", "VBRK_EE4B3" ], [ "CLK_FEED_EE4BEG0", "VBRK_EE4BEG0" ], [ "CLK_FEED_EE4BEG1", "VBRK_EE4BEG1" ], [ "CLK_FEED_EE4BEG2", "VBRK_EE4BEG2" ], [ "CLK_FEED_EE4BEG3", "VBRK_EE4BEG3" ], [ "CLK_FEED_EE4C0", "VBRK_EE4C0" ], [ "CLK_FEED_EE4C1", "VBRK_EE4C1" ], [ "CLK_FEED_EE4C2", "VBRK_EE4C2" ], [ "CLK_FEED_EE4C3", "VBRK_EE4C3" ], [ "CLK_FEED_EL1BEG0", "VBRK_EL1BEG0" ], [ "CLK_FEED_EL1BEG1", "VBRK_EL1BEG1" ], [ "CLK_FEED_EL1BEG2", "VBRK_EL1BEG2" ], [ "CLK_FEED_EL1BEG3", "VBRK_EL1BEG3" ], [ "CLK_FEED_ER1BEG0", "VBRK_ER1BEG0" ], [ "CLK_FEED_ER1BEG1", "VBRK_ER1BEG1" ], [ "CLK_FEED_ER1BEG2", "VBRK_ER1BEG2" ], [ "CLK_FEED_ER1BEG3", "VBRK_ER1BEG3" ], [ "CLK_FEED_LH1", "VBRK_LH1" ], [ "CLK_FEED_LH2", "VBRK_LH2" ], [ "CLK_FEED_LH3", "VBRK_LH3" ], [ "CLK_FEED_LH4", "VBRK_LH4" ], [ "CLK_FEED_LH5", "VBRK_LH5" ], [ "CLK_FEED_LH6", "VBRK_LH6" ], [ "CLK_FEED_LH7", "VBRK_LH7" ], [ "CLK_FEED_LH8", "VBRK_LH8" ], [ "CLK_FEED_LH9", "VBRK_LH9" ], [ "CLK_FEED_LH10", "VBRK_LH10" ], [ "CLK_FEED_LH11", "VBRK_LH11" ], [ "CLK_FEED_LH12", "VBRK_LH12" ], [ "CLK_FEED_MONITOR_N", "VBRK_MONITOR_N" ], [ "CLK_FEED_MONITOR_P", "VBRK_MONITOR_P" ], [ "CLK_FEED_NE2A0", "VBRK_NE2A0" ], [ "CLK_FEED_NE2A1", "VBRK_NE2A1" ], [ "CLK_FEED_NE2A2", "VBRK_NE2A2" ], [ "CLK_FEED_NE2A3", "VBRK_NE2A3" ], [ "CLK_FEED_NE4BEG0", "VBRK_NE4BEG0" ], [ "CLK_FEED_NE4BEG1", "VBRK_NE4BEG1" ], [ "CLK_FEED_NE4BEG2", "VBRK_NE4BEG2" ], [ "CLK_FEED_NE4BEG3", "VBRK_NE4BEG3" ], [ "CLK_FEED_NE4C0", "VBRK_NE4C0" ], [ "CLK_FEED_NE4C1", "VBRK_NE4C1" ], [ "CLK_FEED_NE4C2", "VBRK_NE4C2" ], [ "CLK_FEED_NE4C3", "VBRK_NE4C3" ], [ "CLK_FEED_NW2A0", "VBRK_NW2A0" ], [ "CLK_FEED_NW2A1", "VBRK_NW2A1" ], [ "CLK_FEED_NW2A2", "VBRK_NW2A2" ], [ "CLK_FEED_NW2A3", "VBRK_NW2A3" ], [ "CLK_FEED_NW4A0", "VBRK_NW4A0" ], [ "CLK_FEED_NW4A1", "VBRK_NW4A1" ], [ "CLK_FEED_NW4A2", "VBRK_NW4A2" ], [ "CLK_FEED_NW4A3", "VBRK_NW4A3" ], [ "CLK_FEED_NW4END0", "VBRK_NW4END0" ], [ "CLK_FEED_NW4END1", "VBRK_NW4END1" ], [ "CLK_FEED_NW4END2", "VBRK_NW4END2" ], [ "CLK_FEED_NW4END3", "VBRK_NW4END3" ], [ "CLK_FEED_SE2A0", "VBRK_SE2A0" ], [ "CLK_FEED_SE2A1", "VBRK_SE2A1" ], [ "CLK_FEED_SE2A2", "VBRK_SE2A2" ], [ "CLK_FEED_SE2A3", "VBRK_SE2A3" ], [ "CLK_FEED_SE4BEG0", "VBRK_SE4BEG0" ], [ "CLK_FEED_SE4BEG1", "VBRK_SE4BEG1" ], [ "CLK_FEED_SE4BEG2", "VBRK_SE4BEG2" ], [ "CLK_FEED_SE4BEG3", "VBRK_SE4BEG3" ], [ "CLK_FEED_SE4C0", "VBRK_SE4C0" ], [ "CLK_FEED_SE4C1", "VBRK_SE4C1" ], [ "CLK_FEED_SE4C2", "VBRK_SE4C2" ], [ "CLK_FEED_SE4C3", "VBRK_SE4C3" ], [ "CLK_FEED_SW2A0", "VBRK_SW2A0" ], [ "CLK_FEED_SW2A1", "VBRK_SW2A1" ], [ "CLK_FEED_SW2A2", "VBRK_SW2A2" ], [ "CLK_FEED_SW2A3", "VBRK_SW2A3" ], [ "CLK_FEED_SW4A0", "VBRK_SW4A0" ], [ "CLK_FEED_SW4A1", "VBRK_SW4A1" ], [ "CLK_FEED_SW4A2", "VBRK_SW4A2" ], [ "CLK_FEED_SW4A3", "VBRK_SW4A3" ], [ "CLK_FEED_SW4END0", "VBRK_SW4END0" ], [ "CLK_FEED_SW4END1", "VBRK_SW4END1" ], [ "CLK_FEED_SW4END2", "VBRK_SW4END2" ], [ "CLK_FEED_SW4END3", "VBRK_SW4END3" ], [ "CLK_FEED_WL1END0", "VBRK_WL1END0" ], [ "CLK_FEED_WL1END1", "VBRK_WL1END1" ], [ "CLK_FEED_WL1END2", "VBRK_WL1END2" ], [ "CLK_FEED_WL1END3", "VBRK_WL1END3" ], [ "CLK_FEED_WR1END0", "VBRK_WR1END0" ], [ "CLK_FEED_WR1END1", "VBRK_WR1END1" ], [ "CLK_FEED_WR1END2", "VBRK_WR1END2" ], [ "CLK_FEED_WR1END3", "VBRK_WR1END3" ], [ "CLK_FEED_WW2A0", "VBRK_WW2A0" ], [ "CLK_FEED_WW2A1", "VBRK_WW2A1" ], [ "CLK_FEED_WW2A2", "VBRK_WW2A2" ], [ "CLK_FEED_WW2A3", "VBRK_WW2A3" ], [ "CLK_FEED_WW2END0", "VBRK_WW2END0" ], [ "CLK_FEED_WW2END1", "VBRK_WW2END1" ], [ "CLK_FEED_WW2END2", "VBRK_WW2END2" ], [ "CLK_FEED_WW2END3", "VBRK_WW2END3" ], [ "CLK_FEED_WW4A0", "VBRK_WW4A0" ], [ "CLK_FEED_WW4A1", "VBRK_WW4A1" ], [ "CLK_FEED_WW4A2", "VBRK_WW4A2" ], [ "CLK_FEED_WW4A3", "VBRK_WW4A3" ], [ "CLK_FEED_WW4B0", "VBRK_WW4B0" ], [ "CLK_FEED_WW4B1", "VBRK_WW4B1" ], [ "CLK_FEED_WW4B2", "VBRK_WW4B2" ], [ "CLK_FEED_WW4B3", "VBRK_WW4B3" ], [ "CLK_FEED_WW4C0", "VBRK_WW4C0" ], [ "CLK_FEED_WW4C1", "VBRK_WW4C1" ], [ "CLK_FEED_WW4C2", "VBRK_WW4C2" ], [ "CLK_FEED_WW4C3", "VBRK_WW4C3" ], [ "CLK_FEED_WW4END0", "VBRK_WW4END0" ], [ "CLK_FEED_WW4END1", "VBRK_WW4END1" ], [ "CLK_FEED_WW4END2", "VBRK_WW4END2" ], [ "CLK_FEED_WW4END3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "CLK_HROW_BOT_R", "HCLK_INT_INTERFACE" ], "wire_pairs": [ [ "CLK_HROW_CK_BUFHCLK_L0", "HCLK_INT_INTERFACE_CK_BUFHCLK0" ], [ "CLK_HROW_CK_BUFHCLK_L1", "HCLK_INT_INTERFACE_CK_BUFHCLK1" ], [ "CLK_HROW_CK_BUFHCLK_L2", "HCLK_INT_INTERFACE_CK_BUFHCLK2" ], [ "CLK_HROW_CK_BUFHCLK_L3", "HCLK_INT_INTERFACE_CK_BUFHCLK3" ], [ "CLK_HROW_CK_BUFHCLK_L4", "HCLK_INT_INTERFACE_CK_BUFHCLK4" ], [ "CLK_HROW_CK_BUFHCLK_L5", "HCLK_INT_INTERFACE_CK_BUFHCLK5" ], [ "CLK_HROW_CK_BUFHCLK_L6", "HCLK_INT_INTERFACE_CK_BUFHCLK6" ], [ "CLK_HROW_CK_BUFHCLK_L7", "HCLK_INT_INTERFACE_CK_BUFHCLK7" ], [ "CLK_HROW_CK_BUFHCLK_L8", "HCLK_INT_INTERFACE_CK_BUFHCLK8" ], [ "CLK_HROW_CK_BUFHCLK_L9", "HCLK_INT_INTERFACE_CK_BUFHCLK9" ], [ "CLK_HROW_CK_BUFHCLK_L10", "HCLK_INT_INTERFACE_CK_BUFHCLK10" ], [ "CLK_HROW_CK_BUFHCLK_L11", "HCLK_INT_INTERFACE_CK_BUFHCLK11" ], [ "CLK_HROW_CK_BUFRCLK_L0", "HCLK_INT_INTERFACE_CK_BUFRCLK0" ], [ "CLK_HROW_CK_BUFRCLK_L1", "HCLK_INT_INTERFACE_CK_BUFRCLK1" ], [ "CLK_HROW_CK_BUFRCLK_L2", "HCLK_INT_INTERFACE_CK_BUFRCLK2" ], [ "CLK_HROW_CK_BUFRCLK_L3", "HCLK_INT_INTERFACE_CK_BUFRCLK3" ], [ "CLK_HROW_CK_IN_L0", "HCLK_INT_INTERFACE_CK_IN0" ], [ "CLK_HROW_CK_IN_L1", "HCLK_INT_INTERFACE_CK_IN1" ], [ "CLK_HROW_CK_IN_L2", "HCLK_INT_INTERFACE_CK_IN2" ], [ "CLK_HROW_CK_IN_L3", "HCLK_INT_INTERFACE_CK_IN3" ], [ "CLK_HROW_CK_IN_L4", "HCLK_INT_INTERFACE_CK_IN4" ], [ "CLK_HROW_CK_IN_L5", "HCLK_INT_INTERFACE_CK_IN5" ], [ "CLK_HROW_CK_IN_L6", "HCLK_INT_INTERFACE_CK_IN6" ], [ "CLK_HROW_CK_IN_L7", "HCLK_INT_INTERFACE_CK_IN7" ], [ "CLK_HROW_CK_IN_L8", "HCLK_INT_INTERFACE_CK_IN8" ], [ "CLK_HROW_CK_IN_L9", "HCLK_INT_INTERFACE_CK_IN9" ], [ "CLK_HROW_CK_IN_L10", "HCLK_INT_INTERFACE_CK_IN10" ], [ "CLK_HROW_CK_IN_L11", "HCLK_INT_INTERFACE_CK_IN11" ], [ "CLK_HROW_CK_IN_L12", "HCLK_INT_INTERFACE_CK_IN12" ], [ "CLK_HROW_CK_IN_L13", "HCLK_INT_INTERFACE_CK_IN13" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLK_HROW_BOT_R", "HCLK_VBRK" ], "wire_pairs": [ [ "CLK_HROW_CK_BUFHCLK_R0", "HCLK_VBRK_CK_BUFHCLK0" ], [ "CLK_HROW_CK_BUFHCLK_R1", "HCLK_VBRK_CK_BUFHCLK1" ], [ "CLK_HROW_CK_BUFHCLK_R2", "HCLK_VBRK_CK_BUFHCLK2" ], [ "CLK_HROW_CK_BUFHCLK_R3", "HCLK_VBRK_CK_BUFHCLK3" ], [ "CLK_HROW_CK_BUFHCLK_R4", "HCLK_VBRK_CK_BUFHCLK4" ], [ "CLK_HROW_CK_BUFHCLK_R5", "HCLK_VBRK_CK_BUFHCLK5" ], [ "CLK_HROW_CK_BUFHCLK_R6", "HCLK_VBRK_CK_BUFHCLK6" ], [ "CLK_HROW_CK_BUFHCLK_R7", "HCLK_VBRK_CK_BUFHCLK7" ], [ "CLK_HROW_CK_BUFHCLK_R8", "HCLK_VBRK_CK_BUFHCLK8" ], [ "CLK_HROW_CK_BUFHCLK_R9", "HCLK_VBRK_CK_BUFHCLK9" ], [ "CLK_HROW_CK_BUFHCLK_R10", "HCLK_VBRK_CK_BUFHCLK10" ], [ "CLK_HROW_CK_BUFHCLK_R11", "HCLK_VBRK_CK_BUFHCLK11" ], [ "CLK_HROW_CK_BUFRCLK_R0", "HCLK_VBRK_CK_BUFRCLK0" ], [ "CLK_HROW_CK_BUFRCLK_R1", "HCLK_VBRK_CK_BUFRCLK1" ], [ "CLK_HROW_CK_BUFRCLK_R2", "HCLK_VBRK_CK_BUFRCLK2" ], [ "CLK_HROW_CK_BUFRCLK_R3", "HCLK_VBRK_CK_BUFRCLK3" ], [ "CLK_HROW_CK_IN_R0", "HCLK_VBRK_MUX_CLK0" ], [ "CLK_HROW_CK_IN_R1", "HCLK_VBRK_MUX_CLK1" ], [ "CLK_HROW_CK_IN_R2", "HCLK_VBRK_MUX_CLK2" ], [ "CLK_HROW_CK_IN_R3", "HCLK_VBRK_MUX_CLK3" ], [ "CLK_HROW_CK_IN_R4", "HCLK_VBRK_MUX_CLK4" ], [ "CLK_HROW_CK_IN_R5", "HCLK_VBRK_MUX_CLK5" ], [ "CLK_HROW_CK_IN_R6", "HCLK_VBRK_MUX_CLK6" ], [ "CLK_HROW_CK_IN_R7", "HCLK_VBRK_MUX_CLK7" ], [ "CLK_HROW_CK_IN_R8", "HCLK_VBRK_MUX_CLK8" ], [ "CLK_HROW_CK_IN_R9", "HCLK_VBRK_MUX_CLK9" ], [ "CLK_HROW_CK_IN_R10", "HCLK_VBRK_MUX_CLK10" ], [ "CLK_HROW_CK_IN_R11", "HCLK_VBRK_MUX_CLK11" ], [ "CLK_HROW_CK_IN_R12", "HCLK_VBRK_MUX_CLK12" ], [ "CLK_HROW_CK_IN_R13", "HCLK_VBRK_MUX_CLK13" ] ] }, { "grid_deltas": [ -1, -4 ], "tile_types": [ "CLK_HROW_BOT_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_7", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_7", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_7", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_7", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_7", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_7", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_7", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_7", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_7", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_7", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_7", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_7", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_7", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_7", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_7", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_7", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_7", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_7", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_7", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_7", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_7", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_7", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_7", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_7", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_7", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_7", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_7", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_7", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_7", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_7", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_7", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_7", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_7", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_7", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_7", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_7", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_7", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_7", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_7", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_7", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_7", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_7", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_7", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_7", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_7", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_7", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_7", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_7", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_7", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_7", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_7", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_7", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_7", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_7", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_7", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_7", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_7", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_7", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_7", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_7", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_7", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_7", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_7", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_7", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_7", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_7", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_7", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_7", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_7", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_7", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_7", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_7", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_7", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_7", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_7", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_7", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_7", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_7", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_7", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_7", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_7", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_7", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_7", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_7", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_7", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_7", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_7", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_7", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_7", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_7", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_7", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_7", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_7", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_7", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_7", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_7", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_7", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_7", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_7", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_7", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_7", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_7", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_7", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_7", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_7", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_7", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_7", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_7", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_7", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_7", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_7", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_7", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_7", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_7", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_7", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_7", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_7", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_7", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_7", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_7", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_7", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_7", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_7", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_7", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_7", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_7", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_7", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_7", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_7", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_7", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_7", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_7", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_7", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_7", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_7", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_7", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_7", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_7", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_7", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_7", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_7", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_7", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_7", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_7", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_7", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_7", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_7", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_7", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_7", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_7", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_7", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_7", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_7", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_7", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_7", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_7", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_7", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_7", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_7", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_7", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_7", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_7", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_7", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_7", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_7", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_7", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_7", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_7", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_7", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_7", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_7", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_7", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_7", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_7", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_7", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_7", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_7", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_7", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_7", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_7", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_7", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_7", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_7", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_7", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_7", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_7", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_7", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_7", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_7", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_7", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_7", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_7", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -3 ], "tile_types": [ "CLK_HROW_BOT_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_6", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_6", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_6", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_6", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_6", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_6", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_6", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_6", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_6", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_6", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_6", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_6", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_6", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_6", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_6", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_6", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_6", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_6", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_6", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_6", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_6", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_6", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_6", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_6", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_6", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_6", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_6", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_6", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_6", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_6", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_6", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_6", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_6", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_6", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_6", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_6", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_6", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_6", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_6", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_6", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_6", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_6", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_6", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_6", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_6", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_6", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_6", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_6", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_6", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_6", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_6", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_6", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_6", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_6", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_6", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_6", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_6", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_6", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_6", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_6", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_6", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_6", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_6", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_6", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_6", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_6", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_6", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_6", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_6", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_6", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_6", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_6", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_6", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_6", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_6", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_6", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_6", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_6", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_6", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_6", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_6", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_6", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_6", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_6", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_6", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_6", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_6", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_6", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_6", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_6", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_6", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_6", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_6", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_6", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_6", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_6", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_6", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_6", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_6", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_6", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_6", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_6", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_6", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_6", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_6", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_6", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_6", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_6", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_6", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_6", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_6", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_6", "INT_INTERFACE_LH12" ], [ "CLK_HROW_MONITOR_N_6", "INT_INTERFACE_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_6", "INT_INTERFACE_MONITOR_P" ], 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"INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_6", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_6", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_6", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_6", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_6", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_6", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_6", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_6", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_6", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_6", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_6", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_6", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_6", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_6", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_6", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_6", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_6", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_6", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_6", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_6", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_6", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_6", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_6", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_6", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_6", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_6", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_6", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_6", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_6", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_6", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_6", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_6", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_6", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_6", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_6", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_6", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_6", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_6", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_6", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_6", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_6", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_6", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_6", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_6", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_6", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_6", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_6", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_6", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_6", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_6", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_6", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_6", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_6", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_6", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_6", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_6", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_6", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_6", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_6", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -2 ], "tile_types": [ "CLK_HROW_BOT_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_5", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_5", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_5", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_5", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_5", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_5", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_5", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_5", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_5", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_5", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_5", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_5", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_5", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_5", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_5", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_5", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_5", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_5", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_5", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_5", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_5", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_5", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_5", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_5", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_5", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_5", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_5", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_5", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_5", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_5", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_5", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_5", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_5", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_5", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_5", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_5", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_5", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_5", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_5", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_5", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_5", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_5", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_5", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_5", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_5", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_5", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_5", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_5", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_5", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_5", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_5", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_5", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_5", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_5", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_5", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_5", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_5", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_5", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_5", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_5", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_5", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_5", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_5", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_5", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_5", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_5", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_5", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_5", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_5", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_5", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_5", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_5", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_5", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_5", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_5", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_5", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_5", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_5", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_5", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_5", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_5", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_5", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_5", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_5", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_5", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_5", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_5", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_5", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_5", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_5", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_5", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_5", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_5", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_5", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_5", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_5", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_5", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_5", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_5", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_5", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_5", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_5", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_5", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_5", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_5", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_5", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_5", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_5", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_5", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_5", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_5", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_5", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_5", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_5", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_5", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_5", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_5", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_5", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_5", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_5", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_5", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_5", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_5", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_5", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_5", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_5", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_5", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_5", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_5", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_5", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_5", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_5", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_5", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_5", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_5", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_5", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_5", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_5", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_5", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_5", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_5", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_5", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_5", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_5", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_5", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_5", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_5", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_5", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_5", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_5", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_5", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_5", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_5", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_5", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_5", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_5", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_5", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_5", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_5", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_5", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_5", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_5", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_5", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_5", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_5", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_5", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_5", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_5", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_5", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_5", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_5", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_5", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_5", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_5", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_5", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_5", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_5", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_5", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_5", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_5", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_5", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_5", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_5", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_5", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_5", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_5", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_5", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_5", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_5", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_5", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_5", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_5", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -1 ], "tile_types": [ "CLK_HROW_BOT_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_4", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_4", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_4", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_4", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_4", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_4", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_4", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_4", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_4", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_4", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_4", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_4", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_4", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_4", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_4", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_4", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_4", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_4", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_4", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_4", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_4", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_4", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_4", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_4", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_4", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_4", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_4", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_4", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_4", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_4", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_4", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_4", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_4", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_4", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_4", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_4", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_4", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_4", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_4", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_4", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_4", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_4", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_4", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_4", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_4", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_4", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_4", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_4", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_4", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_4", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_4", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_4", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_4", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_4", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_4", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_4", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_4", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_4", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_4", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_4", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_4", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_4", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_4", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_4", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_4", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_4", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_4", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_4", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_4", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_4", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_4", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_4", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_4", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_4", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_4", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_4", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_4", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_4", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_4", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_4", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_4", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_4", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_4", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_4", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_4", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_4", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_4", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_4", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_4", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_4", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_4", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_4", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_4", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_4", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_4", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_4", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_4", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_4", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_4", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_4", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_4", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_4", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_4", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_4", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_4", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_4", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_4", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_4", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_4", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_4", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_4", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_4", "INT_INTERFACE_LH12" ], [ "CLK_HROW_MONITOR_N_4", "INT_INTERFACE_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_4", "INT_INTERFACE_MONITOR_P" ], [ "CLK_HROW_NE2A0_4", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_4", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_4", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_4", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_4", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_4", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_4", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_4", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_4", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_4", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_4", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_4", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_4", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_4", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_4", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_4", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_4", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_4", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_4", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_4", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_4", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_4", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_4", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_4", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_4", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_4", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_4", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_4", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_4", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_4", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_4", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_4", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_4", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_4", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_4", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_4", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_4", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_4", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_4", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_4", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_4", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_4", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_4", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_4", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_4", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_4", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_4", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_4", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_4", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_4", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_4", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_4", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_4", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_4", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_4", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_4", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_4", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_4", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_4", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_4", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_4", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_4", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_4", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_4", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_4", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_4", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_4", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_4", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_4", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_4", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_4", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_4", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_4", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_4", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_4", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_4", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_4", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_4", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_4", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_4", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, 1 ], "tile_types": [ "CLK_HROW_BOT_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_3", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_3", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_3", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_3", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_3", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_3", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_3", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_3", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_3", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_3", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_3", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_3", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_3", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_3", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_3", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_3", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_3", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_3", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_3", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_3", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_3", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_3", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_3", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_3", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_3", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_3", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_3", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_3", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_3", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_3", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_3", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_3", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_3", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_3", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_3", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_3", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_3", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_3", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_3", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_3", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_3", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_3", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_3", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_3", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_3", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_3", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_3", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_3", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_3", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_3", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_3", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_3", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_3", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_3", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_3", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_3", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_3", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_3", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_3", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_3", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_3", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_3", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_3", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_3", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_3", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_3", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_3", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_3", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_3", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_3", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_3", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_3", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_3", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_3", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_3", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_3", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_3", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_3", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_3", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_3", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_3", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_3", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_3", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_3", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_3", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_3", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_3", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_3", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_3", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_3", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_3", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_3", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_3", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_3", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_3", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_3", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_3", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_3", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_3", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_3", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_3", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_3", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_3", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_3", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_3", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_3", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_3", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_3", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_3", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_3", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_3", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_3", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_3", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_3", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_3", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_3", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_3", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_3", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_3", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_3", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_3", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_3", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_3", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_3", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_3", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_3", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_3", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_3", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_3", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_3", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_3", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_3", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_3", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_3", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_3", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_3", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_3", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_3", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_3", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_3", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_3", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_3", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_3", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_3", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_3", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_3", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_3", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_3", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_3", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_3", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_3", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_3", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_3", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_3", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_3", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_3", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_3", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_3", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_3", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_3", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_3", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_3", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_3", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_3", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_3", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_3", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_3", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_3", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_3", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_3", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_3", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_3", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_3", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_3", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_3", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_3", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_3", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_3", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_3", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_3", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_3", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_3", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_3", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_3", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_3", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_3", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_3", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_3", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_3", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_3", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_3", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_3", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, 2 ], "tile_types": [ "CLK_HROW_BOT_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_2", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_2", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_2", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_2", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_2", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_2", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_2", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_2", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_2", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_2", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_2", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_2", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_2", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_2", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_2", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_2", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_2", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_2", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_2", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_2", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_2", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_2", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_2", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_2", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_2", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_2", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_2", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_2", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_2", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_2", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_2", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_2", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_2", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_2", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_2", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_2", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_2", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_2", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_2", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_2", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_2", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_2", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_2", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_2", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_2", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_2", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_2", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_2", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_2", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_2", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_2", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_2", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_2", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_2", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_2", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_2", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_2", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_2", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_2", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_2", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_2", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_2", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_2", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_2", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_2", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_2", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_2", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_2", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_2", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_2", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_2", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_2", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_2", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_2", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_2", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_2", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_2", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_2", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_2", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_2", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_2", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_2", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_2", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_2", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_2", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_2", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_2", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_2", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_2", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_2", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_2", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_2", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_2", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_2", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_2", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_2", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_2", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_2", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_2", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_2", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_2", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_2", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_2", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_2", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_2", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_2", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_2", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_2", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_2", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_2", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_2", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_2", "INT_INTERFACE_LH12" ], [ "CLK_HROW_MONITOR_N_2", "INT_INTERFACE_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_2", "INT_INTERFACE_MONITOR_P" ], [ "CLK_HROW_NE2A0_2", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_2", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_2", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_2", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_2", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_2", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_2", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_2", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_2", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_2", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_2", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_2", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_2", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_2", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_2", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_2", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_2", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_2", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_2", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_2", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_2", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_2", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_2", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_2", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_2", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_2", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_2", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_2", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_2", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_2", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_2", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_2", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_2", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_2", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_2", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_2", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_2", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_2", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_2", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_2", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_2", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_2", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_2", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_2", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_2", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_2", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_2", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_2", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_2", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_2", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_2", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_2", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_2", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_2", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_2", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_2", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_2", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_2", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_2", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_2", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_2", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_2", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_2", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_2", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_2", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_2", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_2", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_2", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_2", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_2", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_2", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_2", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_2", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_2", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_2", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_2", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_2", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_2", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_2", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_2", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, 3 ], "tile_types": [ "CLK_HROW_BOT_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_1", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_1", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_1", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_1", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_1", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_1", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_1", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_1", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_1", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_1", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_1", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_1", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_1", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_1", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_1", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_1", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_1", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_1", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_1", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_1", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_1", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_1", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_1", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_1", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_1", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_1", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_1", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_1", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_1", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_1", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_1", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_1", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_1", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_1", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_1", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_1", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_1", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_1", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_1", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_1", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_1", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_1", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_1", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_1", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_1", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_1", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_1", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_1", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_1", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_1", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_1", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_1", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_1", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_1", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_1", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_1", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_1", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_1", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_1", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_1", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_1", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_1", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_1", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_1", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_1", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_1", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_1", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_1", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_1", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_1", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_1", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_1", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_1", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_1", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_1", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_1", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_1", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_1", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_1", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_1", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_1", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_1", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_1", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_1", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_1", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_1", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_1", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_1", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_1", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_1", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_1", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_1", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_1", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_1", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_1", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_1", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_1", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_1", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_1", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_1", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_1", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_1", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_1", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_1", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_1", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_1", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_1", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_1", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_1", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_1", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_1", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_1", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_1", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_1", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_1", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_1", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_1", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_1", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_1", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_1", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_1", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_1", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_1", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_1", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_1", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_1", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_1", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_1", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_1", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_1", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_1", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_1", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_1", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_1", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_1", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_1", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_1", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_1", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_1", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_1", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_1", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_1", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_1", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_1", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_1", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_1", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_1", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_1", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_1", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_1", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_1", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_1", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_1", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_1", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_1", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_1", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_1", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_1", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_1", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_1", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_1", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_1", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_1", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_1", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_1", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_1", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_1", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_1", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_1", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_1", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_1", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_1", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_1", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_1", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_1", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_1", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_1", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_1", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_1", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_1", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_1", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_1", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_1", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_1", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_1", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_1", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_1", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_1", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_1", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_1", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_1", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_1", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, 4 ], "tile_types": [ "CLK_HROW_BOT_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_0", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_0", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_0", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_0", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_0", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_0", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_0", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_0", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_0", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_0", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_0", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_0", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_0", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_0", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_0", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_0", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_0", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_0", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_0", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_0", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_0", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_0", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_0", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_0", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_0", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_0", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_0", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_0", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_0", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_0", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_0", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_0", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_0", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_0", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_0", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_0", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_0", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_0", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_0", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_0", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_0", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_0", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_0", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_0", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_0", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_0", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_0", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_0", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_0", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_0", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_0", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_0", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_0", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_0", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_0", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_0", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_0", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_0", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_0", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_0", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_0", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_0", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_0", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_0", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_0", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_0", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_0", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_0", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_0", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_0", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_0", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_0", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_0", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_0", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_0", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_0", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_0", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_0", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_0", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_0", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_0", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_0", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_0", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_0", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_0", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_0", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_0", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_0", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_0", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_0", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_0", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_0", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_0", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_0", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_0", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_0", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_0", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_0", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_0", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_0", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_0", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_0", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_0", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_0", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_0", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_0", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_0", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_0", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_0", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_0", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_0", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_0", "INT_INTERFACE_LH12" ], [ "CLK_HROW_MONITOR_N_0", "INT_INTERFACE_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_0", "INT_INTERFACE_MONITOR_P" ], [ "CLK_HROW_NE2A0_0", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_0", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_0", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_0", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_0", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_0", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_0", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_0", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_0", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_0", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_0", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_0", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_0", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_0", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_0", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_0", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_0", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_0", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_0", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_0", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_0", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_0", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_0", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_0", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_0", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_0", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_0", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_0", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_0", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_0", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_0", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_0", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_0", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_0", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_0", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_0", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_0", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_0", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_0", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_0", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_0", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_0", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_0", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_0", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_0", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_0", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_0", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_0", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_0", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_0", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_0", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_0", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_0", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_0", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_0", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_0", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_0", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_0", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_0", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_0", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_0", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_0", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_0", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_0", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_0", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_0", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_0", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_0", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_0", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_0", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_0", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_0", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_0", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_0", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_0", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_0", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_0", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_0", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_0", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_0", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ 1, -4 ], "tile_types": [ "CLK_HROW_BOT_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_7", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_7", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_7", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_7", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_7", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_7", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_7", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_7", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_7", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_7", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_7", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_7", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_7", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_7", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_7", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_7", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_7", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_7", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_7", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_7", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_7", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_7", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_7", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_7", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_7", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_7", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_7", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_7", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_7", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_7", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_7", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_7", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_7", "VBRK_LH1" ], [ "CLK_HROW_LH2_7", "VBRK_LH2" ], [ "CLK_HROW_LH3_7", "VBRK_LH3" ], [ "CLK_HROW_LH4_7", "VBRK_LH4" ], [ "CLK_HROW_LH5_7", "VBRK_LH5" ], [ "CLK_HROW_LH6_7", "VBRK_LH6" ], [ "CLK_HROW_LH7_7", "VBRK_LH7" ], [ "CLK_HROW_LH8_7", "VBRK_LH8" ], [ "CLK_HROW_LH9_7", "VBRK_LH9" ], [ "CLK_HROW_LH10_7", "VBRK_LH10" ], [ "CLK_HROW_LH11_7", "VBRK_LH11" ], [ "CLK_HROW_LH12_7", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_7", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_7", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_7", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_7", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_7", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_7", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_7", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_7", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_7", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_7", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_7", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_7", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_7", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_7", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_7", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_7", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_7", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_7", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_7", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_7", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_7", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_7", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_7", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_7", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_7", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_7", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_7", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_7", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_7", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_7", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_7", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_7", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_7", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_7", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_7", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_7", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_7", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_7", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_7", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_7", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_7", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_7", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_7", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_7", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_7", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_7", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_7", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_7", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_7", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_7", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_7", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_7", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_7", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_7", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_7", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_7", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_7", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_7", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_7", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_7", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_7", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_7", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_7", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_7", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_7", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_7", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_7", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_7", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_7", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_7", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_7", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_7", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_7", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_7", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_7", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_7", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_7", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_7", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_7", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_7", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -3 ], "tile_types": [ "CLK_HROW_BOT_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_6", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_6", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_6", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_6", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_6", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_6", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_6", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_6", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_6", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_6", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_6", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_6", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_6", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_6", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_6", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_6", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_6", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_6", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_6", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_6", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_6", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_6", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_6", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_6", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_6", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_6", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_6", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_6", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_6", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_6", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_6", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_6", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_6", "VBRK_LH1" ], [ "CLK_HROW_LH2_6", "VBRK_LH2" ], [ "CLK_HROW_LH3_6", "VBRK_LH3" ], [ "CLK_HROW_LH4_6", "VBRK_LH4" ], [ "CLK_HROW_LH5_6", "VBRK_LH5" ], [ "CLK_HROW_LH6_6", "VBRK_LH6" ], [ "CLK_HROW_LH7_6", "VBRK_LH7" ], [ "CLK_HROW_LH8_6", "VBRK_LH8" ], [ "CLK_HROW_LH9_6", "VBRK_LH9" ], [ "CLK_HROW_LH10_6", "VBRK_LH10" ], [ "CLK_HROW_LH11_6", "VBRK_LH11" ], [ "CLK_HROW_LH12_6", "VBRK_LH12" ], [ "CLK_HROW_MONITOR_N_6", "VBRK_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_6", "VBRK_MONITOR_P" ], [ "CLK_HROW_NE2A0_6", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_6", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_6", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_6", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_6", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_6", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_6", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_6", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_6", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_6", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_6", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_6", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_6", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_6", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_6", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_6", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_6", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_6", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_6", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_6", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_6", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_6", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_6", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_6", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_6", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_6", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_6", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_6", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_6", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_6", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_6", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_6", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_6", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_6", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_6", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_6", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_6", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_6", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_6", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_6", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_6", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_6", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_6", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_6", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_6", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_6", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_6", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_6", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_6", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_6", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_6", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_6", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_6", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_6", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_6", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_6", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_6", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_6", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_6", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_6", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_6", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_6", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_6", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_6", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_6", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_6", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_6", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_6", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_6", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_6", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_6", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_6", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_6", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_6", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_6", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_6", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_6", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_6", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_6", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_6", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -2 ], "tile_types": [ "CLK_HROW_BOT_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_5", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_5", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_5", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_5", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_5", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_5", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_5", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_5", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_5", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_5", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_5", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_5", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_5", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_5", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_5", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_5", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_5", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_5", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_5", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_5", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_5", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_5", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_5", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_5", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_5", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_5", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_5", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_5", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_5", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_5", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_5", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_5", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_5", "VBRK_LH1" ], [ "CLK_HROW_LH2_5", "VBRK_LH2" ], [ "CLK_HROW_LH3_5", "VBRK_LH3" ], [ "CLK_HROW_LH4_5", "VBRK_LH4" ], [ "CLK_HROW_LH5_5", "VBRK_LH5" ], [ "CLK_HROW_LH6_5", "VBRK_LH6" ], [ "CLK_HROW_LH7_5", "VBRK_LH7" ], [ "CLK_HROW_LH8_5", "VBRK_LH8" ], [ "CLK_HROW_LH9_5", "VBRK_LH9" ], [ "CLK_HROW_LH10_5", "VBRK_LH10" ], [ "CLK_HROW_LH11_5", "VBRK_LH11" ], [ "CLK_HROW_LH12_5", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_5", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_5", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_5", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_5", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_5", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_5", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_5", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_5", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_5", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_5", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_5", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_5", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_5", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_5", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_5", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_5", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_5", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_5", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_5", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_5", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_5", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_5", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_5", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_5", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_5", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_5", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_5", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_5", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_5", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_5", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_5", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_5", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_5", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_5", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_5", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_5", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_5", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_5", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_5", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_5", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_5", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_5", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_5", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_5", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_5", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_5", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_5", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_5", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_5", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_5", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_5", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_5", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_5", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_5", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_5", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_5", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_5", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_5", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_5", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_5", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_5", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_5", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_5", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_5", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_5", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_5", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_5", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_5", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_5", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_5", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_5", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_5", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_5", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_5", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_5", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_5", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_5", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_5", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_5", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_5", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -1 ], "tile_types": [ "CLK_HROW_BOT_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_4", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_4", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_4", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_4", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_4", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_4", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_4", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_4", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_4", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_4", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_4", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_4", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_4", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_4", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_4", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_4", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_4", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_4", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_4", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_4", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_4", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_4", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_4", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_4", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_4", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_4", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_4", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_4", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_4", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_4", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_4", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_4", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_4", "VBRK_LH1" ], [ "CLK_HROW_LH2_4", "VBRK_LH2" ], [ "CLK_HROW_LH3_4", "VBRK_LH3" ], [ "CLK_HROW_LH4_4", "VBRK_LH4" ], [ "CLK_HROW_LH5_4", "VBRK_LH5" ], [ "CLK_HROW_LH6_4", "VBRK_LH6" ], [ "CLK_HROW_LH7_4", "VBRK_LH7" ], [ "CLK_HROW_LH8_4", "VBRK_LH8" ], [ "CLK_HROW_LH9_4", "VBRK_LH9" ], [ "CLK_HROW_LH10_4", "VBRK_LH10" ], [ "CLK_HROW_LH11_4", "VBRK_LH11" ], [ "CLK_HROW_LH12_4", "VBRK_LH12" ], [ "CLK_HROW_MONITOR_N_4", "VBRK_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_4", "VBRK_MONITOR_P" ], [ "CLK_HROW_NE2A0_4", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_4", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_4", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_4", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_4", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_4", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_4", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_4", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_4", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_4", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_4", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_4", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_4", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_4", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_4", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_4", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_4", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_4", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_4", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_4", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_4", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_4", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_4", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_4", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_4", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_4", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_4", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_4", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_4", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_4", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_4", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_4", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_4", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_4", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_4", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_4", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_4", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_4", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_4", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_4", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_4", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_4", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_4", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_4", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_4", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_4", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_4", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_4", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_4", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_4", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_4", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_4", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_4", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_4", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_4", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_4", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_4", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_4", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_4", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_4", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_4", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_4", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_4", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_4", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_4", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_4", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_4", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_4", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_4", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_4", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_4", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_4", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_4", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_4", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_4", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_4", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_4", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_4", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_4", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_4", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, 1 ], "tile_types": [ "CLK_HROW_BOT_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_3", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_3", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_3", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_3", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_3", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_3", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_3", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_3", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_3", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_3", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_3", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_3", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_3", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_3", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_3", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_3", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_3", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_3", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_3", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_3", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_3", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_3", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_3", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_3", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_3", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_3", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_3", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_3", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_3", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_3", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_3", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_3", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_3", "VBRK_LH1" ], [ "CLK_HROW_LH2_3", "VBRK_LH2" ], [ "CLK_HROW_LH3_3", "VBRK_LH3" ], [ "CLK_HROW_LH4_3", "VBRK_LH4" ], [ "CLK_HROW_LH5_3", "VBRK_LH5" ], [ "CLK_HROW_LH6_3", "VBRK_LH6" ], [ "CLK_HROW_LH7_3", "VBRK_LH7" ], [ "CLK_HROW_LH8_3", "VBRK_LH8" ], [ "CLK_HROW_LH9_3", "VBRK_LH9" ], [ "CLK_HROW_LH10_3", "VBRK_LH10" ], [ "CLK_HROW_LH11_3", "VBRK_LH11" ], [ "CLK_HROW_LH12_3", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_3", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_3", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_3", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_3", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_3", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_3", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_3", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_3", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_3", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_3", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_3", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_3", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_3", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_3", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_3", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_3", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_3", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_3", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_3", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_3", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_3", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_3", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_3", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_3", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_3", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_3", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_3", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_3", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_3", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_3", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_3", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_3", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_3", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_3", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_3", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_3", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_3", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_3", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_3", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_3", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_3", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_3", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_3", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_3", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_3", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_3", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_3", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_3", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_3", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_3", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_3", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_3", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_3", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_3", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_3", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_3", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_3", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_3", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_3", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_3", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_3", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_3", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_3", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_3", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_3", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_3", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_3", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_3", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_3", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_3", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_3", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_3", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_3", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_3", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_3", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_3", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_3", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_3", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_3", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, 2 ], "tile_types": [ "CLK_HROW_BOT_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_2", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_2", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_2", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_2", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_2", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_2", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_2", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_2", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_2", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_2", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_2", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_2", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_2", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_2", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_2", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_2", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_2", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_2", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_2", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_2", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_2", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_2", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_2", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_2", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_2", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_2", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_2", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_2", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_2", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_2", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_2", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_2", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_2", "VBRK_LH1" ], [ "CLK_HROW_LH2_2", "VBRK_LH2" ], [ "CLK_HROW_LH3_2", "VBRK_LH3" ], [ "CLK_HROW_LH4_2", "VBRK_LH4" ], [ "CLK_HROW_LH5_2", "VBRK_LH5" ], [ "CLK_HROW_LH6_2", "VBRK_LH6" ], [ "CLK_HROW_LH7_2", "VBRK_LH7" ], [ "CLK_HROW_LH8_2", "VBRK_LH8" ], [ "CLK_HROW_LH9_2", "VBRK_LH9" ], [ "CLK_HROW_LH10_2", "VBRK_LH10" ], [ "CLK_HROW_LH11_2", "VBRK_LH11" ], [ "CLK_HROW_LH12_2", "VBRK_LH12" ], [ "CLK_HROW_MONITOR_N_2", "VBRK_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_2", "VBRK_MONITOR_P" ], [ "CLK_HROW_NE2A0_2", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_2", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_2", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_2", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_2", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_2", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_2", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_2", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_2", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_2", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_2", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_2", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_2", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_2", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_2", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_2", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_2", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_2", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_2", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_2", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_2", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_2", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_2", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_2", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_2", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_2", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_2", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_2", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_2", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_2", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_2", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_2", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_2", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_2", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_2", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_2", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_2", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_2", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_2", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_2", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_2", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_2", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_2", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_2", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_2", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_2", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_2", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_2", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_2", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_2", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_2", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_2", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_2", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_2", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_2", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_2", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_2", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_2", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_2", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_2", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_2", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_2", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_2", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_2", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_2", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_2", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_2", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_2", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_2", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_2", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_2", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_2", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_2", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_2", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_2", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_2", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_2", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_2", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_2", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_2", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, 3 ], "tile_types": [ "CLK_HROW_BOT_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_1", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_1", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_1", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_1", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_1", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_1", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_1", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_1", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_1", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_1", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_1", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_1", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_1", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_1", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_1", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_1", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_1", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_1", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_1", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_1", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_1", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_1", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_1", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_1", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_1", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_1", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_1", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_1", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_1", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_1", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_1", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_1", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_1", "VBRK_LH1" ], [ "CLK_HROW_LH2_1", "VBRK_LH2" ], [ "CLK_HROW_LH3_1", "VBRK_LH3" ], [ "CLK_HROW_LH4_1", "VBRK_LH4" ], [ "CLK_HROW_LH5_1", "VBRK_LH5" ], [ "CLK_HROW_LH6_1", "VBRK_LH6" ], [ "CLK_HROW_LH7_1", "VBRK_LH7" ], [ "CLK_HROW_LH8_1", "VBRK_LH8" ], [ "CLK_HROW_LH9_1", "VBRK_LH9" ], [ "CLK_HROW_LH10_1", "VBRK_LH10" ], [ "CLK_HROW_LH11_1", "VBRK_LH11" ], [ "CLK_HROW_LH12_1", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_1", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_1", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_1", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_1", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_1", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_1", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_1", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_1", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_1", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_1", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_1", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_1", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_1", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_1", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_1", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_1", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_1", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_1", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_1", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_1", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_1", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_1", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_1", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_1", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_1", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_1", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_1", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_1", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_1", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_1", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_1", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_1", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_1", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_1", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_1", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_1", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_1", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_1", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_1", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_1", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_1", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_1", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_1", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_1", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_1", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_1", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_1", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_1", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_1", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_1", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_1", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_1", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_1", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_1", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_1", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_1", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_1", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_1", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_1", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_1", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_1", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_1", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_1", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_1", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_1", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_1", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_1", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_1", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_1", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_1", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_1", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_1", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_1", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_1", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_1", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_1", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_1", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_1", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_1", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_1", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, 4 ], "tile_types": [ "CLK_HROW_BOT_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_0", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_0", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_0", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_0", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_0", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_0", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_0", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_0", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_0", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_0", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_0", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_0", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_0", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_0", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_0", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_0", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_0", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_0", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_0", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_0", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_0", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_0", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_0", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_0", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_0", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_0", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_0", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_0", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_0", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_0", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_0", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_0", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_0", "VBRK_LH1" ], [ "CLK_HROW_LH2_0", "VBRK_LH2" ], [ "CLK_HROW_LH3_0", "VBRK_LH3" ], [ "CLK_HROW_LH4_0", "VBRK_LH4" ], [ "CLK_HROW_LH5_0", "VBRK_LH5" ], [ "CLK_HROW_LH6_0", "VBRK_LH6" ], [ "CLK_HROW_LH7_0", "VBRK_LH7" ], [ "CLK_HROW_LH8_0", "VBRK_LH8" ], [ "CLK_HROW_LH9_0", "VBRK_LH9" ], [ "CLK_HROW_LH10_0", "VBRK_LH10" ], [ "CLK_HROW_LH11_0", "VBRK_LH11" ], [ "CLK_HROW_LH12_0", "VBRK_LH12" ], [ "CLK_HROW_MONITOR_N_0", "VBRK_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_0", "VBRK_MONITOR_P" ], [ "CLK_HROW_NE2A0_0", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_0", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_0", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_0", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_0", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_0", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_0", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_0", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_0", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_0", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_0", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_0", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_0", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_0", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_0", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_0", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_0", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_0", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_0", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_0", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_0", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_0", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_0", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_0", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_0", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_0", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_0", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_0", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_0", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_0", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_0", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_0", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_0", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_0", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_0", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_0", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_0", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_0", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_0", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_0", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_0", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_0", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_0", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_0", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_0", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_0", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_0", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_0", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_0", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_0", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_0", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_0", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_0", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_0", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_0", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_0", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_0", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_0", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_0", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_0", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_0", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_0", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_0", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_0", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_0", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_0", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_0", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_0", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_0", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_0", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_0", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_0", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_0", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_0", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_0", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_0", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_0", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_0", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_0", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_0", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "CLK_HROW_TOP_R", "HCLK_INT_INTERFACE" ], "wire_pairs": [ [ "CLK_HROW_CK_BUFHCLK_L0", "HCLK_INT_INTERFACE_CK_BUFHCLK0" ], [ "CLK_HROW_CK_BUFHCLK_L1", "HCLK_INT_INTERFACE_CK_BUFHCLK1" ], [ "CLK_HROW_CK_BUFHCLK_L2", "HCLK_INT_INTERFACE_CK_BUFHCLK2" ], [ "CLK_HROW_CK_BUFHCLK_L3", "HCLK_INT_INTERFACE_CK_BUFHCLK3" ], [ "CLK_HROW_CK_BUFHCLK_L4", "HCLK_INT_INTERFACE_CK_BUFHCLK4" ], [ "CLK_HROW_CK_BUFHCLK_L5", "HCLK_INT_INTERFACE_CK_BUFHCLK5" ], [ "CLK_HROW_CK_BUFHCLK_L6", "HCLK_INT_INTERFACE_CK_BUFHCLK6" ], [ "CLK_HROW_CK_BUFHCLK_L7", "HCLK_INT_INTERFACE_CK_BUFHCLK7" ], [ "CLK_HROW_CK_BUFHCLK_L8", "HCLK_INT_INTERFACE_CK_BUFHCLK8" ], [ "CLK_HROW_CK_BUFHCLK_L9", "HCLK_INT_INTERFACE_CK_BUFHCLK9" ], [ "CLK_HROW_CK_BUFHCLK_L10", "HCLK_INT_INTERFACE_CK_BUFHCLK10" ], [ "CLK_HROW_CK_BUFHCLK_L11", "HCLK_INT_INTERFACE_CK_BUFHCLK11" ], [ "CLK_HROW_CK_BUFRCLK_L0", "HCLK_INT_INTERFACE_CK_BUFRCLK0" ], [ "CLK_HROW_CK_BUFRCLK_L1", "HCLK_INT_INTERFACE_CK_BUFRCLK1" ], [ "CLK_HROW_CK_BUFRCLK_L2", "HCLK_INT_INTERFACE_CK_BUFRCLK2" ], [ "CLK_HROW_CK_BUFRCLK_L3", "HCLK_INT_INTERFACE_CK_BUFRCLK3" ], [ "CLK_HROW_CK_IN_L0", "HCLK_INT_INTERFACE_CK_IN0" ], [ "CLK_HROW_CK_IN_L1", "HCLK_INT_INTERFACE_CK_IN1" ], [ "CLK_HROW_CK_IN_L2", "HCLK_INT_INTERFACE_CK_IN2" ], [ "CLK_HROW_CK_IN_L3", "HCLK_INT_INTERFACE_CK_IN3" ], [ "CLK_HROW_CK_IN_L4", "HCLK_INT_INTERFACE_CK_IN4" ], [ "CLK_HROW_CK_IN_L5", "HCLK_INT_INTERFACE_CK_IN5" ], [ "CLK_HROW_CK_IN_L6", "HCLK_INT_INTERFACE_CK_IN6" ], [ "CLK_HROW_CK_IN_L7", "HCLK_INT_INTERFACE_CK_IN7" ], [ "CLK_HROW_CK_IN_L8", "HCLK_INT_INTERFACE_CK_IN8" ], [ "CLK_HROW_CK_IN_L9", "HCLK_INT_INTERFACE_CK_IN9" ], [ "CLK_HROW_CK_IN_L10", "HCLK_INT_INTERFACE_CK_IN10" ], [ "CLK_HROW_CK_IN_L11", "HCLK_INT_INTERFACE_CK_IN11" ], [ "CLK_HROW_CK_IN_L12", "HCLK_INT_INTERFACE_CK_IN12" ], [ "CLK_HROW_CK_IN_L13", "HCLK_INT_INTERFACE_CK_IN13" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLK_HROW_TOP_R", "HCLK_VBRK" ], "wire_pairs": [ [ "CLK_HROW_CK_BUFHCLK_R0", "HCLK_VBRK_CK_BUFHCLK0" ], [ "CLK_HROW_CK_BUFHCLK_R1", "HCLK_VBRK_CK_BUFHCLK1" ], [ "CLK_HROW_CK_BUFHCLK_R2", "HCLK_VBRK_CK_BUFHCLK2" ], [ "CLK_HROW_CK_BUFHCLK_R3", "HCLK_VBRK_CK_BUFHCLK3" ], [ "CLK_HROW_CK_BUFHCLK_R4", "HCLK_VBRK_CK_BUFHCLK4" ], [ "CLK_HROW_CK_BUFHCLK_R5", "HCLK_VBRK_CK_BUFHCLK5" ], [ "CLK_HROW_CK_BUFHCLK_R6", "HCLK_VBRK_CK_BUFHCLK6" ], [ "CLK_HROW_CK_BUFHCLK_R7", "HCLK_VBRK_CK_BUFHCLK7" ], [ "CLK_HROW_CK_BUFHCLK_R8", "HCLK_VBRK_CK_BUFHCLK8" ], [ "CLK_HROW_CK_BUFHCLK_R9", "HCLK_VBRK_CK_BUFHCLK9" ], [ "CLK_HROW_CK_BUFHCLK_R10", "HCLK_VBRK_CK_BUFHCLK10" ], [ "CLK_HROW_CK_BUFHCLK_R11", "HCLK_VBRK_CK_BUFHCLK11" ], [ "CLK_HROW_CK_BUFRCLK_R0", "HCLK_VBRK_CK_BUFRCLK0" ], [ "CLK_HROW_CK_BUFRCLK_R1", "HCLK_VBRK_CK_BUFRCLK1" ], [ "CLK_HROW_CK_BUFRCLK_R2", "HCLK_VBRK_CK_BUFRCLK2" ], [ "CLK_HROW_CK_BUFRCLK_R3", "HCLK_VBRK_CK_BUFRCLK3" ], [ "CLK_HROW_CK_IN_R0", "HCLK_VBRK_MUX_CLK0" ], [ "CLK_HROW_CK_IN_R1", "HCLK_VBRK_MUX_CLK1" ], [ "CLK_HROW_CK_IN_R2", "HCLK_VBRK_MUX_CLK2" ], [ "CLK_HROW_CK_IN_R3", "HCLK_VBRK_MUX_CLK3" ], [ "CLK_HROW_CK_IN_R4", "HCLK_VBRK_MUX_CLK4" ], [ "CLK_HROW_CK_IN_R5", "HCLK_VBRK_MUX_CLK5" ], [ "CLK_HROW_CK_IN_R6", "HCLK_VBRK_MUX_CLK6" ], [ "CLK_HROW_CK_IN_R7", "HCLK_VBRK_MUX_CLK7" ], [ "CLK_HROW_CK_IN_R8", "HCLK_VBRK_MUX_CLK8" ], [ "CLK_HROW_CK_IN_R9", "HCLK_VBRK_MUX_CLK9" ], [ "CLK_HROW_CK_IN_R10", "HCLK_VBRK_MUX_CLK10" ], [ "CLK_HROW_CK_IN_R11", "HCLK_VBRK_MUX_CLK11" ], [ "CLK_HROW_CK_IN_R12", "HCLK_VBRK_MUX_CLK12" ], [ "CLK_HROW_CK_IN_R13", "HCLK_VBRK_MUX_CLK13" ] ] }, { "grid_deltas": [ -1, -4 ], "tile_types": [ "CLK_HROW_TOP_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_7", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_7", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_7", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_7", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_7", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_7", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_7", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_7", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_7", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_7", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_7", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_7", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_7", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_7", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_7", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_7", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_7", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_7", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_7", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_7", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_7", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_7", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_7", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_7", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_7", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_7", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_7", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_7", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_7", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_7", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_7", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_7", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_7", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_7", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_7", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_7", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_7", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_7", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_7", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_7", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_7", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_7", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_7", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_7", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_7", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_7", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_7", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_7", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_7", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_7", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_7", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_7", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_7", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_7", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_7", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_7", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_7", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_7", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_7", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_7", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_7", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_7", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_7", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_7", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_7", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_7", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_7", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_7", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_7", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_7", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_7", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_7", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_7", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_7", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_7", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_7", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_7", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_7", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_7", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_7", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_7", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_7", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_7", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_7", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_7", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_7", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_7", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_7", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_7", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_7", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_7", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_7", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_7", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_7", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_7", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_7", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_7", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_7", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_7", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_7", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_7", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_7", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_7", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_7", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_7", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_7", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_7", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_7", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_7", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_7", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_7", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_7", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_7", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_7", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_7", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_7", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_7", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_7", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_7", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_7", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_7", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_7", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_7", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_7", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_7", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_7", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_7", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_7", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_7", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_7", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_7", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_7", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_7", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_7", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_7", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_7", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_7", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_7", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_7", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_7", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_7", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_7", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_7", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_7", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_7", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_7", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_7", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_7", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_7", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_7", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_7", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_7", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_7", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_7", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_7", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_7", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_7", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_7", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_7", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_7", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_7", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_7", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_7", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_7", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_7", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_7", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_7", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_7", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_7", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_7", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_7", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_7", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_7", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_7", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_7", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_7", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_7", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_7", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_7", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_7", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_7", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_7", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_7", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_7", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_7", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_7", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_7", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_7", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_7", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_7", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_7", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_7", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -3 ], "tile_types": [ "CLK_HROW_TOP_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_6", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_6", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_6", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_6", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_6", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_6", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_6", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_6", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_6", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_6", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_6", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_6", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_6", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_6", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_6", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_6", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_6", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_6", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_6", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_6", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_6", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_6", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_6", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_6", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_6", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_6", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_6", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_6", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_6", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_6", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_6", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_6", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_6", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_6", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_6", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_6", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_6", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_6", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_6", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_6", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_6", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_6", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_6", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_6", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_6", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_6", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_6", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_6", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_6", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_6", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_6", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_6", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_6", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_6", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_6", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_6", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_6", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_6", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_6", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_6", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_6", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_6", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_6", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_6", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_6", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_6", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_6", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_6", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_6", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_6", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_6", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_6", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_6", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_6", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_6", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_6", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_6", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_6", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_6", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_6", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_6", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_6", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_6", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_6", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_6", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_6", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_6", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_6", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_6", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_6", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_6", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_6", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_6", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_6", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_6", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_6", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_6", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_6", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_6", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_6", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_6", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_6", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_6", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_6", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_6", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_6", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_6", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_6", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_6", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_6", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_6", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_6", "INT_INTERFACE_LH12" ], [ "CLK_HROW_MONITOR_N_6", "INT_INTERFACE_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_6", "INT_INTERFACE_MONITOR_P" ], [ "CLK_HROW_NE2A0_6", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_6", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_6", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_6", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_6", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_6", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_6", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_6", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_6", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_6", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_6", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_6", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_6", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_6", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_6", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_6", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_6", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_6", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_6", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_6", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_6", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_6", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_6", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_6", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_6", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_6", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_6", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_6", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_6", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_6", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_6", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_6", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_6", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_6", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_6", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_6", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_6", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_6", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_6", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_6", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_6", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_6", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_6", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_6", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_6", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_6", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_6", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_6", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_6", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_6", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_6", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_6", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_6", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_6", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_6", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_6", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_6", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_6", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_6", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_6", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_6", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_6", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_6", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_6", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_6", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_6", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_6", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_6", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_6", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_6", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_6", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_6", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_6", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_6", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_6", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_6", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_6", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_6", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_6", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_6", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -2 ], "tile_types": [ "CLK_HROW_TOP_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_5", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_5", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_5", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_5", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_5", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_5", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_5", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_5", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_5", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_5", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_5", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_5", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_5", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_5", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_5", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_5", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_5", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_5", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_5", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_5", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_5", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_5", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_5", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_5", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_5", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_5", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_5", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_5", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_5", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_5", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_5", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_5", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_5", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_5", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_5", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_5", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_5", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_5", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_5", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_5", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_5", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_5", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_5", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_5", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_5", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_5", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_5", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_5", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_5", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_5", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_5", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_5", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_5", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_5", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_5", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_5", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_5", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_5", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_5", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_5", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_5", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_5", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_5", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_5", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_5", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_5", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_5", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_5", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_5", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_5", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_5", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_5", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_5", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_5", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_5", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_5", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_5", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_5", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_5", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_5", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_5", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_5", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_5", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_5", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_5", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_5", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_5", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_5", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_5", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_5", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_5", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_5", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_5", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_5", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_5", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_5", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_5", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_5", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_5", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_5", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_5", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_5", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_5", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_5", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_5", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_5", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_5", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_5", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_5", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_5", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_5", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_5", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_5", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_5", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_5", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_5", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_5", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_5", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_5", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_5", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_5", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_5", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_5", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_5", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_5", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_5", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_5", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_5", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_5", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_5", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_5", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_5", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_5", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_5", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_5", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_5", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_5", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_5", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_5", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_5", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_5", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_5", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_5", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_5", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_5", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_5", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_5", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_5", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_5", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_5", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_5", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_5", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_5", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_5", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_5", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_5", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_5", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_5", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_5", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_5", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_5", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_5", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_5", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_5", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_5", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_5", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_5", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_5", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_5", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_5", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_5", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_5", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_5", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_5", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_5", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_5", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_5", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_5", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_5", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_5", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_5", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_5", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_5", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_5", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_5", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_5", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_5", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_5", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_5", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_5", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_5", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_5", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -1 ], "tile_types": [ "CLK_HROW_TOP_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_4", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_4", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_4", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_4", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_4", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_4", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_4", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_4", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_4", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_4", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_4", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_4", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_4", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_4", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_4", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_4", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_4", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_4", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_4", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_4", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_4", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_4", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_4", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_4", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_4", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_4", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_4", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_4", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_4", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_4", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_4", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_4", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_4", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_4", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_4", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_4", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_4", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_4", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_4", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_4", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_4", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_4", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_4", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_4", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_4", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_4", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_4", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_4", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_4", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_4", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_4", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_4", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_4", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_4", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_4", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_4", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_4", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_4", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_4", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_4", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_4", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_4", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_4", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_4", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_4", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_4", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_4", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_4", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_4", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_4", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_4", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_4", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_4", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_4", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_4", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_4", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_4", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_4", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_4", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_4", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_4", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_4", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_4", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_4", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_4", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_4", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_4", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_4", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_4", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_4", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_4", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_4", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_4", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_4", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_4", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_4", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_4", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_4", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_4", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_4", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_4", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_4", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_4", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_4", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_4", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_4", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_4", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_4", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_4", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_4", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_4", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_4", "INT_INTERFACE_LH12" ], [ "CLK_HROW_MONITOR_N_4", "INT_INTERFACE_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_4", "INT_INTERFACE_MONITOR_P" ], [ "CLK_HROW_NE2A0_4", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_4", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_4", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_4", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_4", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_4", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_4", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_4", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_4", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_4", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_4", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_4", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_4", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_4", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_4", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_4", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_4", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_4", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_4", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_4", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_4", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_4", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_4", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_4", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_4", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_4", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_4", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_4", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_4", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_4", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_4", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_4", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_4", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_4", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_4", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_4", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_4", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_4", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_4", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_4", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_4", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_4", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_4", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_4", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_4", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_4", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_4", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_4", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_4", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_4", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_4", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_4", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_4", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_4", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_4", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_4", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_4", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_4", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_4", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_4", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_4", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_4", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_4", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_4", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_4", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_4", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_4", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_4", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_4", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_4", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_4", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_4", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_4", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_4", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_4", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_4", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_4", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_4", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_4", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_4", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, 1 ], "tile_types": [ "CLK_HROW_TOP_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_3", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_3", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_3", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_3", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_3", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_3", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_3", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_3", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_3", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_3", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_3", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_3", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_3", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_3", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_3", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_3", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_3", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_3", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_3", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_3", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_3", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_3", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_3", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_3", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_3", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_3", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_3", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_3", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_3", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_3", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_3", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_3", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_3", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_3", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_3", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_3", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_3", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_3", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_3", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_3", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_3", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_3", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_3", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_3", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_3", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_3", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_3", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_3", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_3", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_3", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_3", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_3", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_3", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_3", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_3", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_3", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_3", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_3", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_3", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_3", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_3", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_3", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_3", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_3", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_3", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_3", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_3", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_3", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_3", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_3", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_3", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_3", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_3", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_3", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_3", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_3", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_3", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_3", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_3", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_3", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_3", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_3", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_3", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_3", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_3", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_3", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_3", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_3", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_3", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_3", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_3", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_3", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_3", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_3", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_3", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_3", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_3", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_3", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_3", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_3", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_3", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_3", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_3", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_3", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_3", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_3", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_3", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_3", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_3", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_3", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_3", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_3", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_3", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_3", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_3", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_3", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_3", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_3", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_3", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_3", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_3", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_3", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_3", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_3", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_3", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_3", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_3", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_3", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_3", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_3", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_3", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_3", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_3", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_3", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_3", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_3", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_3", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_3", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_3", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_3", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_3", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_3", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_3", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_3", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_3", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_3", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_3", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_3", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_3", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_3", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_3", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_3", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_3", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_3", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_3", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_3", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_3", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_3", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_3", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_3", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_3", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_3", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_3", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_3", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_3", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_3", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_3", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_3", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_3", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_3", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_3", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_3", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_3", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_3", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_3", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_3", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_3", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_3", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_3", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_3", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_3", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_3", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_3", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_3", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_3", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_3", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_3", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_3", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_3", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_3", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_3", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_3", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, 2 ], "tile_types": [ "CLK_HROW_TOP_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_2", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_2", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_2", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_2", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_2", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_2", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_2", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_2", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_2", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_2", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_2", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_2", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_2", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_2", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_2", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_2", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_2", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_2", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_2", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_2", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_2", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_2", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_2", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_2", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_2", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_2", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_2", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_2", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_2", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_2", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_2", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_2", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_2", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_2", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_2", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_2", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_2", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_2", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_2", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_2", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_2", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_2", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_2", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_2", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_2", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_2", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_2", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_2", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_2", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_2", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_2", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_2", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_2", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_2", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_2", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_2", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_2", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_2", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_2", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_2", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_2", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_2", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_2", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_2", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_2", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_2", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_2", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_2", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_2", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_2", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_2", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_2", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_2", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_2", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_2", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_2", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_2", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_2", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_2", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_2", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_2", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_2", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_2", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_2", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_2", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_2", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_2", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_2", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_2", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_2", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_2", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_2", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_2", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_2", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_2", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_2", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_2", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_2", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_2", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_2", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_2", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_2", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_2", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_2", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_2", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_2", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_2", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_2", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_2", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_2", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_2", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_2", "INT_INTERFACE_LH12" ], [ "CLK_HROW_MONITOR_N_2", "INT_INTERFACE_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_2", "INT_INTERFACE_MONITOR_P" ], [ "CLK_HROW_NE2A0_2", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_2", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_2", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_2", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_2", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_2", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_2", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_2", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_2", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_2", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_2", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_2", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_2", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_2", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_2", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_2", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_2", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_2", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_2", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_2", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_2", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_2", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_2", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_2", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_2", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_2", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_2", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_2", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_2", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_2", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_2", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_2", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_2", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_2", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_2", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_2", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_2", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_2", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_2", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_2", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_2", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_2", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_2", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_2", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_2", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_2", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_2", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_2", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_2", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_2", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_2", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_2", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_2", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_2", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_2", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_2", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_2", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_2", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_2", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_2", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_2", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_2", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_2", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_2", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_2", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_2", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_2", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_2", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_2", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_2", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_2", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_2", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_2", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_2", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_2", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_2", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_2", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_2", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_2", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_2", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, 3 ], "tile_types": [ "CLK_HROW_TOP_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_1", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_1", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_1", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_1", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_1", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_1", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_1", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_1", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_1", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_1", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_1", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_1", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_1", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_1", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_1", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_1", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_1", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_1", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_1", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_1", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_1", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_1", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_1", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_1", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_1", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_1", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_1", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_1", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_1", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_1", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_1", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_1", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_1", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_1", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_1", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_1", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_1", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_1", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_1", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_1", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_1", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_1", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_1", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_1", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_1", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_1", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_1", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_1", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_1", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_1", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_1", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_1", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_1", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_1", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_1", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_1", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_1", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_1", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_1", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_1", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_1", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_1", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_1", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_1", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_1", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_1", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_1", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_1", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_1", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_1", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_1", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_1", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_1", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_1", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_1", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_1", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_1", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_1", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_1", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_1", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_1", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_1", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_1", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_1", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_1", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_1", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_1", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_1", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_1", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_1", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_1", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_1", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_1", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_1", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_1", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_1", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_1", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_1", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_1", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_1", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_1", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_1", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_1", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_1", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_1", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_1", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_1", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_1", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_1", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_1", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_1", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_1", "INT_INTERFACE_LH12" ], [ "CLK_HROW_NE2A0_1", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_1", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_1", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_1", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_1", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_1", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_1", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_1", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_1", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_1", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_1", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_1", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_1", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_1", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_1", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_1", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_1", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_1", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_1", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_1", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_1", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_1", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_1", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_1", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_1", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_1", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_1", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_1", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_1", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_1", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_1", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_1", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_1", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_1", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_1", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_1", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_1", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_1", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_1", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_1", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_1", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_1", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_1", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_1", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_1", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_1", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_1", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_1", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_1", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_1", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_1", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_1", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_1", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_1", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_1", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_1", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_1", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_1", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_1", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_1", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_1", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_1", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_1", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_1", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_1", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_1", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_1", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_1", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_1", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_1", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_1", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_1", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_1", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_1", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_1", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_1", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_1", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_1", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_1", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_1", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, 4 ], "tile_types": [ "CLK_HROW_TOP_R", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_HROW_BYP0_0", "INT_INTERFACE_BYP0" ], [ "CLK_HROW_BYP1_0", "INT_INTERFACE_BYP1" ], [ "CLK_HROW_BYP2_0", "INT_INTERFACE_BYP2" ], [ "CLK_HROW_BYP3_0", "INT_INTERFACE_BYP3" ], [ "CLK_HROW_BYP4_0", "INT_INTERFACE_BYP4" ], [ "CLK_HROW_BYP5_0", "INT_INTERFACE_BYP5" ], [ "CLK_HROW_BYP6_0", "INT_INTERFACE_BYP6" ], [ "CLK_HROW_BYP7_0", "INT_INTERFACE_BYP7" ], [ "CLK_HROW_CLK0_0", "INT_INTERFACE_CLK0" ], [ "CLK_HROW_CLK1_0", "INT_INTERFACE_CLK1" ], [ "CLK_HROW_CTRL0_0", "INT_INTERFACE_CTRL0" ], [ "CLK_HROW_CTRL1_0", "INT_INTERFACE_CTRL1" ], [ "CLK_HROW_EE2A0_0", "INT_INTERFACE_EE2A0" ], [ "CLK_HROW_EE2A1_0", "INT_INTERFACE_EE2A1" ], [ "CLK_HROW_EE2A2_0", "INT_INTERFACE_EE2A2" ], [ "CLK_HROW_EE2A3_0", "INT_INTERFACE_EE2A3" ], [ "CLK_HROW_EE2BEG0_0", "INT_INTERFACE_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_0", "INT_INTERFACE_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_0", "INT_INTERFACE_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_0", "INT_INTERFACE_EE2BEG3" ], [ "CLK_HROW_EE4A0_0", "INT_INTERFACE_EE4A0" ], [ "CLK_HROW_EE4A1_0", "INT_INTERFACE_EE4A1" ], [ "CLK_HROW_EE4A2_0", "INT_INTERFACE_EE4A2" ], [ "CLK_HROW_EE4A3_0", "INT_INTERFACE_EE4A3" ], [ "CLK_HROW_EE4B0_0", "INT_INTERFACE_EE4B0" ], [ "CLK_HROW_EE4B1_0", "INT_INTERFACE_EE4B1" ], [ "CLK_HROW_EE4B2_0", "INT_INTERFACE_EE4B2" ], [ "CLK_HROW_EE4B3_0", "INT_INTERFACE_EE4B3" ], [ "CLK_HROW_EE4BEG0_0", "INT_INTERFACE_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_0", "INT_INTERFACE_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_0", "INT_INTERFACE_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_0", "INT_INTERFACE_EE4BEG3" ], [ "CLK_HROW_EE4C0_0", "INT_INTERFACE_EE4C0" ], [ "CLK_HROW_EE4C1_0", "INT_INTERFACE_EE4C1" ], [ "CLK_HROW_EE4C2_0", "INT_INTERFACE_EE4C2" ], [ "CLK_HROW_EE4C3_0", "INT_INTERFACE_EE4C3" ], [ "CLK_HROW_EL1BEG0_0", "INT_INTERFACE_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_0", "INT_INTERFACE_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_0", "INT_INTERFACE_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_0", "INT_INTERFACE_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_0", "INT_INTERFACE_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_0", "INT_INTERFACE_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_0", "INT_INTERFACE_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_0", "INT_INTERFACE_ER1BEG3" ], [ "CLK_HROW_FAN0_0", "INT_INTERFACE_FAN0" ], [ "CLK_HROW_FAN1_0", "INT_INTERFACE_FAN1" ], [ "CLK_HROW_FAN2_0", "INT_INTERFACE_FAN2" ], [ "CLK_HROW_FAN3_0", "INT_INTERFACE_FAN3" ], [ "CLK_HROW_FAN4_0", "INT_INTERFACE_FAN4" ], [ "CLK_HROW_FAN5_0", "INT_INTERFACE_FAN5" ], [ "CLK_HROW_FAN6_0", "INT_INTERFACE_FAN6" ], [ "CLK_HROW_FAN7_0", "INT_INTERFACE_FAN7" ], [ "CLK_HROW_IMUX0_0", "INT_INTERFACE_IMUX0" ], [ "CLK_HROW_IMUX1_0", "INT_INTERFACE_IMUX1" ], [ "CLK_HROW_IMUX2_0", "INT_INTERFACE_IMUX2" ], [ "CLK_HROW_IMUX3_0", "INT_INTERFACE_IMUX3" ], [ "CLK_HROW_IMUX4_0", "INT_INTERFACE_IMUX4" ], [ "CLK_HROW_IMUX5_0", "INT_INTERFACE_IMUX5" ], [ "CLK_HROW_IMUX6_0", "INT_INTERFACE_IMUX6" ], [ "CLK_HROW_IMUX7_0", "INT_INTERFACE_IMUX7" ], [ "CLK_HROW_IMUX8_0", "INT_INTERFACE_IMUX8" ], [ "CLK_HROW_IMUX9_0", "INT_INTERFACE_IMUX9" ], [ "CLK_HROW_IMUX10_0", "INT_INTERFACE_IMUX10" ], [ "CLK_HROW_IMUX11_0", "INT_INTERFACE_IMUX11" ], [ "CLK_HROW_IMUX12_0", "INT_INTERFACE_IMUX12" ], [ "CLK_HROW_IMUX13_0", "INT_INTERFACE_IMUX13" ], [ "CLK_HROW_IMUX14_0", "INT_INTERFACE_IMUX14" ], [ "CLK_HROW_IMUX15_0", "INT_INTERFACE_IMUX15" ], [ "CLK_HROW_IMUX16_0", "INT_INTERFACE_IMUX16" ], [ "CLK_HROW_IMUX17_0", "INT_INTERFACE_IMUX17" ], [ "CLK_HROW_IMUX18_0", "INT_INTERFACE_IMUX18" ], [ "CLK_HROW_IMUX19_0", "INT_INTERFACE_IMUX19" ], [ "CLK_HROW_IMUX20_0", "INT_INTERFACE_IMUX20" ], [ "CLK_HROW_IMUX21_0", "INT_INTERFACE_IMUX21" ], [ "CLK_HROW_IMUX22_0", "INT_INTERFACE_IMUX22" ], [ "CLK_HROW_IMUX23_0", "INT_INTERFACE_IMUX23" ], [ "CLK_HROW_IMUX24_0", "INT_INTERFACE_IMUX24" ], [ "CLK_HROW_IMUX25_0", "INT_INTERFACE_IMUX25" ], [ "CLK_HROW_IMUX26_0", "INT_INTERFACE_IMUX26" ], [ "CLK_HROW_IMUX27_0", "INT_INTERFACE_IMUX27" ], [ "CLK_HROW_IMUX28_0", "INT_INTERFACE_IMUX28" ], [ "CLK_HROW_IMUX29_0", "INT_INTERFACE_IMUX29" ], [ "CLK_HROW_IMUX30_0", "INT_INTERFACE_IMUX30" ], [ "CLK_HROW_IMUX31_0", "INT_INTERFACE_IMUX31" ], [ "CLK_HROW_IMUX32_0", "INT_INTERFACE_IMUX32" ], [ "CLK_HROW_IMUX33_0", "INT_INTERFACE_IMUX33" ], [ "CLK_HROW_IMUX34_0", "INT_INTERFACE_IMUX34" ], [ "CLK_HROW_IMUX35_0", "INT_INTERFACE_IMUX35" ], [ "CLK_HROW_IMUX36_0", "INT_INTERFACE_IMUX36" ], [ "CLK_HROW_IMUX37_0", "INT_INTERFACE_IMUX37" ], [ "CLK_HROW_IMUX38_0", "INT_INTERFACE_IMUX38" ], [ "CLK_HROW_IMUX39_0", "INT_INTERFACE_IMUX39" ], [ "CLK_HROW_IMUX40_0", "INT_INTERFACE_IMUX40" ], [ "CLK_HROW_IMUX41_0", "INT_INTERFACE_IMUX41" ], [ "CLK_HROW_IMUX42_0", "INT_INTERFACE_IMUX42" ], [ "CLK_HROW_IMUX43_0", "INT_INTERFACE_IMUX43" ], [ "CLK_HROW_IMUX44_0", "INT_INTERFACE_IMUX44" ], [ "CLK_HROW_IMUX45_0", "INT_INTERFACE_IMUX45" ], [ "CLK_HROW_IMUX46_0", "INT_INTERFACE_IMUX46" ], [ "CLK_HROW_IMUX47_0", "INT_INTERFACE_IMUX47" ], [ "CLK_HROW_LH1_0", "INT_INTERFACE_LH1" ], [ "CLK_HROW_LH2_0", "INT_INTERFACE_LH2" ], [ "CLK_HROW_LH3_0", "INT_INTERFACE_LH3" ], [ "CLK_HROW_LH4_0", "INT_INTERFACE_LH4" ], [ "CLK_HROW_LH5_0", "INT_INTERFACE_LH5" ], [ "CLK_HROW_LH6_0", "INT_INTERFACE_LH6" ], [ "CLK_HROW_LH7_0", "INT_INTERFACE_LH7" ], [ "CLK_HROW_LH8_0", "INT_INTERFACE_LH8" ], [ "CLK_HROW_LH9_0", "INT_INTERFACE_LH9" ], [ "CLK_HROW_LH10_0", "INT_INTERFACE_LH10" ], [ "CLK_HROW_LH11_0", "INT_INTERFACE_LH11" ], [ "CLK_HROW_LH12_0", "INT_INTERFACE_LH12" ], [ "CLK_HROW_MONITOR_N_0", "INT_INTERFACE_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_0", "INT_INTERFACE_MONITOR_P" ], [ "CLK_HROW_NE2A0_0", "INT_INTERFACE_NE2A0" ], [ "CLK_HROW_NE2A1_0", "INT_INTERFACE_NE2A1" ], [ "CLK_HROW_NE2A2_0", "INT_INTERFACE_NE2A2" ], [ "CLK_HROW_NE2A3_0", "INT_INTERFACE_NE2A3" ], [ "CLK_HROW_NE4BEG0_0", "INT_INTERFACE_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_0", "INT_INTERFACE_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_0", "INT_INTERFACE_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_0", "INT_INTERFACE_NE4BEG3" ], [ "CLK_HROW_NE4C0_0", "INT_INTERFACE_NE4C0" ], [ "CLK_HROW_NE4C1_0", "INT_INTERFACE_NE4C1" ], [ "CLK_HROW_NE4C2_0", "INT_INTERFACE_NE4C2" ], [ "CLK_HROW_NE4C3_0", "INT_INTERFACE_NE4C3" ], [ "CLK_HROW_NW2A0_0", "INT_INTERFACE_NW2A0" ], [ "CLK_HROW_NW2A1_0", "INT_INTERFACE_NW2A1" ], [ "CLK_HROW_NW2A2_0", "INT_INTERFACE_NW2A2" ], [ "CLK_HROW_NW2A3_0", "INT_INTERFACE_NW2A3" ], [ "CLK_HROW_NW4A0_0", "INT_INTERFACE_NW4A0" ], [ "CLK_HROW_NW4A1_0", "INT_INTERFACE_NW4A1" ], [ "CLK_HROW_NW4A2_0", "INT_INTERFACE_NW4A2" ], [ "CLK_HROW_NW4A3_0", "INT_INTERFACE_NW4A3" ], [ "CLK_HROW_NW4END0_0", "INT_INTERFACE_NW4END0" ], [ "CLK_HROW_NW4END1_0", "INT_INTERFACE_NW4END1" ], [ "CLK_HROW_NW4END2_0", "INT_INTERFACE_NW4END2" ], [ "CLK_HROW_NW4END3_0", "INT_INTERFACE_NW4END3" ], [ "CLK_HROW_SE2A0_0", "INT_INTERFACE_SE2A0" ], [ "CLK_HROW_SE2A1_0", "INT_INTERFACE_SE2A1" ], [ "CLK_HROW_SE2A2_0", "INT_INTERFACE_SE2A2" ], [ "CLK_HROW_SE2A3_0", "INT_INTERFACE_SE2A3" ], [ "CLK_HROW_SE4BEG0_0", "INT_INTERFACE_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_0", "INT_INTERFACE_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_0", "INT_INTERFACE_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_0", "INT_INTERFACE_SE4BEG3" ], [ "CLK_HROW_SE4C0_0", "INT_INTERFACE_SE4C0" ], [ "CLK_HROW_SE4C1_0", "INT_INTERFACE_SE4C1" ], [ "CLK_HROW_SE4C2_0", "INT_INTERFACE_SE4C2" ], [ "CLK_HROW_SE4C3_0", "INT_INTERFACE_SE4C3" ], [ "CLK_HROW_SW2A0_0", "INT_INTERFACE_SW2A0" ], [ "CLK_HROW_SW2A1_0", "INT_INTERFACE_SW2A1" ], [ "CLK_HROW_SW2A2_0", "INT_INTERFACE_SW2A2" ], [ "CLK_HROW_SW2A3_0", "INT_INTERFACE_SW2A3" ], [ "CLK_HROW_SW4A0_0", "INT_INTERFACE_SW4A0" ], [ "CLK_HROW_SW4A1_0", "INT_INTERFACE_SW4A1" ], [ "CLK_HROW_SW4A2_0", "INT_INTERFACE_SW4A2" ], [ "CLK_HROW_SW4A3_0", "INT_INTERFACE_SW4A3" ], [ "CLK_HROW_SW4END0_0", "INT_INTERFACE_SW4END0" ], [ "CLK_HROW_SW4END1_0", "INT_INTERFACE_SW4END1" ], [ "CLK_HROW_SW4END2_0", "INT_INTERFACE_SW4END2" ], [ "CLK_HROW_SW4END3_0", "INT_INTERFACE_SW4END3" ], [ "CLK_HROW_WL1END0_0", "INT_INTERFACE_WL1END0" ], [ "CLK_HROW_WL1END1_0", "INT_INTERFACE_WL1END1" ], [ "CLK_HROW_WL1END2_0", "INT_INTERFACE_WL1END2" ], [ "CLK_HROW_WL1END3_0", "INT_INTERFACE_WL1END3" ], [ "CLK_HROW_WR1END0_0", "INT_INTERFACE_WR1END0" ], [ "CLK_HROW_WR1END1_0", "INT_INTERFACE_WR1END1" ], [ "CLK_HROW_WR1END2_0", "INT_INTERFACE_WR1END2" ], [ "CLK_HROW_WR1END3_0", "INT_INTERFACE_WR1END3" ], [ "CLK_HROW_WW2A0_0", "INT_INTERFACE_WW2A0" ], [ "CLK_HROW_WW2A1_0", "INT_INTERFACE_WW2A1" ], [ "CLK_HROW_WW2A2_0", "INT_INTERFACE_WW2A2" ], [ "CLK_HROW_WW2A3_0", "INT_INTERFACE_WW2A3" ], [ "CLK_HROW_WW2END0_0", "INT_INTERFACE_WW2END0" ], [ "CLK_HROW_WW2END1_0", "INT_INTERFACE_WW2END1" ], [ "CLK_HROW_WW2END2_0", "INT_INTERFACE_WW2END2" ], [ "CLK_HROW_WW2END3_0", "INT_INTERFACE_WW2END3" ], [ "CLK_HROW_WW4A0_0", "INT_INTERFACE_WW4A0" ], [ "CLK_HROW_WW4A1_0", "INT_INTERFACE_WW4A1" ], [ "CLK_HROW_WW4A2_0", "INT_INTERFACE_WW4A2" ], [ "CLK_HROW_WW4A3_0", "INT_INTERFACE_WW4A3" ], [ "CLK_HROW_WW4B0_0", "INT_INTERFACE_WW4B0" ], [ "CLK_HROW_WW4B1_0", "INT_INTERFACE_WW4B1" ], [ "CLK_HROW_WW4B2_0", "INT_INTERFACE_WW4B2" ], [ "CLK_HROW_WW4B3_0", "INT_INTERFACE_WW4B3" ], [ "CLK_HROW_WW4C0_0", "INT_INTERFACE_WW4C0" ], [ "CLK_HROW_WW4C1_0", "INT_INTERFACE_WW4C1" ], [ "CLK_HROW_WW4C2_0", "INT_INTERFACE_WW4C2" ], [ "CLK_HROW_WW4C3_0", "INT_INTERFACE_WW4C3" ], [ "CLK_HROW_WW4END0_0", "INT_INTERFACE_WW4END0" ], [ "CLK_HROW_WW4END1_0", "INT_INTERFACE_WW4END1" ], [ "CLK_HROW_WW4END2_0", "INT_INTERFACE_WW4END2" ], [ "CLK_HROW_WW4END3_0", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ 1, -4 ], "tile_types": [ "CLK_HROW_TOP_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_7", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_7", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_7", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_7", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_7", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_7", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_7", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_7", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_7", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_7", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_7", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_7", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_7", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_7", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_7", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_7", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_7", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_7", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_7", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_7", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_7", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_7", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_7", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_7", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_7", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_7", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_7", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_7", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_7", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_7", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_7", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_7", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_7", "VBRK_LH1" ], [ "CLK_HROW_LH2_7", "VBRK_LH2" ], [ "CLK_HROW_LH3_7", "VBRK_LH3" ], [ "CLK_HROW_LH4_7", "VBRK_LH4" ], [ "CLK_HROW_LH5_7", "VBRK_LH5" ], [ "CLK_HROW_LH6_7", "VBRK_LH6" ], [ "CLK_HROW_LH7_7", "VBRK_LH7" ], [ "CLK_HROW_LH8_7", "VBRK_LH8" ], [ "CLK_HROW_LH9_7", "VBRK_LH9" ], [ "CLK_HROW_LH10_7", "VBRK_LH10" ], [ "CLK_HROW_LH11_7", "VBRK_LH11" ], [ "CLK_HROW_LH12_7", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_7", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_7", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_7", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_7", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_7", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_7", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_7", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_7", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_7", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_7", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_7", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_7", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_7", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_7", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_7", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_7", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_7", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_7", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_7", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_7", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_7", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_7", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_7", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_7", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_7", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_7", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_7", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_7", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_7", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_7", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_7", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_7", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_7", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_7", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_7", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_7", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_7", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_7", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_7", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_7", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_7", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_7", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_7", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_7", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_7", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_7", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_7", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_7", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_7", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_7", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_7", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_7", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_7", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_7", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_7", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_7", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_7", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_7", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_7", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_7", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_7", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_7", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_7", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_7", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_7", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_7", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_7", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_7", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_7", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_7", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_7", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_7", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_7", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_7", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_7", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_7", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_7", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_7", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_7", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_7", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -3 ], "tile_types": [ "CLK_HROW_TOP_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_6", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_6", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_6", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_6", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_6", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_6", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_6", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_6", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_6", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_6", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_6", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_6", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_6", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_6", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_6", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_6", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_6", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_6", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_6", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_6", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_6", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_6", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_6", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_6", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_6", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_6", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_6", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_6", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_6", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_6", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_6", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_6", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_6", "VBRK_LH1" ], [ "CLK_HROW_LH2_6", "VBRK_LH2" ], [ "CLK_HROW_LH3_6", "VBRK_LH3" ], [ "CLK_HROW_LH4_6", "VBRK_LH4" ], [ "CLK_HROW_LH5_6", "VBRK_LH5" ], [ "CLK_HROW_LH6_6", "VBRK_LH6" ], [ "CLK_HROW_LH7_6", "VBRK_LH7" ], [ "CLK_HROW_LH8_6", "VBRK_LH8" ], [ "CLK_HROW_LH9_6", "VBRK_LH9" ], [ "CLK_HROW_LH10_6", "VBRK_LH10" ], [ "CLK_HROW_LH11_6", "VBRK_LH11" ], [ "CLK_HROW_LH12_6", "VBRK_LH12" ], [ "CLK_HROW_MONITOR_N_6", "VBRK_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_6", "VBRK_MONITOR_P" ], [ "CLK_HROW_NE2A0_6", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_6", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_6", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_6", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_6", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_6", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_6", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_6", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_6", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_6", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_6", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_6", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_6", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_6", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_6", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_6", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_6", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_6", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_6", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_6", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_6", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_6", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_6", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_6", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_6", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_6", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_6", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_6", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_6", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_6", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_6", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_6", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_6", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_6", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_6", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_6", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_6", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_6", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_6", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_6", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_6", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_6", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_6", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_6", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_6", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_6", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_6", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_6", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_6", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_6", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_6", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_6", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_6", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_6", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_6", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_6", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_6", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_6", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_6", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_6", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_6", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_6", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_6", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_6", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_6", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_6", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_6", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_6", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_6", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_6", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_6", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_6", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_6", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_6", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_6", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_6", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_6", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_6", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_6", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_6", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -2 ], "tile_types": [ "CLK_HROW_TOP_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_5", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_5", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_5", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_5", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_5", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_5", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_5", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_5", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_5", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_5", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_5", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_5", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_5", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_5", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_5", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_5", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_5", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_5", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_5", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_5", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_5", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_5", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_5", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_5", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_5", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_5", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_5", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_5", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_5", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_5", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_5", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_5", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_5", "VBRK_LH1" ], [ "CLK_HROW_LH2_5", "VBRK_LH2" ], [ "CLK_HROW_LH3_5", "VBRK_LH3" ], [ "CLK_HROW_LH4_5", "VBRK_LH4" ], [ "CLK_HROW_LH5_5", "VBRK_LH5" ], [ "CLK_HROW_LH6_5", "VBRK_LH6" ], [ "CLK_HROW_LH7_5", "VBRK_LH7" ], [ "CLK_HROW_LH8_5", "VBRK_LH8" ], [ "CLK_HROW_LH9_5", "VBRK_LH9" ], [ "CLK_HROW_LH10_5", "VBRK_LH10" ], [ "CLK_HROW_LH11_5", "VBRK_LH11" ], [ "CLK_HROW_LH12_5", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_5", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_5", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_5", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_5", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_5", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_5", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_5", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_5", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_5", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_5", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_5", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_5", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_5", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_5", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_5", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_5", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_5", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_5", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_5", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_5", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_5", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_5", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_5", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_5", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_5", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_5", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_5", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_5", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_5", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_5", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_5", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_5", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_5", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_5", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_5", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_5", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_5", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_5", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_5", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_5", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_5", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_5", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_5", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_5", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_5", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_5", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_5", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_5", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_5", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_5", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_5", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_5", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_5", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_5", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_5", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_5", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_5", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_5", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_5", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_5", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_5", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_5", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_5", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_5", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_5", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_5", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_5", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_5", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_5", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_5", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_5", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_5", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_5", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_5", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_5", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_5", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_5", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_5", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_5", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_5", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -1 ], "tile_types": [ "CLK_HROW_TOP_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_4", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_4", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_4", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_4", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_4", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_4", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_4", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_4", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_4", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_4", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_4", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_4", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_4", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_4", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_4", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_4", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_4", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_4", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_4", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_4", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_4", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_4", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_4", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_4", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_4", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_4", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_4", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_4", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_4", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_4", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_4", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_4", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_4", "VBRK_LH1" ], [ "CLK_HROW_LH2_4", "VBRK_LH2" ], [ "CLK_HROW_LH3_4", "VBRK_LH3" ], [ "CLK_HROW_LH4_4", "VBRK_LH4" ], [ "CLK_HROW_LH5_4", "VBRK_LH5" ], [ "CLK_HROW_LH6_4", "VBRK_LH6" ], [ "CLK_HROW_LH7_4", "VBRK_LH7" ], [ "CLK_HROW_LH8_4", "VBRK_LH8" ], [ "CLK_HROW_LH9_4", "VBRK_LH9" ], [ "CLK_HROW_LH10_4", "VBRK_LH10" ], [ "CLK_HROW_LH11_4", "VBRK_LH11" ], [ "CLK_HROW_LH12_4", "VBRK_LH12" ], [ "CLK_HROW_MONITOR_N_4", "VBRK_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_4", "VBRK_MONITOR_P" ], [ "CLK_HROW_NE2A0_4", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_4", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_4", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_4", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_4", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_4", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_4", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_4", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_4", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_4", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_4", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_4", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_4", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_4", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_4", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_4", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_4", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_4", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_4", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_4", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_4", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_4", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_4", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_4", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_4", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_4", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_4", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_4", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_4", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_4", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_4", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_4", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_4", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_4", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_4", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_4", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_4", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_4", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_4", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_4", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_4", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_4", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_4", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_4", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_4", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_4", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_4", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_4", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_4", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_4", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_4", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_4", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_4", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_4", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_4", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_4", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_4", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_4", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_4", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_4", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_4", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_4", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_4", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_4", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_4", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_4", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_4", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_4", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_4", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_4", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_4", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_4", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_4", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_4", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_4", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_4", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_4", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_4", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_4", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_4", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, 1 ], "tile_types": [ "CLK_HROW_TOP_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_3", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_3", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_3", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_3", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_3", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_3", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_3", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_3", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_3", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_3", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_3", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_3", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_3", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_3", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_3", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_3", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_3", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_3", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_3", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_3", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_3", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_3", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_3", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_3", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_3", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_3", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_3", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_3", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_3", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_3", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_3", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_3", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_3", "VBRK_LH1" ], [ "CLK_HROW_LH2_3", "VBRK_LH2" ], [ "CLK_HROW_LH3_3", "VBRK_LH3" ], [ "CLK_HROW_LH4_3", "VBRK_LH4" ], [ "CLK_HROW_LH5_3", "VBRK_LH5" ], [ "CLK_HROW_LH6_3", "VBRK_LH6" ], [ "CLK_HROW_LH7_3", "VBRK_LH7" ], [ "CLK_HROW_LH8_3", "VBRK_LH8" ], [ "CLK_HROW_LH9_3", "VBRK_LH9" ], [ "CLK_HROW_LH10_3", "VBRK_LH10" ], [ "CLK_HROW_LH11_3", "VBRK_LH11" ], [ "CLK_HROW_LH12_3", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_3", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_3", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_3", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_3", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_3", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_3", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_3", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_3", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_3", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_3", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_3", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_3", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_3", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_3", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_3", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_3", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_3", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_3", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_3", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_3", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_3", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_3", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_3", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_3", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_3", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_3", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_3", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_3", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_3", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_3", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_3", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_3", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_3", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_3", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_3", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_3", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_3", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_3", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_3", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_3", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_3", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_3", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_3", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_3", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_3", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_3", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_3", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_3", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_3", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_3", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_3", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_3", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_3", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_3", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_3", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_3", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_3", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_3", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_3", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_3", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_3", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_3", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_3", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_3", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_3", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_3", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_3", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_3", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_3", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_3", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_3", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_3", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_3", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_3", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_3", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_3", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_3", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_3", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_3", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, 2 ], "tile_types": [ "CLK_HROW_TOP_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_2", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_2", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_2", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_2", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_2", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_2", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_2", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_2", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_2", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_2", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_2", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_2", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_2", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_2", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_2", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_2", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_2", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_2", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_2", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_2", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_2", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_2", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_2", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_2", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_2", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_2", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_2", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_2", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_2", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_2", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_2", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_2", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_2", "VBRK_LH1" ], [ "CLK_HROW_LH2_2", "VBRK_LH2" ], [ "CLK_HROW_LH3_2", "VBRK_LH3" ], [ "CLK_HROW_LH4_2", "VBRK_LH4" ], [ "CLK_HROW_LH5_2", "VBRK_LH5" ], [ "CLK_HROW_LH6_2", "VBRK_LH6" ], [ "CLK_HROW_LH7_2", "VBRK_LH7" ], [ "CLK_HROW_LH8_2", "VBRK_LH8" ], [ "CLK_HROW_LH9_2", "VBRK_LH9" ], [ "CLK_HROW_LH10_2", "VBRK_LH10" ], [ "CLK_HROW_LH11_2", "VBRK_LH11" ], [ "CLK_HROW_LH12_2", "VBRK_LH12" ], [ "CLK_HROW_MONITOR_N_2", "VBRK_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_2", "VBRK_MONITOR_P" ], [ "CLK_HROW_NE2A0_2", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_2", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_2", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_2", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_2", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_2", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_2", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_2", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_2", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_2", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_2", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_2", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_2", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_2", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_2", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_2", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_2", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_2", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_2", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_2", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_2", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_2", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_2", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_2", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_2", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_2", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_2", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_2", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_2", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_2", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_2", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_2", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_2", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_2", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_2", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_2", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_2", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_2", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_2", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_2", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_2", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_2", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_2", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_2", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_2", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_2", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_2", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_2", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_2", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_2", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_2", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_2", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_2", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_2", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_2", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_2", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_2", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_2", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_2", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_2", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_2", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_2", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_2", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_2", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_2", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_2", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_2", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_2", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_2", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_2", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_2", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_2", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_2", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_2", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_2", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_2", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_2", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_2", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_2", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_2", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, 3 ], "tile_types": [ "CLK_HROW_TOP_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_1", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_1", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_1", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_1", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_1", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_1", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_1", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_1", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_1", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_1", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_1", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_1", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_1", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_1", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_1", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_1", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_1", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_1", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_1", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_1", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_1", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_1", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_1", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_1", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_1", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_1", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_1", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_1", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_1", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_1", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_1", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_1", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_1", "VBRK_LH1" ], [ "CLK_HROW_LH2_1", "VBRK_LH2" ], [ "CLK_HROW_LH3_1", "VBRK_LH3" ], [ "CLK_HROW_LH4_1", "VBRK_LH4" ], [ "CLK_HROW_LH5_1", "VBRK_LH5" ], [ "CLK_HROW_LH6_1", "VBRK_LH6" ], [ "CLK_HROW_LH7_1", "VBRK_LH7" ], [ "CLK_HROW_LH8_1", "VBRK_LH8" ], [ "CLK_HROW_LH9_1", "VBRK_LH9" ], [ "CLK_HROW_LH10_1", "VBRK_LH10" ], [ "CLK_HROW_LH11_1", "VBRK_LH11" ], [ "CLK_HROW_LH12_1", "VBRK_LH12" ], [ "CLK_HROW_NE2A0_1", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_1", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_1", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_1", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_1", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_1", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_1", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_1", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_1", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_1", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_1", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_1", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_1", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_1", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_1", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_1", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_1", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_1", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_1", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_1", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_1", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_1", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_1", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_1", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_1", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_1", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_1", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_1", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_1", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_1", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_1", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_1", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_1", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_1", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_1", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_1", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_1", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_1", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_1", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_1", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_1", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_1", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_1", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_1", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_1", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_1", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_1", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_1", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_1", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_1", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_1", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_1", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_1", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_1", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_1", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_1", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_1", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_1", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_1", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_1", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_1", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_1", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_1", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_1", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_1", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_1", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_1", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_1", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_1", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_1", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_1", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_1", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_1", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_1", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_1", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_1", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_1", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_1", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_1", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_1", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, 4 ], "tile_types": [ "CLK_HROW_TOP_R", "VBRK" ], "wire_pairs": [ [ "CLK_HROW_EE2A0_0", "VBRK_EE2A0" ], [ "CLK_HROW_EE2A1_0", "VBRK_EE2A1" ], [ "CLK_HROW_EE2A2_0", "VBRK_EE2A2" ], [ "CLK_HROW_EE2A3_0", "VBRK_EE2A3" ], [ "CLK_HROW_EE2BEG0_0", "VBRK_EE2BEG0" ], [ "CLK_HROW_EE2BEG1_0", "VBRK_EE2BEG1" ], [ "CLK_HROW_EE2BEG2_0", "VBRK_EE2BEG2" ], [ "CLK_HROW_EE2BEG3_0", "VBRK_EE2BEG3" ], [ "CLK_HROW_EE4A0_0", "VBRK_EE4A0" ], [ "CLK_HROW_EE4A1_0", "VBRK_EE4A1" ], [ "CLK_HROW_EE4A2_0", "VBRK_EE4A2" ], [ "CLK_HROW_EE4A3_0", "VBRK_EE4A3" ], [ "CLK_HROW_EE4B0_0", "VBRK_EE4B0" ], [ "CLK_HROW_EE4B1_0", "VBRK_EE4B1" ], [ "CLK_HROW_EE4B2_0", "VBRK_EE4B2" ], [ "CLK_HROW_EE4B3_0", "VBRK_EE4B3" ], [ "CLK_HROW_EE4BEG0_0", "VBRK_EE4BEG0" ], [ "CLK_HROW_EE4BEG1_0", "VBRK_EE4BEG1" ], [ "CLK_HROW_EE4BEG2_0", "VBRK_EE4BEG2" ], [ "CLK_HROW_EE4BEG3_0", "VBRK_EE4BEG3" ], [ "CLK_HROW_EE4C0_0", "VBRK_EE4C0" ], [ "CLK_HROW_EE4C1_0", "VBRK_EE4C1" ], [ "CLK_HROW_EE4C2_0", "VBRK_EE4C2" ], [ "CLK_HROW_EE4C3_0", "VBRK_EE4C3" ], [ "CLK_HROW_EL1BEG0_0", "VBRK_EL1BEG0" ], [ "CLK_HROW_EL1BEG1_0", "VBRK_EL1BEG1" ], [ "CLK_HROW_EL1BEG2_0", "VBRK_EL1BEG2" ], [ "CLK_HROW_EL1BEG3_0", "VBRK_EL1BEG3" ], [ "CLK_HROW_ER1BEG0_0", "VBRK_ER1BEG0" ], [ "CLK_HROW_ER1BEG1_0", "VBRK_ER1BEG1" ], [ "CLK_HROW_ER1BEG2_0", "VBRK_ER1BEG2" ], [ "CLK_HROW_ER1BEG3_0", "VBRK_ER1BEG3" ], [ "CLK_HROW_LH1_0", "VBRK_LH1" ], [ "CLK_HROW_LH2_0", "VBRK_LH2" ], [ "CLK_HROW_LH3_0", "VBRK_LH3" ], [ "CLK_HROW_LH4_0", "VBRK_LH4" ], [ "CLK_HROW_LH5_0", "VBRK_LH5" ], [ "CLK_HROW_LH6_0", "VBRK_LH6" ], [ "CLK_HROW_LH7_0", "VBRK_LH7" ], [ "CLK_HROW_LH8_0", "VBRK_LH8" ], [ "CLK_HROW_LH9_0", "VBRK_LH9" ], [ "CLK_HROW_LH10_0", "VBRK_LH10" ], [ "CLK_HROW_LH11_0", "VBRK_LH11" ], [ "CLK_HROW_LH12_0", "VBRK_LH12" ], [ "CLK_HROW_MONITOR_N_0", "VBRK_MONITOR_N" ], [ "CLK_HROW_MONITOR_P_0", "VBRK_MONITOR_P" ], [ "CLK_HROW_NE2A0_0", "VBRK_NE2A0" ], [ "CLK_HROW_NE2A1_0", "VBRK_NE2A1" ], [ "CLK_HROW_NE2A2_0", "VBRK_NE2A2" ], [ "CLK_HROW_NE2A3_0", "VBRK_NE2A3" ], [ "CLK_HROW_NE4BEG0_0", "VBRK_NE4BEG0" ], [ "CLK_HROW_NE4BEG1_0", "VBRK_NE4BEG1" ], [ "CLK_HROW_NE4BEG2_0", "VBRK_NE4BEG2" ], [ "CLK_HROW_NE4BEG3_0", "VBRK_NE4BEG3" ], [ "CLK_HROW_NE4C0_0", "VBRK_NE4C0" ], [ "CLK_HROW_NE4C1_0", "VBRK_NE4C1" ], [ "CLK_HROW_NE4C2_0", "VBRK_NE4C2" ], [ "CLK_HROW_NE4C3_0", "VBRK_NE4C3" ], [ "CLK_HROW_NW2A0_0", "VBRK_NW2A0" ], [ "CLK_HROW_NW2A1_0", "VBRK_NW2A1" ], [ "CLK_HROW_NW2A2_0", "VBRK_NW2A2" ], [ "CLK_HROW_NW2A3_0", "VBRK_NW2A3" ], [ "CLK_HROW_NW4A0_0", "VBRK_NW4A0" ], [ "CLK_HROW_NW4A1_0", "VBRK_NW4A1" ], [ "CLK_HROW_NW4A2_0", "VBRK_NW4A2" ], [ "CLK_HROW_NW4A3_0", "VBRK_NW4A3" ], [ "CLK_HROW_NW4END0_0", "VBRK_NW4END0" ], [ "CLK_HROW_NW4END1_0", "VBRK_NW4END1" ], [ "CLK_HROW_NW4END2_0", "VBRK_NW4END2" ], [ "CLK_HROW_NW4END3_0", "VBRK_NW4END3" ], [ "CLK_HROW_SE2A0_0", "VBRK_SE2A0" ], [ "CLK_HROW_SE2A1_0", "VBRK_SE2A1" ], [ "CLK_HROW_SE2A2_0", "VBRK_SE2A2" ], [ "CLK_HROW_SE2A3_0", "VBRK_SE2A3" ], [ "CLK_HROW_SE4BEG0_0", "VBRK_SE4BEG0" ], [ "CLK_HROW_SE4BEG1_0", "VBRK_SE4BEG1" ], [ "CLK_HROW_SE4BEG2_0", "VBRK_SE4BEG2" ], [ "CLK_HROW_SE4BEG3_0", "VBRK_SE4BEG3" ], [ "CLK_HROW_SE4C0_0", "VBRK_SE4C0" ], [ "CLK_HROW_SE4C1_0", "VBRK_SE4C1" ], [ "CLK_HROW_SE4C2_0", "VBRK_SE4C2" ], [ "CLK_HROW_SE4C3_0", "VBRK_SE4C3" ], [ "CLK_HROW_SW2A0_0", "VBRK_SW2A0" ], [ "CLK_HROW_SW2A1_0", "VBRK_SW2A1" ], [ "CLK_HROW_SW2A2_0", "VBRK_SW2A2" ], [ "CLK_HROW_SW2A3_0", "VBRK_SW2A3" ], [ "CLK_HROW_SW4A0_0", "VBRK_SW4A0" ], [ "CLK_HROW_SW4A1_0", "VBRK_SW4A1" ], [ "CLK_HROW_SW4A2_0", "VBRK_SW4A2" ], [ "CLK_HROW_SW4A3_0", "VBRK_SW4A3" ], [ "CLK_HROW_SW4END0_0", "VBRK_SW4END0" ], [ "CLK_HROW_SW4END1_0", "VBRK_SW4END1" ], [ "CLK_HROW_SW4END2_0", "VBRK_SW4END2" ], [ "CLK_HROW_SW4END3_0", "VBRK_SW4END3" ], [ "CLK_HROW_WL1END0_0", "VBRK_WL1END0" ], [ "CLK_HROW_WL1END1_0", "VBRK_WL1END1" ], [ "CLK_HROW_WL1END2_0", "VBRK_WL1END2" ], [ "CLK_HROW_WL1END3_0", "VBRK_WL1END3" ], [ "CLK_HROW_WR1END0_0", "VBRK_WR1END0" ], [ "CLK_HROW_WR1END1_0", "VBRK_WR1END1" ], [ "CLK_HROW_WR1END2_0", "VBRK_WR1END2" ], [ "CLK_HROW_WR1END3_0", "VBRK_WR1END3" ], [ "CLK_HROW_WW2A0_0", "VBRK_WW2A0" ], [ "CLK_HROW_WW2A1_0", "VBRK_WW2A1" ], [ "CLK_HROW_WW2A2_0", "VBRK_WW2A2" ], [ "CLK_HROW_WW2A3_0", "VBRK_WW2A3" ], [ "CLK_HROW_WW2END0_0", "VBRK_WW2END0" ], [ "CLK_HROW_WW2END1_0", "VBRK_WW2END1" ], [ "CLK_HROW_WW2END2_0", "VBRK_WW2END2" ], [ "CLK_HROW_WW2END3_0", "VBRK_WW2END3" ], [ "CLK_HROW_WW4A0_0", "VBRK_WW4A0" ], [ "CLK_HROW_WW4A1_0", "VBRK_WW4A1" ], [ "CLK_HROW_WW4A2_0", "VBRK_WW4A2" ], [ "CLK_HROW_WW4A3_0", "VBRK_WW4A3" ], [ "CLK_HROW_WW4B0_0", "VBRK_WW4B0" ], [ "CLK_HROW_WW4B1_0", "VBRK_WW4B1" ], [ "CLK_HROW_WW4B2_0", "VBRK_WW4B2" ], [ "CLK_HROW_WW4B3_0", "VBRK_WW4B3" ], [ "CLK_HROW_WW4C0_0", "VBRK_WW4C0" ], [ "CLK_HROW_WW4C1_0", "VBRK_WW4C1" ], [ "CLK_HROW_WW4C2_0", "VBRK_WW4C2" ], [ "CLK_HROW_WW4C3_0", "VBRK_WW4C3" ], [ "CLK_HROW_WW4END0_0", "VBRK_WW4END0" ], [ "CLK_HROW_WW4END1_0", "VBRK_WW4END1" ], [ "CLK_HROW_WW4END2_0", "VBRK_WW4END2" ], [ "CLK_HROW_WW4END3_0", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "CLK_MTBF2", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_FEED_EE2A0", "INT_INTERFACE_EE2A0" ], [ "CLK_FEED_EE2A1", "INT_INTERFACE_EE2A1" ], [ "CLK_FEED_EE2A2", "INT_INTERFACE_EE2A2" ], [ "CLK_FEED_EE2A3", "INT_INTERFACE_EE2A3" ], [ "CLK_FEED_EE2BEG0", "INT_INTERFACE_EE2BEG0" ], [ "CLK_FEED_EE2BEG1", "INT_INTERFACE_EE2BEG1" ], [ "CLK_FEED_EE2BEG2", "INT_INTERFACE_EE2BEG2" ], [ "CLK_FEED_EE2BEG3", "INT_INTERFACE_EE2BEG3" ], [ "CLK_FEED_EE4A0", "INT_INTERFACE_EE4A0" ], [ "CLK_FEED_EE4A1", "INT_INTERFACE_EE4A1" ], [ "CLK_FEED_EE4A2", "INT_INTERFACE_EE4A2" ], [ "CLK_FEED_EE4A3", "INT_INTERFACE_EE4A3" ], [ "CLK_FEED_EE4B0", "INT_INTERFACE_EE4B0" ], [ "CLK_FEED_EE4B1", "INT_INTERFACE_EE4B1" ], [ "CLK_FEED_EE4B2", "INT_INTERFACE_EE4B2" ], [ "CLK_FEED_EE4B3", "INT_INTERFACE_EE4B3" ], [ "CLK_FEED_EE4BEG0", "INT_INTERFACE_EE4BEG0" ], [ "CLK_FEED_EE4BEG1", "INT_INTERFACE_EE4BEG1" ], [ "CLK_FEED_EE4BEG2", "INT_INTERFACE_EE4BEG2" ], [ "CLK_FEED_EE4BEG3", "INT_INTERFACE_EE4BEG3" ], [ "CLK_FEED_EE4C0", "INT_INTERFACE_EE4C0" ], [ "CLK_FEED_EE4C1", "INT_INTERFACE_EE4C1" ], [ "CLK_FEED_EE4C2", "INT_INTERFACE_EE4C2" ], [ "CLK_FEED_EE4C3", "INT_INTERFACE_EE4C3" ], [ "CLK_FEED_EL1BEG0", "INT_INTERFACE_EL1BEG0" ], [ "CLK_FEED_EL1BEG1", "INT_INTERFACE_EL1BEG1" ], [ "CLK_FEED_EL1BEG2", "INT_INTERFACE_EL1BEG2" ], [ "CLK_FEED_EL1BEG3", "INT_INTERFACE_EL1BEG3" ], [ "CLK_FEED_ER1BEG0", "INT_INTERFACE_ER1BEG0" ], [ "CLK_FEED_ER1BEG1", "INT_INTERFACE_ER1BEG1" ], [ "CLK_FEED_ER1BEG2", "INT_INTERFACE_ER1BEG2" ], [ "CLK_FEED_ER1BEG3", "INT_INTERFACE_ER1BEG3" ], [ "CLK_FEED_LH1", "INT_INTERFACE_LH1" ], [ "CLK_FEED_LH2", "INT_INTERFACE_LH2" ], [ "CLK_FEED_LH3", "INT_INTERFACE_LH3" ], [ "CLK_FEED_LH4", "INT_INTERFACE_LH4" ], [ "CLK_FEED_LH5", "INT_INTERFACE_LH5" ], [ "CLK_FEED_LH6", "INT_INTERFACE_LH6" ], [ "CLK_FEED_LH7", "INT_INTERFACE_LH7" ], [ "CLK_FEED_LH8", "INT_INTERFACE_LH8" ], [ "CLK_FEED_LH9", "INT_INTERFACE_LH9" ], [ "CLK_FEED_LH10", "INT_INTERFACE_LH10" ], [ "CLK_FEED_LH11", "INT_INTERFACE_LH11" ], [ "CLK_FEED_LH12", "INT_INTERFACE_LH12" ], [ "CLK_FEED_MONITOR_N", "INT_INTERFACE_MONITOR_N" ], [ "CLK_FEED_MONITOR_P", "INT_INTERFACE_MONITOR_P" ], [ "CLK_FEED_NE2A0", "INT_INTERFACE_NE2A0" ], [ "CLK_FEED_NE2A1", "INT_INTERFACE_NE2A1" ], [ "CLK_FEED_NE2A2", "INT_INTERFACE_NE2A2" ], [ "CLK_FEED_NE2A3", "INT_INTERFACE_NE2A3" ], [ "CLK_FEED_NE4BEG0", "INT_INTERFACE_NE4BEG0" ], [ "CLK_FEED_NE4BEG1", "INT_INTERFACE_NE4BEG1" ], [ "CLK_FEED_NE4BEG2", "INT_INTERFACE_NE4BEG2" ], [ "CLK_FEED_NE4BEG3", "INT_INTERFACE_NE4BEG3" ], [ "CLK_FEED_NE4C0", "INT_INTERFACE_NE4C0" ], [ "CLK_FEED_NE4C1", "INT_INTERFACE_NE4C1" ], [ "CLK_FEED_NE4C2", "INT_INTERFACE_NE4C2" ], [ "CLK_FEED_NE4C3", "INT_INTERFACE_NE4C3" ], [ "CLK_FEED_NW2A0", "INT_INTERFACE_NW2A0" ], [ "CLK_FEED_NW2A1", "INT_INTERFACE_NW2A1" ], [ "CLK_FEED_NW2A2", "INT_INTERFACE_NW2A2" ], [ "CLK_FEED_NW2A3", "INT_INTERFACE_NW2A3" ], [ "CLK_FEED_NW4A0", "INT_INTERFACE_NW4A0" ], [ "CLK_FEED_NW4A1", "INT_INTERFACE_NW4A1" ], [ "CLK_FEED_NW4A2", "INT_INTERFACE_NW4A2" ], [ "CLK_FEED_NW4A3", "INT_INTERFACE_NW4A3" ], [ "CLK_FEED_NW4END0", "INT_INTERFACE_NW4END0" ], [ "CLK_FEED_NW4END1", "INT_INTERFACE_NW4END1" ], [ "CLK_FEED_NW4END2", "INT_INTERFACE_NW4END2" ], [ "CLK_FEED_NW4END3", "INT_INTERFACE_NW4END3" ], [ "CLK_FEED_SE2A0", "INT_INTERFACE_SE2A0" ], [ "CLK_FEED_SE2A1", "INT_INTERFACE_SE2A1" ], [ "CLK_FEED_SE2A2", "INT_INTERFACE_SE2A2" ], [ "CLK_FEED_SE2A3", "INT_INTERFACE_SE2A3" ], [ "CLK_FEED_SE4BEG0", "INT_INTERFACE_SE4BEG0" ], [ "CLK_FEED_SE4BEG1", "INT_INTERFACE_SE4BEG1" ], [ "CLK_FEED_SE4BEG2", "INT_INTERFACE_SE4BEG2" ], [ "CLK_FEED_SE4BEG3", "INT_INTERFACE_SE4BEG3" ], [ "CLK_FEED_SE4C0", "INT_INTERFACE_SE4C0" ], [ "CLK_FEED_SE4C1", "INT_INTERFACE_SE4C1" ], [ "CLK_FEED_SE4C2", "INT_INTERFACE_SE4C2" ], [ "CLK_FEED_SE4C3", "INT_INTERFACE_SE4C3" ], [ "CLK_FEED_SW2A0", "INT_INTERFACE_SW2A0" ], [ "CLK_FEED_SW2A1", "INT_INTERFACE_SW2A1" ], [ "CLK_FEED_SW2A2", "INT_INTERFACE_SW2A2" ], [ "CLK_FEED_SW2A3", "INT_INTERFACE_SW2A3" ], [ "CLK_FEED_SW4A0", "INT_INTERFACE_SW4A0" ], [ "CLK_FEED_SW4A1", "INT_INTERFACE_SW4A1" ], [ "CLK_FEED_SW4A2", "INT_INTERFACE_SW4A2" ], [ "CLK_FEED_SW4A3", "INT_INTERFACE_SW4A3" ], [ "CLK_FEED_SW4END0", "INT_INTERFACE_SW4END0" ], [ "CLK_FEED_SW4END1", "INT_INTERFACE_SW4END1" ], [ "CLK_FEED_SW4END2", "INT_INTERFACE_SW4END2" ], [ "CLK_FEED_SW4END3", "INT_INTERFACE_SW4END3" ], [ "CLK_FEED_WL1END0", "INT_INTERFACE_WL1END0" ], [ "CLK_FEED_WL1END1", "INT_INTERFACE_WL1END1" ], [ "CLK_FEED_WL1END2", "INT_INTERFACE_WL1END2" ], [ "CLK_FEED_WL1END3", "INT_INTERFACE_WL1END3" ], [ "CLK_FEED_WR1END0", "INT_INTERFACE_WR1END0" ], [ "CLK_FEED_WR1END1", "INT_INTERFACE_WR1END1" ], [ "CLK_FEED_WR1END2", "INT_INTERFACE_WR1END2" ], [ "CLK_FEED_WR1END3", "INT_INTERFACE_WR1END3" ], [ "CLK_FEED_WW2A0", "INT_INTERFACE_WW2A0" ], [ "CLK_FEED_WW2A1", "INT_INTERFACE_WW2A1" ], [ "CLK_FEED_WW2A2", "INT_INTERFACE_WW2A2" ], [ "CLK_FEED_WW2A3", "INT_INTERFACE_WW2A3" ], [ "CLK_FEED_WW2END0", "INT_INTERFACE_WW2END0" ], [ "CLK_FEED_WW2END1", "INT_INTERFACE_WW2END1" ], [ "CLK_FEED_WW2END2", "INT_INTERFACE_WW2END2" ], [ "CLK_FEED_WW2END3", "INT_INTERFACE_WW2END3" ], [ "CLK_FEED_WW4A0", "INT_INTERFACE_WW4A0" ], [ "CLK_FEED_WW4A1", "INT_INTERFACE_WW4A1" ], [ "CLK_FEED_WW4A2", "INT_INTERFACE_WW4A2" ], [ "CLK_FEED_WW4A3", "INT_INTERFACE_WW4A3" ], [ "CLK_FEED_WW4B0", "INT_INTERFACE_WW4B0" ], [ "CLK_FEED_WW4B1", "INT_INTERFACE_WW4B1" ], [ "CLK_FEED_WW4B2", "INT_INTERFACE_WW4B2" ], [ "CLK_FEED_WW4B3", "INT_INTERFACE_WW4B3" ], [ "CLK_FEED_WW4C0", "INT_INTERFACE_WW4C0" ], [ "CLK_FEED_WW4C1", "INT_INTERFACE_WW4C1" ], [ "CLK_FEED_WW4C2", "INT_INTERFACE_WW4C2" ], [ "CLK_FEED_WW4C3", "INT_INTERFACE_WW4C3" ], [ "CLK_FEED_WW4END0", "INT_INTERFACE_WW4END0" ], [ "CLK_FEED_WW4END1", "INT_INTERFACE_WW4END1" ], [ "CLK_FEED_WW4END2", "INT_INTERFACE_WW4END2" ], [ "CLK_FEED_WW4END3", "INT_INTERFACE_WW4END3" ], [ "CLK_PMV_BYP0_0", "INT_INTERFACE_BYP0" ], [ "CLK_PMV_BYP1_0", "INT_INTERFACE_BYP1" ], [ "CLK_PMV_BYP2_0", "INT_INTERFACE_BYP2" ], [ "CLK_PMV_BYP3_0", "INT_INTERFACE_BYP3" ], [ "CLK_PMV_BYP4_0", "INT_INTERFACE_BYP4" ], [ "CLK_PMV_BYP5_0", "INT_INTERFACE_BYP5" ], [ "CLK_PMV_BYP6_0", "INT_INTERFACE_BYP6" ], [ "CLK_PMV_BYP7_0", "INT_INTERFACE_BYP7" ], [ "CLK_PMV_CLK0_0", "INT_INTERFACE_CLK0" ], [ "CLK_PMV_CLK1_0", "INT_INTERFACE_CLK1" ], [ "CLK_PMV_CTRL0_0", "INT_INTERFACE_CTRL0" ], [ "CLK_PMV_CTRL1_0", "INT_INTERFACE_CTRL1" ], [ "CLK_PMV_FAN0_0", "INT_INTERFACE_FAN0" ], [ "CLK_PMV_FAN1_0", "INT_INTERFACE_FAN1" ], [ "CLK_PMV_FAN2_0", "INT_INTERFACE_FAN2" ], [ "CLK_PMV_FAN3_0", "INT_INTERFACE_FAN3" ], [ "CLK_PMV_FAN4_0", "INT_INTERFACE_FAN4" ], [ "CLK_PMV_FAN5_0", "INT_INTERFACE_FAN5" ], [ "CLK_PMV_FAN6_0", "INT_INTERFACE_FAN6" ], [ "CLK_PMV_FAN7_0", "INT_INTERFACE_FAN7" ], [ "CLK_PMV_IMUX0_0", "INT_INTERFACE_IMUX0" ], [ "CLK_PMV_IMUX1_0", "INT_INTERFACE_IMUX1" ], [ "CLK_PMV_IMUX2_0", "INT_INTERFACE_IMUX2" ], [ "CLK_PMV_IMUX3_0", "INT_INTERFACE_IMUX3" ], [ "CLK_PMV_IMUX4_0", "INT_INTERFACE_IMUX4" ], [ "CLK_PMV_IMUX5_0", "INT_INTERFACE_IMUX5" ], [ "CLK_PMV_IMUX6_0", "INT_INTERFACE_IMUX6" ], [ "CLK_PMV_IMUX7_0", "INT_INTERFACE_IMUX7" ], [ "CLK_PMV_IMUX8_0", "INT_INTERFACE_IMUX8" ], [ "CLK_PMV_IMUX9_0", "INT_INTERFACE_IMUX9" ], [ "CLK_PMV_IMUX10_0", "INT_INTERFACE_IMUX10" ], [ "CLK_PMV_IMUX11_0", "INT_INTERFACE_IMUX11" ], [ "CLK_PMV_IMUX12_0", "INT_INTERFACE_IMUX12" ], [ "CLK_PMV_IMUX13_0", "INT_INTERFACE_IMUX13" ], [ "CLK_PMV_IMUX14_0", "INT_INTERFACE_IMUX14" ], [ "CLK_PMV_IMUX15_0", "INT_INTERFACE_IMUX15" ], [ "CLK_PMV_IMUX16_0", "INT_INTERFACE_IMUX16" ], [ "CLK_PMV_IMUX17_0", "INT_INTERFACE_IMUX17" ], [ "CLK_PMV_IMUX18_0", "INT_INTERFACE_IMUX18" ], [ "CLK_PMV_IMUX19_0", "INT_INTERFACE_IMUX19" ], [ "CLK_PMV_IMUX20_0", "INT_INTERFACE_IMUX20" ], [ "CLK_PMV_IMUX21_0", "INT_INTERFACE_IMUX21" ], [ "CLK_PMV_IMUX22_0", "INT_INTERFACE_IMUX22" ], [ "CLK_PMV_IMUX23_0", "INT_INTERFACE_IMUX23" ], [ "CLK_PMV_IMUX24_0", "INT_INTERFACE_IMUX24" ], [ "CLK_PMV_IMUX25_0", "INT_INTERFACE_IMUX25" ], [ "CLK_PMV_IMUX26_0", "INT_INTERFACE_IMUX26" ], [ "CLK_PMV_IMUX27_0", "INT_INTERFACE_IMUX27" ], [ "CLK_PMV_IMUX28_0", "INT_INTERFACE_IMUX28" ], [ "CLK_PMV_IMUX29_0", "INT_INTERFACE_IMUX29" ], [ "CLK_PMV_IMUX30_0", "INT_INTERFACE_IMUX30" ], [ "CLK_PMV_IMUX31_0", "INT_INTERFACE_IMUX31" ], [ "CLK_PMV_IMUX32_0", "INT_INTERFACE_IMUX32" ], [ "CLK_PMV_IMUX33_0", "INT_INTERFACE_IMUX33" ], [ "CLK_PMV_IMUX34_0", "INT_INTERFACE_IMUX34" ], [ "CLK_PMV_IMUX35_0", "INT_INTERFACE_IMUX35" ], [ "CLK_PMV_IMUX36_0", "INT_INTERFACE_IMUX36" ], [ "CLK_PMV_IMUX37_0", "INT_INTERFACE_IMUX37" ], [ "CLK_PMV_IMUX38_0", "INT_INTERFACE_IMUX38" ], [ "CLK_PMV_IMUX39_0", "INT_INTERFACE_IMUX39" ], [ "CLK_PMV_IMUX40_0", "INT_INTERFACE_IMUX40" ], [ "CLK_PMV_IMUX41_0", "INT_INTERFACE_IMUX41" ], [ "CLK_PMV_IMUX42_0", "INT_INTERFACE_IMUX42" ], [ "CLK_PMV_IMUX43_0", "INT_INTERFACE_IMUX43" ], [ "CLK_PMV_IMUX44_0", "INT_INTERFACE_IMUX44" ], [ "CLK_PMV_IMUX45_0", "INT_INTERFACE_IMUX45" ], [ "CLK_PMV_IMUX46_0", "INT_INTERFACE_IMUX46" ], [ "CLK_PMV_IMUX47_0", "INT_INTERFACE_IMUX47" ], [ "CLK_PMV_LOGIC_OUTS2_0", "INT_INTERFACE_LOGIC_OUTS_B2" ], [ "CLK_PMV_LOGIC_OUTS5_0", "INT_INTERFACE_LOGIC_OUTS_B5" ], [ "CLK_PMV_LOGIC_OUTS6_0", "INT_INTERFACE_LOGIC_OUTS_B6" ], [ "CLK_PMV_LOGIC_OUTS9_0", "INT_INTERFACE_LOGIC_OUTS_B9" ], [ "CLK_PMV_LOGIC_OUTS10_0", "INT_INTERFACE_LOGIC_OUTS_B10" ], [ "CLK_PMV_LOGIC_OUTS14_0", "INT_INTERFACE_LOGIC_OUTS_B14" ], [ "CLK_PMV_LOGIC_OUTS16_0", "INT_INTERFACE_LOGIC_OUTS_B16" ], [ "CLK_PMV_LOGIC_OUTS19_0", "INT_INTERFACE_LOGIC_OUTS_B19" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLK_MTBF2", "VBRK" ], "wire_pairs": [ [ "CLK_FEED_EE2A0", "VBRK_EE2A0" ], [ "CLK_FEED_EE2A1", "VBRK_EE2A1" ], [ "CLK_FEED_EE2A2", "VBRK_EE2A2" ], [ "CLK_FEED_EE2A3", "VBRK_EE2A3" ], [ "CLK_FEED_EE2BEG0", "VBRK_EE2BEG0" ], [ "CLK_FEED_EE2BEG1", "VBRK_EE2BEG1" ], [ "CLK_FEED_EE2BEG2", "VBRK_EE2BEG2" ], [ "CLK_FEED_EE2BEG3", "VBRK_EE2BEG3" ], [ "CLK_FEED_EE4A0", "VBRK_EE4A0" ], [ "CLK_FEED_EE4A1", "VBRK_EE4A1" ], [ "CLK_FEED_EE4A2", "VBRK_EE4A2" ], [ "CLK_FEED_EE4A3", "VBRK_EE4A3" ], [ "CLK_FEED_EE4B0", "VBRK_EE4B0" ], [ "CLK_FEED_EE4B1", "VBRK_EE4B1" ], [ "CLK_FEED_EE4B2", "VBRK_EE4B2" ], [ "CLK_FEED_EE4B3", "VBRK_EE4B3" ], [ "CLK_FEED_EE4BEG0", "VBRK_EE4BEG0" ], [ "CLK_FEED_EE4BEG1", "VBRK_EE4BEG1" ], [ "CLK_FEED_EE4BEG2", "VBRK_EE4BEG2" ], [ "CLK_FEED_EE4BEG3", "VBRK_EE4BEG3" ], [ "CLK_FEED_EE4C0", "VBRK_EE4C0" ], [ "CLK_FEED_EE4C1", "VBRK_EE4C1" ], [ "CLK_FEED_EE4C2", "VBRK_EE4C2" ], [ "CLK_FEED_EE4C3", "VBRK_EE4C3" ], [ "CLK_FEED_EL1BEG0", "VBRK_EL1BEG0" ], [ "CLK_FEED_EL1BEG1", "VBRK_EL1BEG1" ], [ "CLK_FEED_EL1BEG2", "VBRK_EL1BEG2" ], [ "CLK_FEED_EL1BEG3", "VBRK_EL1BEG3" ], [ "CLK_FEED_ER1BEG0", "VBRK_ER1BEG0" ], [ "CLK_FEED_ER1BEG1", "VBRK_ER1BEG1" ], [ "CLK_FEED_ER1BEG2", "VBRK_ER1BEG2" ], [ "CLK_FEED_ER1BEG3", "VBRK_ER1BEG3" ], [ "CLK_FEED_LH1", "VBRK_LH1" ], [ "CLK_FEED_LH2", "VBRK_LH2" ], [ "CLK_FEED_LH3", "VBRK_LH3" ], [ "CLK_FEED_LH4", "VBRK_LH4" ], [ "CLK_FEED_LH5", "VBRK_LH5" ], [ "CLK_FEED_LH6", "VBRK_LH6" ], [ "CLK_FEED_LH7", "VBRK_LH7" ], [ "CLK_FEED_LH8", "VBRK_LH8" ], [ "CLK_FEED_LH9", "VBRK_LH9" ], [ "CLK_FEED_LH10", "VBRK_LH10" ], [ "CLK_FEED_LH11", "VBRK_LH11" ], [ "CLK_FEED_LH12", "VBRK_LH12" ], [ "CLK_FEED_MONITOR_N", "VBRK_MONITOR_N" ], [ "CLK_FEED_MONITOR_P", "VBRK_MONITOR_P" ], [ "CLK_FEED_NE2A0", "VBRK_NE2A0" ], [ "CLK_FEED_NE2A1", "VBRK_NE2A1" ], [ "CLK_FEED_NE2A2", "VBRK_NE2A2" ], [ "CLK_FEED_NE2A3", "VBRK_NE2A3" ], [ "CLK_FEED_NE4BEG0", "VBRK_NE4BEG0" ], [ "CLK_FEED_NE4BEG1", "VBRK_NE4BEG1" ], [ "CLK_FEED_NE4BEG2", "VBRK_NE4BEG2" ], [ "CLK_FEED_NE4BEG3", "VBRK_NE4BEG3" ], [ "CLK_FEED_NE4C0", "VBRK_NE4C0" ], [ "CLK_FEED_NE4C1", "VBRK_NE4C1" ], [ "CLK_FEED_NE4C2", "VBRK_NE4C2" ], [ "CLK_FEED_NE4C3", "VBRK_NE4C3" ], [ "CLK_FEED_NW2A0", "VBRK_NW2A0" ], [ "CLK_FEED_NW2A1", "VBRK_NW2A1" ], [ "CLK_FEED_NW2A2", "VBRK_NW2A2" ], [ "CLK_FEED_NW2A3", "VBRK_NW2A3" ], [ "CLK_FEED_NW4A0", "VBRK_NW4A0" ], [ "CLK_FEED_NW4A1", "VBRK_NW4A1" ], [ "CLK_FEED_NW4A2", "VBRK_NW4A2" ], [ "CLK_FEED_NW4A3", "VBRK_NW4A3" ], [ "CLK_FEED_NW4END0", "VBRK_NW4END0" ], [ "CLK_FEED_NW4END1", "VBRK_NW4END1" ], [ "CLK_FEED_NW4END2", "VBRK_NW4END2" ], [ "CLK_FEED_NW4END3", "VBRK_NW4END3" ], [ "CLK_FEED_SE2A0", "VBRK_SE2A0" ], [ "CLK_FEED_SE2A1", "VBRK_SE2A1" ], [ "CLK_FEED_SE2A2", "VBRK_SE2A2" ], [ "CLK_FEED_SE2A3", "VBRK_SE2A3" ], [ "CLK_FEED_SE4BEG0", "VBRK_SE4BEG0" ], [ "CLK_FEED_SE4BEG1", "VBRK_SE4BEG1" ], [ "CLK_FEED_SE4BEG2", "VBRK_SE4BEG2" ], [ "CLK_FEED_SE4BEG3", "VBRK_SE4BEG3" ], [ "CLK_FEED_SE4C0", "VBRK_SE4C0" ], [ "CLK_FEED_SE4C1", "VBRK_SE4C1" ], [ "CLK_FEED_SE4C2", "VBRK_SE4C2" ], [ "CLK_FEED_SE4C3", "VBRK_SE4C3" ], [ "CLK_FEED_SW2A0", "VBRK_SW2A0" ], [ "CLK_FEED_SW2A1", "VBRK_SW2A1" ], [ "CLK_FEED_SW2A2", "VBRK_SW2A2" ], [ "CLK_FEED_SW2A3", "VBRK_SW2A3" ], [ "CLK_FEED_SW4A0", "VBRK_SW4A0" ], [ "CLK_FEED_SW4A1", "VBRK_SW4A1" ], [ "CLK_FEED_SW4A2", "VBRK_SW4A2" ], [ "CLK_FEED_SW4A3", "VBRK_SW4A3" ], [ "CLK_FEED_SW4END0", "VBRK_SW4END0" ], [ "CLK_FEED_SW4END1", "VBRK_SW4END1" ], [ "CLK_FEED_SW4END2", "VBRK_SW4END2" ], [ "CLK_FEED_SW4END3", "VBRK_SW4END3" ], [ "CLK_FEED_WL1END0", "VBRK_WL1END0" ], [ "CLK_FEED_WL1END1", "VBRK_WL1END1" ], [ "CLK_FEED_WL1END2", "VBRK_WL1END2" ], [ "CLK_FEED_WL1END3", "VBRK_WL1END3" ], [ "CLK_FEED_WR1END0", "VBRK_WR1END0" ], [ "CLK_FEED_WR1END1", "VBRK_WR1END1" ], [ "CLK_FEED_WR1END2", "VBRK_WR1END2" ], [ "CLK_FEED_WR1END3", "VBRK_WR1END3" ], [ "CLK_FEED_WW2A0", "VBRK_WW2A0" ], [ "CLK_FEED_WW2A1", "VBRK_WW2A1" ], [ "CLK_FEED_WW2A2", "VBRK_WW2A2" ], [ "CLK_FEED_WW2A3", "VBRK_WW2A3" ], [ "CLK_FEED_WW2END0", "VBRK_WW2END0" ], [ "CLK_FEED_WW2END1", "VBRK_WW2END1" ], [ "CLK_FEED_WW2END2", "VBRK_WW2END2" ], [ "CLK_FEED_WW2END3", "VBRK_WW2END3" ], [ "CLK_FEED_WW4A0", "VBRK_WW4A0" ], [ "CLK_FEED_WW4A1", "VBRK_WW4A1" ], [ "CLK_FEED_WW4A2", "VBRK_WW4A2" ], [ "CLK_FEED_WW4A3", "VBRK_WW4A3" ], [ "CLK_FEED_WW4B0", "VBRK_WW4B0" ], [ "CLK_FEED_WW4B1", "VBRK_WW4B1" ], [ "CLK_FEED_WW4B2", "VBRK_WW4B2" ], [ "CLK_FEED_WW4B3", "VBRK_WW4B3" ], [ "CLK_FEED_WW4C0", "VBRK_WW4C0" ], [ "CLK_FEED_WW4C1", "VBRK_WW4C1" ], [ "CLK_FEED_WW4C2", "VBRK_WW4C2" ], [ "CLK_FEED_WW4C3", "VBRK_WW4C3" ], [ "CLK_FEED_WW4END0", "VBRK_WW4END0" ], [ "CLK_FEED_WW4END1", "VBRK_WW4END1" ], [ "CLK_FEED_WW4END2", "VBRK_WW4END2" ], [ "CLK_FEED_WW4END3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, -6 ], "tile_types": [ "CLK_PMV", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_PMV_BYP0_6", "INT_INTERFACE_BYP0" ], [ "CLK_PMV_BYP1_6", "INT_INTERFACE_BYP1" ], [ "CLK_PMV_BYP2_6", "INT_INTERFACE_BYP2" ], [ "CLK_PMV_BYP3_6", "INT_INTERFACE_BYP3" ], [ "CLK_PMV_BYP4_6", "INT_INTERFACE_BYP4" ], [ "CLK_PMV_BYP5_6", "INT_INTERFACE_BYP5" ], [ "CLK_PMV_BYP6_6", "INT_INTERFACE_BYP6" ], [ "CLK_PMV_BYP7_6", "INT_INTERFACE_BYP7" ], [ "CLK_PMV_CLK0_6", "INT_INTERFACE_CLK0" ], [ "CLK_PMV_CLK1_6", "INT_INTERFACE_CLK1" ], [ "CLK_PMV_CTRL0_6", "INT_INTERFACE_CTRL0" ], [ "CLK_PMV_CTRL1_6", "INT_INTERFACE_CTRL1" ], [ "CLK_PMV_EE2A0_6", "INT_INTERFACE_EE2A0" ], [ "CLK_PMV_EE2A1_6", "INT_INTERFACE_EE2A1" ], [ "CLK_PMV_EE2A2_6", "INT_INTERFACE_EE2A2" ], [ "CLK_PMV_EE2A3_6", "INT_INTERFACE_EE2A3" ], [ "CLK_PMV_EE2BEG0_6", "INT_INTERFACE_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_6", "INT_INTERFACE_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_6", "INT_INTERFACE_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_6", "INT_INTERFACE_EE2BEG3" ], [ "CLK_PMV_EE4A0_6", "INT_INTERFACE_EE4A0" ], [ "CLK_PMV_EE4A1_6", "INT_INTERFACE_EE4A1" ], [ "CLK_PMV_EE4A2_6", "INT_INTERFACE_EE4A2" ], [ "CLK_PMV_EE4A3_6", "INT_INTERFACE_EE4A3" ], [ "CLK_PMV_EE4B0_6", "INT_INTERFACE_EE4B0" ], [ "CLK_PMV_EE4B1_6", "INT_INTERFACE_EE4B1" ], [ "CLK_PMV_EE4B2_6", "INT_INTERFACE_EE4B2" ], [ "CLK_PMV_EE4B3_6", "INT_INTERFACE_EE4B3" ], [ "CLK_PMV_EE4BEG0_6", "INT_INTERFACE_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_6", "INT_INTERFACE_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_6", "INT_INTERFACE_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_6", "INT_INTERFACE_EE4BEG3" ], [ "CLK_PMV_EE4C0_6", "INT_INTERFACE_EE4C0" ], [ "CLK_PMV_EE4C1_6", "INT_INTERFACE_EE4C1" ], [ "CLK_PMV_EE4C2_6", "INT_INTERFACE_EE4C2" ], [ "CLK_PMV_EE4C3_6", "INT_INTERFACE_EE4C3" ], [ "CLK_PMV_EL1BEG0_6", "INT_INTERFACE_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_6", "INT_INTERFACE_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_6", "INT_INTERFACE_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_6", "INT_INTERFACE_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_6", "INT_INTERFACE_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_6", "INT_INTERFACE_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_6", "INT_INTERFACE_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_6", "INT_INTERFACE_ER1BEG3" ], [ "CLK_PMV_FAN0_6", "INT_INTERFACE_FAN0" ], [ "CLK_PMV_FAN1_6", "INT_INTERFACE_FAN1" ], [ "CLK_PMV_FAN2_6", "INT_INTERFACE_FAN2" ], [ "CLK_PMV_FAN3_6", "INT_INTERFACE_FAN3" ], [ "CLK_PMV_FAN4_6", "INT_INTERFACE_FAN4" ], [ "CLK_PMV_FAN5_6", "INT_INTERFACE_FAN5" ], [ "CLK_PMV_FAN6_6", "INT_INTERFACE_FAN6" ], [ "CLK_PMV_FAN7_6", "INT_INTERFACE_FAN7" ], [ "CLK_PMV_IMUX0_6", "INT_INTERFACE_IMUX0" ], [ "CLK_PMV_IMUX1_6", "INT_INTERFACE_IMUX1" ], [ "CLK_PMV_IMUX2_6", "INT_INTERFACE_IMUX2" ], [ "CLK_PMV_IMUX3_6", "INT_INTERFACE_IMUX3" ], [ "CLK_PMV_IMUX4_6", "INT_INTERFACE_IMUX4" ], [ "CLK_PMV_IMUX5_6", "INT_INTERFACE_IMUX5" ], [ "CLK_PMV_IMUX6_6", "INT_INTERFACE_IMUX6" ], [ "CLK_PMV_IMUX7_6", "INT_INTERFACE_IMUX7" ], [ "CLK_PMV_IMUX8_6", "INT_INTERFACE_IMUX8" ], [ "CLK_PMV_IMUX9_6", "INT_INTERFACE_IMUX9" ], [ "CLK_PMV_IMUX10_6", "INT_INTERFACE_IMUX10" ], [ "CLK_PMV_IMUX11_6", "INT_INTERFACE_IMUX11" ], [ "CLK_PMV_IMUX12_6", "INT_INTERFACE_IMUX12" ], [ "CLK_PMV_IMUX13_6", "INT_INTERFACE_IMUX13" ], [ "CLK_PMV_IMUX14_6", "INT_INTERFACE_IMUX14" ], [ "CLK_PMV_IMUX15_6", "INT_INTERFACE_IMUX15" ], [ "CLK_PMV_IMUX16_6", "INT_INTERFACE_IMUX16" ], [ "CLK_PMV_IMUX17_6", "INT_INTERFACE_IMUX17" ], [ "CLK_PMV_IMUX18_6", "INT_INTERFACE_IMUX18" ], [ "CLK_PMV_IMUX19_6", "INT_INTERFACE_IMUX19" ], [ "CLK_PMV_IMUX20_6", "INT_INTERFACE_IMUX20" ], [ "CLK_PMV_IMUX21_6", "INT_INTERFACE_IMUX21" ], [ "CLK_PMV_IMUX22_6", "INT_INTERFACE_IMUX22" ], [ "CLK_PMV_IMUX23_6", "INT_INTERFACE_IMUX23" ], [ "CLK_PMV_IMUX24_6", "INT_INTERFACE_IMUX24" ], [ "CLK_PMV_IMUX25_6", "INT_INTERFACE_IMUX25" ], [ "CLK_PMV_IMUX26_6", "INT_INTERFACE_IMUX26" ], [ "CLK_PMV_IMUX27_6", "INT_INTERFACE_IMUX27" ], [ "CLK_PMV_IMUX28_6", "INT_INTERFACE_IMUX28" ], [ "CLK_PMV_IMUX29_6", "INT_INTERFACE_IMUX29" ], [ "CLK_PMV_IMUX30_6", "INT_INTERFACE_IMUX30" ], [ "CLK_PMV_IMUX31_6", "INT_INTERFACE_IMUX31" ], [ "CLK_PMV_IMUX32_6", "INT_INTERFACE_IMUX32" ], [ "CLK_PMV_IMUX33_6", "INT_INTERFACE_IMUX33" ], [ "CLK_PMV_IMUX34_6", "INT_INTERFACE_IMUX34" ], [ "CLK_PMV_IMUX35_6", "INT_INTERFACE_IMUX35" ], [ "CLK_PMV_IMUX36_6", "INT_INTERFACE_IMUX36" ], [ "CLK_PMV_IMUX37_6", "INT_INTERFACE_IMUX37" ], [ "CLK_PMV_IMUX38_6", "INT_INTERFACE_IMUX38" ], [ "CLK_PMV_IMUX39_6", "INT_INTERFACE_IMUX39" ], [ "CLK_PMV_IMUX40_6", "INT_INTERFACE_IMUX40" ], [ "CLK_PMV_IMUX41_6", "INT_INTERFACE_IMUX41" ], [ "CLK_PMV_IMUX42_6", "INT_INTERFACE_IMUX42" ], [ "CLK_PMV_IMUX43_6", "INT_INTERFACE_IMUX43" ], [ "CLK_PMV_IMUX44_6", "INT_INTERFACE_IMUX44" ], [ "CLK_PMV_IMUX45_6", "INT_INTERFACE_IMUX45" ], [ "CLK_PMV_IMUX46_6", "INT_INTERFACE_IMUX46" ], [ "CLK_PMV_IMUX47_6", "INT_INTERFACE_IMUX47" ], [ "CLK_PMV_LH1_6", "INT_INTERFACE_LH1" ], [ "CLK_PMV_LH2_6", "INT_INTERFACE_LH2" ], [ "CLK_PMV_LH3_6", "INT_INTERFACE_LH3" ], [ "CLK_PMV_LH4_6", "INT_INTERFACE_LH4" ], [ "CLK_PMV_LH5_6", "INT_INTERFACE_LH5" ], [ "CLK_PMV_LH6_6", "INT_INTERFACE_LH6" ], [ "CLK_PMV_LH7_6", "INT_INTERFACE_LH7" ], [ "CLK_PMV_LH8_6", "INT_INTERFACE_LH8" ], [ "CLK_PMV_LH9_6", "INT_INTERFACE_LH9" ], [ "CLK_PMV_LH10_6", "INT_INTERFACE_LH10" ], [ "CLK_PMV_LH11_6", "INT_INTERFACE_LH11" ], [ "CLK_PMV_LH12_6", "INT_INTERFACE_LH12" ], [ "CLK_PMV_MONITOR_N_6", "INT_INTERFACE_MONITOR_N" ], [ "CLK_PMV_MONITOR_P_6", "INT_INTERFACE_MONITOR_P" ], [ "CLK_PMV_NE2A0_6", "INT_INTERFACE_NE2A0" ], [ "CLK_PMV_NE2A1_6", "INT_INTERFACE_NE2A1" ], [ "CLK_PMV_NE2A2_6", "INT_INTERFACE_NE2A2" ], [ "CLK_PMV_NE2A3_6", "INT_INTERFACE_NE2A3" ], [ "CLK_PMV_NE4BEG0_6", "INT_INTERFACE_NE4BEG0" ], [ "CLK_PMV_NE4BEG1_6", "INT_INTERFACE_NE4BEG1" ], [ "CLK_PMV_NE4BEG2_6", "INT_INTERFACE_NE4BEG2" ], [ "CLK_PMV_NE4BEG3_6", "INT_INTERFACE_NE4BEG3" ], [ "CLK_PMV_NE4C0_6", "INT_INTERFACE_NE4C0" ], [ "CLK_PMV_NE4C1_6", "INT_INTERFACE_NE4C1" ], [ "CLK_PMV_NE4C2_6", "INT_INTERFACE_NE4C2" ], [ "CLK_PMV_NE4C3_6", "INT_INTERFACE_NE4C3" ], [ "CLK_PMV_NW2A0_6", "INT_INTERFACE_NW2A0" ], [ "CLK_PMV_NW2A1_6", "INT_INTERFACE_NW2A1" ], [ "CLK_PMV_NW2A2_6", "INT_INTERFACE_NW2A2" ], [ "CLK_PMV_NW2A3_6", "INT_INTERFACE_NW2A3" ], [ "CLK_PMV_NW4A0_6", "INT_INTERFACE_NW4A0" ], [ "CLK_PMV_NW4A1_6", "INT_INTERFACE_NW4A1" ], [ "CLK_PMV_NW4A2_6", "INT_INTERFACE_NW4A2" ], [ "CLK_PMV_NW4A3_6", "INT_INTERFACE_NW4A3" ], [ "CLK_PMV_NW4END0_6", "INT_INTERFACE_NW4END0" ], [ "CLK_PMV_NW4END1_6", "INT_INTERFACE_NW4END1" ], [ "CLK_PMV_NW4END2_6", "INT_INTERFACE_NW4END2" ], [ "CLK_PMV_NW4END3_6", "INT_INTERFACE_NW4END3" ], [ "CLK_PMV_SE2A0_6", "INT_INTERFACE_SE2A0" ], [ "CLK_PMV_SE2A1_6", "INT_INTERFACE_SE2A1" ], [ "CLK_PMV_SE2A2_6", "INT_INTERFACE_SE2A2" ], [ "CLK_PMV_SE2A3_6", "INT_INTERFACE_SE2A3" ], [ "CLK_PMV_SE4BEG0_6", "INT_INTERFACE_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_6", "INT_INTERFACE_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_6", "INT_INTERFACE_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_6", "INT_INTERFACE_SE4BEG3" ], [ "CLK_PMV_SE4C0_6", "INT_INTERFACE_SE4C0" ], [ "CLK_PMV_SE4C1_6", "INT_INTERFACE_SE4C1" ], [ "CLK_PMV_SE4C2_6", "INT_INTERFACE_SE4C2" ], [ "CLK_PMV_SE4C3_6", "INT_INTERFACE_SE4C3" ], [ "CLK_PMV_SW2A0_6", "INT_INTERFACE_SW2A0" ], [ "CLK_PMV_SW2A1_6", "INT_INTERFACE_SW2A1" ], [ "CLK_PMV_SW2A2_6", "INT_INTERFACE_SW2A2" ], [ "CLK_PMV_SW2A3_6", "INT_INTERFACE_SW2A3" ], [ "CLK_PMV_SW4A0_6", "INT_INTERFACE_SW4A0" ], [ "CLK_PMV_SW4A1_6", "INT_INTERFACE_SW4A1" ], [ "CLK_PMV_SW4A2_6", "INT_INTERFACE_SW4A2" ], [ "CLK_PMV_SW4A3_6", "INT_INTERFACE_SW4A3" ], [ "CLK_PMV_SW4END0_6", "INT_INTERFACE_SW4END0" ], [ "CLK_PMV_SW4END1_6", "INT_INTERFACE_SW4END1" ], [ "CLK_PMV_SW4END2_6", "INT_INTERFACE_SW4END2" ], [ "CLK_PMV_SW4END3_6", "INT_INTERFACE_SW4END3" ], [ "CLK_PMV_WL1END0_6", "INT_INTERFACE_WL1END0" ], [ "CLK_PMV_WL1END1_6", "INT_INTERFACE_WL1END1" ], [ "CLK_PMV_WL1END2_6", "INT_INTERFACE_WL1END2" ], [ "CLK_PMV_WL1END3_6", "INT_INTERFACE_WL1END3" ], [ "CLK_PMV_WR1END0_6", "INT_INTERFACE_WR1END0" ], [ "CLK_PMV_WR1END1_6", "INT_INTERFACE_WR1END1" ], [ "CLK_PMV_WR1END2_6", "INT_INTERFACE_WR1END2" ], [ "CLK_PMV_WR1END3_6", "INT_INTERFACE_WR1END3" ], [ "CLK_PMV_WW2A0_6", "INT_INTERFACE_WW2A0" ], [ "CLK_PMV_WW2A1_6", "INT_INTERFACE_WW2A1" ], [ "CLK_PMV_WW2A2_6", "INT_INTERFACE_WW2A2" ], [ "CLK_PMV_WW2A3_6", "INT_INTERFACE_WW2A3" ], [ "CLK_PMV_WW2END0_6", "INT_INTERFACE_WW2END0" ], [ "CLK_PMV_WW2END1_6", "INT_INTERFACE_WW2END1" ], [ "CLK_PMV_WW2END2_6", "INT_INTERFACE_WW2END2" ], [ "CLK_PMV_WW2END3_6", "INT_INTERFACE_WW2END3" ], [ "CLK_PMV_WW4A0_6", "INT_INTERFACE_WW4A0" ], [ "CLK_PMV_WW4A1_6", "INT_INTERFACE_WW4A1" ], [ "CLK_PMV_WW4A2_6", "INT_INTERFACE_WW4A2" ], [ "CLK_PMV_WW4A3_6", "INT_INTERFACE_WW4A3" ], [ "CLK_PMV_WW4B0_6", "INT_INTERFACE_WW4B0" ], [ "CLK_PMV_WW4B1_6", "INT_INTERFACE_WW4B1" ], [ "CLK_PMV_WW4B2_6", "INT_INTERFACE_WW4B2" ], [ "CLK_PMV_WW4B3_6", "INT_INTERFACE_WW4B3" ], [ "CLK_PMV_WW4C0_6", "INT_INTERFACE_WW4C0" ], [ "CLK_PMV_WW4C1_6", "INT_INTERFACE_WW4C1" ], [ "CLK_PMV_WW4C2_6", "INT_INTERFACE_WW4C2" ], [ "CLK_PMV_WW4C3_6", "INT_INTERFACE_WW4C3" ], [ "CLK_PMV_WW4END0_6", "INT_INTERFACE_WW4END0" ], [ "CLK_PMV_WW4END1_6", "INT_INTERFACE_WW4END1" ], [ "CLK_PMV_WW4END2_6", "INT_INTERFACE_WW4END2" ], [ "CLK_PMV_WW4END3_6", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -5 ], "tile_types": [ "CLK_PMV", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_PMV_BYP0_5", "INT_INTERFACE_BYP0" ], [ "CLK_PMV_BYP1_5", "INT_INTERFACE_BYP1" ], [ "CLK_PMV_BYP2_5", "INT_INTERFACE_BYP2" ], [ "CLK_PMV_BYP3_5", "INT_INTERFACE_BYP3" ], [ "CLK_PMV_BYP4_5", "INT_INTERFACE_BYP4" ], [ "CLK_PMV_BYP5_5", "INT_INTERFACE_BYP5" ], [ "CLK_PMV_BYP6_5", "INT_INTERFACE_BYP6" ], [ "CLK_PMV_BYP7_5", "INT_INTERFACE_BYP7" ], [ "CLK_PMV_CLK0_5", "INT_INTERFACE_CLK0" ], [ "CLK_PMV_CLK1_5", "INT_INTERFACE_CLK1" ], [ "CLK_PMV_CTRL0_5", "INT_INTERFACE_CTRL0" ], [ "CLK_PMV_CTRL1_5", "INT_INTERFACE_CTRL1" ], [ "CLK_PMV_EE2A0_5", "INT_INTERFACE_EE2A0" ], [ "CLK_PMV_EE2A1_5", "INT_INTERFACE_EE2A1" ], [ "CLK_PMV_EE2A2_5", "INT_INTERFACE_EE2A2" ], [ "CLK_PMV_EE2A3_5", "INT_INTERFACE_EE2A3" ], [ "CLK_PMV_EE2BEG0_5", "INT_INTERFACE_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_5", "INT_INTERFACE_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_5", "INT_INTERFACE_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_5", "INT_INTERFACE_EE2BEG3" ], [ "CLK_PMV_EE4A0_5", "INT_INTERFACE_EE4A0" ], [ "CLK_PMV_EE4A1_5", "INT_INTERFACE_EE4A1" ], [ "CLK_PMV_EE4A2_5", "INT_INTERFACE_EE4A2" ], [ "CLK_PMV_EE4A3_5", "INT_INTERFACE_EE4A3" ], [ "CLK_PMV_EE4B0_5", "INT_INTERFACE_EE4B0" ], [ "CLK_PMV_EE4B1_5", "INT_INTERFACE_EE4B1" ], [ "CLK_PMV_EE4B2_5", "INT_INTERFACE_EE4B2" ], [ "CLK_PMV_EE4B3_5", "INT_INTERFACE_EE4B3" ], [ "CLK_PMV_EE4BEG0_5", "INT_INTERFACE_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_5", "INT_INTERFACE_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_5", "INT_INTERFACE_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_5", "INT_INTERFACE_EE4BEG3" ], [ "CLK_PMV_EE4C0_5", "INT_INTERFACE_EE4C0" ], [ "CLK_PMV_EE4C1_5", "INT_INTERFACE_EE4C1" ], [ "CLK_PMV_EE4C2_5", "INT_INTERFACE_EE4C2" ], [ "CLK_PMV_EE4C3_5", "INT_INTERFACE_EE4C3" ], [ "CLK_PMV_EL1BEG0_5", "INT_INTERFACE_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_5", "INT_INTERFACE_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_5", "INT_INTERFACE_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_5", "INT_INTERFACE_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_5", "INT_INTERFACE_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_5", "INT_INTERFACE_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_5", "INT_INTERFACE_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_5", "INT_INTERFACE_ER1BEG3" ], [ "CLK_PMV_FAN0_5", "INT_INTERFACE_FAN0" ], [ "CLK_PMV_FAN1_5", "INT_INTERFACE_FAN1" ], [ "CLK_PMV_FAN2_5", "INT_INTERFACE_FAN2" ], [ "CLK_PMV_FAN3_5", "INT_INTERFACE_FAN3" ], [ "CLK_PMV_FAN4_5", "INT_INTERFACE_FAN4" ], [ "CLK_PMV_FAN5_5", "INT_INTERFACE_FAN5" ], [ "CLK_PMV_FAN6_5", "INT_INTERFACE_FAN6" ], [ "CLK_PMV_FAN7_5", "INT_INTERFACE_FAN7" ], [ "CLK_PMV_IMUX0_5", "INT_INTERFACE_IMUX0" ], [ "CLK_PMV_IMUX1_5", "INT_INTERFACE_IMUX1" ], [ "CLK_PMV_IMUX2_5", "INT_INTERFACE_IMUX2" ], [ "CLK_PMV_IMUX3_5", "INT_INTERFACE_IMUX3" ], [ "CLK_PMV_IMUX4_5", "INT_INTERFACE_IMUX4" ], [ "CLK_PMV_IMUX5_5", "INT_INTERFACE_IMUX5" ], [ "CLK_PMV_IMUX6_5", "INT_INTERFACE_IMUX6" ], [ "CLK_PMV_IMUX7_5", "INT_INTERFACE_IMUX7" ], [ "CLK_PMV_IMUX8_5", "INT_INTERFACE_IMUX8" ], [ "CLK_PMV_IMUX9_5", "INT_INTERFACE_IMUX9" ], [ "CLK_PMV_IMUX10_5", "INT_INTERFACE_IMUX10" ], [ "CLK_PMV_IMUX11_5", "INT_INTERFACE_IMUX11" ], [ "CLK_PMV_IMUX12_5", "INT_INTERFACE_IMUX12" ], [ "CLK_PMV_IMUX13_5", "INT_INTERFACE_IMUX13" ], [ "CLK_PMV_IMUX14_5", "INT_INTERFACE_IMUX14" ], [ "CLK_PMV_IMUX15_5", "INT_INTERFACE_IMUX15" ], [ "CLK_PMV_IMUX16_5", "INT_INTERFACE_IMUX16" ], [ "CLK_PMV_IMUX17_5", "INT_INTERFACE_IMUX17" ], [ "CLK_PMV_IMUX18_5", "INT_INTERFACE_IMUX18" ], [ "CLK_PMV_IMUX19_5", "INT_INTERFACE_IMUX19" ], [ "CLK_PMV_IMUX20_5", "INT_INTERFACE_IMUX20" ], [ "CLK_PMV_IMUX21_5", "INT_INTERFACE_IMUX21" ], [ "CLK_PMV_IMUX22_5", "INT_INTERFACE_IMUX22" ], [ "CLK_PMV_IMUX23_5", "INT_INTERFACE_IMUX23" ], [ "CLK_PMV_IMUX24_5", "INT_INTERFACE_IMUX24" ], [ "CLK_PMV_IMUX25_5", "INT_INTERFACE_IMUX25" ], [ "CLK_PMV_IMUX26_5", "INT_INTERFACE_IMUX26" ], [ "CLK_PMV_IMUX27_5", "INT_INTERFACE_IMUX27" ], [ "CLK_PMV_IMUX28_5", "INT_INTERFACE_IMUX28" ], [ "CLK_PMV_IMUX29_5", "INT_INTERFACE_IMUX29" ], [ "CLK_PMV_IMUX30_5", "INT_INTERFACE_IMUX30" ], [ "CLK_PMV_IMUX31_5", "INT_INTERFACE_IMUX31" ], [ "CLK_PMV_IMUX32_5", "INT_INTERFACE_IMUX32" ], [ "CLK_PMV_IMUX33_5", "INT_INTERFACE_IMUX33" ], [ "CLK_PMV_IMUX34_5", "INT_INTERFACE_IMUX34" ], [ "CLK_PMV_IMUX35_5", "INT_INTERFACE_IMUX35" ], [ "CLK_PMV_IMUX36_5", "INT_INTERFACE_IMUX36" ], [ "CLK_PMV_IMUX37_5", "INT_INTERFACE_IMUX37" ], [ "CLK_PMV_IMUX38_5", "INT_INTERFACE_IMUX38" ], [ "CLK_PMV_IMUX39_5", "INT_INTERFACE_IMUX39" ], [ "CLK_PMV_IMUX40_5", "INT_INTERFACE_IMUX40" ], [ "CLK_PMV_IMUX41_5", "INT_INTERFACE_IMUX41" ], [ "CLK_PMV_IMUX42_5", "INT_INTERFACE_IMUX42" ], [ "CLK_PMV_IMUX43_5", "INT_INTERFACE_IMUX43" ], [ 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"CLK_PMV_WL1END0_5", "INT_INTERFACE_WL1END0" ], [ "CLK_PMV_WL1END1_5", "INT_INTERFACE_WL1END1" ], [ "CLK_PMV_WL1END2_5", "INT_INTERFACE_WL1END2" ], [ "CLK_PMV_WL1END3_5", "INT_INTERFACE_WL1END3" ], [ "CLK_PMV_WR1END0_5", "INT_INTERFACE_WR1END0" ], [ "CLK_PMV_WR1END1_5", "INT_INTERFACE_WR1END1" ], [ "CLK_PMV_WR1END2_5", "INT_INTERFACE_WR1END2" ], [ "CLK_PMV_WR1END3_5", "INT_INTERFACE_WR1END3" ], [ "CLK_PMV_WW2A0_5", "INT_INTERFACE_WW2A0" ], [ "CLK_PMV_WW2A1_5", "INT_INTERFACE_WW2A1" ], [ "CLK_PMV_WW2A2_5", "INT_INTERFACE_WW2A2" ], [ "CLK_PMV_WW2A3_5", "INT_INTERFACE_WW2A3" ], [ "CLK_PMV_WW2END0_5", "INT_INTERFACE_WW2END0" ], [ "CLK_PMV_WW2END1_5", "INT_INTERFACE_WW2END1" ], [ "CLK_PMV_WW2END2_5", "INT_INTERFACE_WW2END2" ], [ "CLK_PMV_WW2END3_5", "INT_INTERFACE_WW2END3" ], [ "CLK_PMV_WW4A0_5", "INT_INTERFACE_WW4A0" ], [ "CLK_PMV_WW4A1_5", "INT_INTERFACE_WW4A1" ], [ "CLK_PMV_WW4A2_5", "INT_INTERFACE_WW4A2" ], [ "CLK_PMV_WW4A3_5", "INT_INTERFACE_WW4A3" ], [ "CLK_PMV_WW4B0_5", "INT_INTERFACE_WW4B0" ], [ "CLK_PMV_WW4B1_5", "INT_INTERFACE_WW4B1" ], [ "CLK_PMV_WW4B2_5", "INT_INTERFACE_WW4B2" ], [ "CLK_PMV_WW4B3_5", "INT_INTERFACE_WW4B3" ], [ "CLK_PMV_WW4C0_5", "INT_INTERFACE_WW4C0" ], [ "CLK_PMV_WW4C1_5", "INT_INTERFACE_WW4C1" ], [ "CLK_PMV_WW4C2_5", "INT_INTERFACE_WW4C2" ], [ "CLK_PMV_WW4C3_5", "INT_INTERFACE_WW4C3" ], [ "CLK_PMV_WW4END0_5", "INT_INTERFACE_WW4END0" ], [ "CLK_PMV_WW4END1_5", "INT_INTERFACE_WW4END1" ], [ "CLK_PMV_WW4END2_5", "INT_INTERFACE_WW4END2" ], [ "CLK_PMV_WW4END3_5", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -4 ], "tile_types": [ "CLK_PMV", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_PMV_BYP0_4", "INT_INTERFACE_BYP0" ], [ "CLK_PMV_BYP1_4", "INT_INTERFACE_BYP1" ], [ "CLK_PMV_BYP2_4", "INT_INTERFACE_BYP2" ], [ "CLK_PMV_BYP3_4", "INT_INTERFACE_BYP3" ], [ "CLK_PMV_BYP4_4", "INT_INTERFACE_BYP4" ], [ "CLK_PMV_BYP5_4", "INT_INTERFACE_BYP5" ], [ "CLK_PMV_BYP6_4", "INT_INTERFACE_BYP6" ], [ "CLK_PMV_BYP7_4", "INT_INTERFACE_BYP7" ], [ "CLK_PMV_CLK0_4", "INT_INTERFACE_CLK0" ], [ "CLK_PMV_CLK1_4", "INT_INTERFACE_CLK1" ], [ "CLK_PMV_CTRL0_4", "INT_INTERFACE_CTRL0" ], [ "CLK_PMV_CTRL1_4", "INT_INTERFACE_CTRL1" ], [ "CLK_PMV_EE2A0_4", "INT_INTERFACE_EE2A0" ], [ "CLK_PMV_EE2A1_4", "INT_INTERFACE_EE2A1" ], [ "CLK_PMV_EE2A2_4", "INT_INTERFACE_EE2A2" ], [ "CLK_PMV_EE2A3_4", "INT_INTERFACE_EE2A3" ], [ "CLK_PMV_EE2BEG0_4", "INT_INTERFACE_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_4", "INT_INTERFACE_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_4", "INT_INTERFACE_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_4", "INT_INTERFACE_EE2BEG3" ], [ "CLK_PMV_EE4A0_4", "INT_INTERFACE_EE4A0" ], [ "CLK_PMV_EE4A1_4", "INT_INTERFACE_EE4A1" ], [ "CLK_PMV_EE4A2_4", "INT_INTERFACE_EE4A2" ], [ "CLK_PMV_EE4A3_4", "INT_INTERFACE_EE4A3" ], [ "CLK_PMV_EE4B0_4", "INT_INTERFACE_EE4B0" ], [ "CLK_PMV_EE4B1_4", "INT_INTERFACE_EE4B1" ], [ "CLK_PMV_EE4B2_4", "INT_INTERFACE_EE4B2" ], [ "CLK_PMV_EE4B3_4", "INT_INTERFACE_EE4B3" ], [ "CLK_PMV_EE4BEG0_4", "INT_INTERFACE_EE4BEG0" ], [ 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"CLK_PMV_FAN6_4", "INT_INTERFACE_FAN6" ], [ "CLK_PMV_FAN7_4", "INT_INTERFACE_FAN7" ], [ "CLK_PMV_IMUX0_4", "INT_INTERFACE_IMUX0" ], [ "CLK_PMV_IMUX1_4", "INT_INTERFACE_IMUX1" ], [ "CLK_PMV_IMUX2_4", "INT_INTERFACE_IMUX2" ], [ "CLK_PMV_IMUX3_4", "INT_INTERFACE_IMUX3" ], [ "CLK_PMV_IMUX4_4", "INT_INTERFACE_IMUX4" ], [ "CLK_PMV_IMUX5_4", "INT_INTERFACE_IMUX5" ], [ "CLK_PMV_IMUX6_4", "INT_INTERFACE_IMUX6" ], [ "CLK_PMV_IMUX7_4", "INT_INTERFACE_IMUX7" ], [ "CLK_PMV_IMUX8_4", "INT_INTERFACE_IMUX8" ], [ "CLK_PMV_IMUX9_4", "INT_INTERFACE_IMUX9" ], [ "CLK_PMV_IMUX10_4", "INT_INTERFACE_IMUX10" ], [ "CLK_PMV_IMUX11_4", "INT_INTERFACE_IMUX11" ], [ "CLK_PMV_IMUX12_4", "INT_INTERFACE_IMUX12" ], [ "CLK_PMV_IMUX13_4", "INT_INTERFACE_IMUX13" ], [ "CLK_PMV_IMUX14_4", "INT_INTERFACE_IMUX14" ], [ "CLK_PMV_IMUX15_4", "INT_INTERFACE_IMUX15" ], [ "CLK_PMV_IMUX16_4", "INT_INTERFACE_IMUX16" ], [ "CLK_PMV_IMUX17_4", "INT_INTERFACE_IMUX17" ], [ "CLK_PMV_IMUX18_4", "INT_INTERFACE_IMUX18" ], [ "CLK_PMV_IMUX19_4", "INT_INTERFACE_IMUX19" ], [ "CLK_PMV_IMUX20_4", "INT_INTERFACE_IMUX20" ], [ "CLK_PMV_IMUX21_4", "INT_INTERFACE_IMUX21" ], [ "CLK_PMV_IMUX22_4", "INT_INTERFACE_IMUX22" ], [ "CLK_PMV_IMUX23_4", "INT_INTERFACE_IMUX23" ], [ "CLK_PMV_IMUX24_4", "INT_INTERFACE_IMUX24" ], [ "CLK_PMV_IMUX25_4", "INT_INTERFACE_IMUX25" ], [ "CLK_PMV_IMUX26_4", "INT_INTERFACE_IMUX26" ], [ "CLK_PMV_IMUX27_4", "INT_INTERFACE_IMUX27" ], [ "CLK_PMV_IMUX28_4", "INT_INTERFACE_IMUX28" ], [ "CLK_PMV_IMUX29_4", "INT_INTERFACE_IMUX29" ], [ "CLK_PMV_IMUX30_4", "INT_INTERFACE_IMUX30" ], [ "CLK_PMV_IMUX31_4", "INT_INTERFACE_IMUX31" ], [ "CLK_PMV_IMUX32_4", "INT_INTERFACE_IMUX32" ], [ "CLK_PMV_IMUX33_4", "INT_INTERFACE_IMUX33" ], [ "CLK_PMV_IMUX34_4", "INT_INTERFACE_IMUX34" ], [ "CLK_PMV_IMUX35_4", "INT_INTERFACE_IMUX35" ], [ "CLK_PMV_IMUX36_4", "INT_INTERFACE_IMUX36" ], [ "CLK_PMV_IMUX37_4", "INT_INTERFACE_IMUX37" ], [ "CLK_PMV_IMUX38_4", "INT_INTERFACE_IMUX38" ], [ "CLK_PMV_IMUX39_4", "INT_INTERFACE_IMUX39" ], [ "CLK_PMV_IMUX40_4", "INT_INTERFACE_IMUX40" ], [ "CLK_PMV_IMUX41_4", "INT_INTERFACE_IMUX41" ], [ "CLK_PMV_IMUX42_4", "INT_INTERFACE_IMUX42" ], [ "CLK_PMV_IMUX43_4", "INT_INTERFACE_IMUX43" ], [ "CLK_PMV_IMUX44_4", "INT_INTERFACE_IMUX44" ], [ "CLK_PMV_IMUX45_4", "INT_INTERFACE_IMUX45" ], [ "CLK_PMV_IMUX46_4", "INT_INTERFACE_IMUX46" ], [ "CLK_PMV_IMUX47_4", "INT_INTERFACE_IMUX47" ], [ "CLK_PMV_LH1_4", "INT_INTERFACE_LH1" ], [ "CLK_PMV_LH2_4", "INT_INTERFACE_LH2" ], [ "CLK_PMV_LH3_4", "INT_INTERFACE_LH3" ], [ "CLK_PMV_LH4_4", "INT_INTERFACE_LH4" ], [ "CLK_PMV_LH5_4", "INT_INTERFACE_LH5" ], [ "CLK_PMV_LH6_4", "INT_INTERFACE_LH6" ], [ "CLK_PMV_LH7_4", "INT_INTERFACE_LH7" ], [ "CLK_PMV_LH8_4", "INT_INTERFACE_LH8" ], [ "CLK_PMV_LH9_4", "INT_INTERFACE_LH9" ], [ "CLK_PMV_LH10_4", "INT_INTERFACE_LH10" ], [ "CLK_PMV_LH11_4", "INT_INTERFACE_LH11" ], [ "CLK_PMV_LH12_4", "INT_INTERFACE_LH12" ], [ "CLK_PMV_MONITOR_N_4", "INT_INTERFACE_MONITOR_N" ], [ "CLK_PMV_MONITOR_P_4", "INT_INTERFACE_MONITOR_P" ], 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"CLK_PMV_NW4END1_4", "INT_INTERFACE_NW4END1" ], [ "CLK_PMV_NW4END2_4", "INT_INTERFACE_NW4END2" ], [ "CLK_PMV_NW4END3_4", "INT_INTERFACE_NW4END3" ], [ "CLK_PMV_SE2A0_4", "INT_INTERFACE_SE2A0" ], [ "CLK_PMV_SE2A1_4", "INT_INTERFACE_SE2A1" ], [ "CLK_PMV_SE2A2_4", "INT_INTERFACE_SE2A2" ], [ "CLK_PMV_SE2A3_4", "INT_INTERFACE_SE2A3" ], [ "CLK_PMV_SE4BEG0_4", "INT_INTERFACE_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_4", "INT_INTERFACE_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_4", "INT_INTERFACE_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_4", "INT_INTERFACE_SE4BEG3" ], [ "CLK_PMV_SE4C0_4", "INT_INTERFACE_SE4C0" ], [ "CLK_PMV_SE4C1_4", "INT_INTERFACE_SE4C1" ], [ "CLK_PMV_SE4C2_4", "INT_INTERFACE_SE4C2" ], [ "CLK_PMV_SE4C3_4", "INT_INTERFACE_SE4C3" ], [ "CLK_PMV_SW2A0_4", "INT_INTERFACE_SW2A0" ], [ "CLK_PMV_SW2A1_4", "INT_INTERFACE_SW2A1" ], [ "CLK_PMV_SW2A2_4", "INT_INTERFACE_SW2A2" ], [ "CLK_PMV_SW2A3_4", "INT_INTERFACE_SW2A3" ], [ "CLK_PMV_SW4A0_4", "INT_INTERFACE_SW4A0" ], [ "CLK_PMV_SW4A1_4", "INT_INTERFACE_SW4A1" ], [ "CLK_PMV_SW4A2_4", "INT_INTERFACE_SW4A2" ], [ "CLK_PMV_SW4A3_4", "INT_INTERFACE_SW4A3" ], [ "CLK_PMV_SW4END0_4", "INT_INTERFACE_SW4END0" ], [ "CLK_PMV_SW4END1_4", "INT_INTERFACE_SW4END1" ], [ "CLK_PMV_SW4END2_4", "INT_INTERFACE_SW4END2" ], [ "CLK_PMV_SW4END3_4", "INT_INTERFACE_SW4END3" ], [ "CLK_PMV_WL1END0_4", "INT_INTERFACE_WL1END0" ], [ "CLK_PMV_WL1END1_4", "INT_INTERFACE_WL1END1" ], [ "CLK_PMV_WL1END2_4", "INT_INTERFACE_WL1END2" ], [ "CLK_PMV_WL1END3_4", "INT_INTERFACE_WL1END3" ], [ "CLK_PMV_WR1END0_4", "INT_INTERFACE_WR1END0" ], [ "CLK_PMV_WR1END1_4", "INT_INTERFACE_WR1END1" ], [ "CLK_PMV_WR1END2_4", "INT_INTERFACE_WR1END2" ], [ "CLK_PMV_WR1END3_4", "INT_INTERFACE_WR1END3" ], [ "CLK_PMV_WW2A0_4", "INT_INTERFACE_WW2A0" ], [ "CLK_PMV_WW2A1_4", "INT_INTERFACE_WW2A1" ], [ "CLK_PMV_WW2A2_4", "INT_INTERFACE_WW2A2" ], [ "CLK_PMV_WW2A3_4", "INT_INTERFACE_WW2A3" ], [ "CLK_PMV_WW2END0_4", "INT_INTERFACE_WW2END0" ], [ "CLK_PMV_WW2END1_4", "INT_INTERFACE_WW2END1" ], [ "CLK_PMV_WW2END2_4", "INT_INTERFACE_WW2END2" ], [ "CLK_PMV_WW2END3_4", "INT_INTERFACE_WW2END3" ], [ "CLK_PMV_WW4A0_4", "INT_INTERFACE_WW4A0" ], [ "CLK_PMV_WW4A1_4", "INT_INTERFACE_WW4A1" ], [ "CLK_PMV_WW4A2_4", "INT_INTERFACE_WW4A2" ], [ "CLK_PMV_WW4A3_4", "INT_INTERFACE_WW4A3" ], [ "CLK_PMV_WW4B0_4", "INT_INTERFACE_WW4B0" ], [ "CLK_PMV_WW4B1_4", "INT_INTERFACE_WW4B1" ], [ "CLK_PMV_WW4B2_4", "INT_INTERFACE_WW4B2" ], [ "CLK_PMV_WW4B3_4", "INT_INTERFACE_WW4B3" ], [ "CLK_PMV_WW4C0_4", "INT_INTERFACE_WW4C0" ], [ "CLK_PMV_WW4C1_4", "INT_INTERFACE_WW4C1" ], [ "CLK_PMV_WW4C2_4", "INT_INTERFACE_WW4C2" ], [ "CLK_PMV_WW4C3_4", "INT_INTERFACE_WW4C3" ], [ "CLK_PMV_WW4END0_4", "INT_INTERFACE_WW4END0" ], [ "CLK_PMV_WW4END1_4", "INT_INTERFACE_WW4END1" ], [ "CLK_PMV_WW4END2_4", "INT_INTERFACE_WW4END2" ], [ "CLK_PMV_WW4END3_4", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -3 ], "tile_types": [ "CLK_PMV", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_PMV_BYP0_3", "INT_INTERFACE_BYP0" ], [ "CLK_PMV_BYP1_3", "INT_INTERFACE_BYP1" ], [ "CLK_PMV_BYP2_3", "INT_INTERFACE_BYP2" ], [ "CLK_PMV_BYP3_3", "INT_INTERFACE_BYP3" ], [ "CLK_PMV_BYP4_3", "INT_INTERFACE_BYP4" ], [ "CLK_PMV_BYP5_3", "INT_INTERFACE_BYP5" ], [ "CLK_PMV_BYP6_3", "INT_INTERFACE_BYP6" ], [ "CLK_PMV_BYP7_3", "INT_INTERFACE_BYP7" ], [ "CLK_PMV_CLK0_3", "INT_INTERFACE_CLK0" ], [ "CLK_PMV_CLK1_3", "INT_INTERFACE_CLK1" ], [ "CLK_PMV_CTRL0_3", "INT_INTERFACE_CTRL0" ], [ "CLK_PMV_CTRL1_3", "INT_INTERFACE_CTRL1" ], [ "CLK_PMV_EE2A0_3", "INT_INTERFACE_EE2A0" ], [ "CLK_PMV_EE2A1_3", "INT_INTERFACE_EE2A1" ], [ "CLK_PMV_EE2A2_3", "INT_INTERFACE_EE2A2" ], [ "CLK_PMV_EE2A3_3", "INT_INTERFACE_EE2A3" ], [ "CLK_PMV_EE2BEG0_3", "INT_INTERFACE_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_3", "INT_INTERFACE_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_3", "INT_INTERFACE_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_3", "INT_INTERFACE_EE2BEG3" ], [ "CLK_PMV_EE4A0_3", "INT_INTERFACE_EE4A0" ], [ "CLK_PMV_EE4A1_3", "INT_INTERFACE_EE4A1" ], [ "CLK_PMV_EE4A2_3", "INT_INTERFACE_EE4A2" ], [ "CLK_PMV_EE4A3_3", "INT_INTERFACE_EE4A3" ], [ "CLK_PMV_EE4B0_3", "INT_INTERFACE_EE4B0" ], [ "CLK_PMV_EE4B1_3", "INT_INTERFACE_EE4B1" ], [ "CLK_PMV_EE4B2_3", "INT_INTERFACE_EE4B2" ], [ "CLK_PMV_EE4B3_3", "INT_INTERFACE_EE4B3" ], [ "CLK_PMV_EE4BEG0_3", "INT_INTERFACE_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_3", "INT_INTERFACE_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_3", "INT_INTERFACE_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_3", "INT_INTERFACE_EE4BEG3" ], [ "CLK_PMV_EE4C0_3", "INT_INTERFACE_EE4C0" ], [ "CLK_PMV_EE4C1_3", "INT_INTERFACE_EE4C1" ], [ "CLK_PMV_EE4C2_3", "INT_INTERFACE_EE4C2" ], [ "CLK_PMV_EE4C3_3", "INT_INTERFACE_EE4C3" ], [ "CLK_PMV_EL1BEG0_3", "INT_INTERFACE_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_3", "INT_INTERFACE_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_3", "INT_INTERFACE_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_3", "INT_INTERFACE_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_3", "INT_INTERFACE_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_3", "INT_INTERFACE_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_3", "INT_INTERFACE_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_3", "INT_INTERFACE_ER1BEG3" ], [ "CLK_PMV_FAN0_3", "INT_INTERFACE_FAN0" ], [ "CLK_PMV_FAN1_3", "INT_INTERFACE_FAN1" ], [ "CLK_PMV_FAN2_3", "INT_INTERFACE_FAN2" ], [ "CLK_PMV_FAN3_3", "INT_INTERFACE_FAN3" ], [ "CLK_PMV_FAN4_3", "INT_INTERFACE_FAN4" ], [ "CLK_PMV_FAN5_3", "INT_INTERFACE_FAN5" ], [ "CLK_PMV_FAN6_3", "INT_INTERFACE_FAN6" ], [ "CLK_PMV_FAN7_3", "INT_INTERFACE_FAN7" ], [ "CLK_PMV_IMUX0_3", "INT_INTERFACE_IMUX0" ], [ "CLK_PMV_IMUX1_3", "INT_INTERFACE_IMUX1" ], [ "CLK_PMV_IMUX2_3", "INT_INTERFACE_IMUX2" ], [ "CLK_PMV_IMUX3_3", "INT_INTERFACE_IMUX3" ], [ "CLK_PMV_IMUX4_3", "INT_INTERFACE_IMUX4" ], [ "CLK_PMV_IMUX5_3", "INT_INTERFACE_IMUX5" ], [ "CLK_PMV_IMUX6_3", "INT_INTERFACE_IMUX6" ], [ "CLK_PMV_IMUX7_3", "INT_INTERFACE_IMUX7" ], [ "CLK_PMV_IMUX8_3", "INT_INTERFACE_IMUX8" ], [ "CLK_PMV_IMUX9_3", "INT_INTERFACE_IMUX9" ], [ "CLK_PMV_IMUX10_3", "INT_INTERFACE_IMUX10" ], [ "CLK_PMV_IMUX11_3", "INT_INTERFACE_IMUX11" ], [ "CLK_PMV_IMUX12_3", "INT_INTERFACE_IMUX12" ], [ "CLK_PMV_IMUX13_3", "INT_INTERFACE_IMUX13" ], [ "CLK_PMV_IMUX14_3", "INT_INTERFACE_IMUX14" ], [ "CLK_PMV_IMUX15_3", "INT_INTERFACE_IMUX15" ], [ "CLK_PMV_IMUX16_3", "INT_INTERFACE_IMUX16" ], [ "CLK_PMV_IMUX17_3", "INT_INTERFACE_IMUX17" ], [ "CLK_PMV_IMUX18_3", "INT_INTERFACE_IMUX18" ], [ "CLK_PMV_IMUX19_3", "INT_INTERFACE_IMUX19" ], [ "CLK_PMV_IMUX20_3", "INT_INTERFACE_IMUX20" ], [ "CLK_PMV_IMUX21_3", "INT_INTERFACE_IMUX21" ], [ "CLK_PMV_IMUX22_3", "INT_INTERFACE_IMUX22" ], [ "CLK_PMV_IMUX23_3", "INT_INTERFACE_IMUX23" ], [ "CLK_PMV_IMUX24_3", "INT_INTERFACE_IMUX24" ], [ "CLK_PMV_IMUX25_3", "INT_INTERFACE_IMUX25" ], [ "CLK_PMV_IMUX26_3", "INT_INTERFACE_IMUX26" ], [ "CLK_PMV_IMUX27_3", "INT_INTERFACE_IMUX27" ], [ "CLK_PMV_IMUX28_3", "INT_INTERFACE_IMUX28" ], [ "CLK_PMV_IMUX29_3", "INT_INTERFACE_IMUX29" ], [ "CLK_PMV_IMUX30_3", "INT_INTERFACE_IMUX30" ], [ "CLK_PMV_IMUX31_3", "INT_INTERFACE_IMUX31" ], [ "CLK_PMV_IMUX32_3", "INT_INTERFACE_IMUX32" ], [ "CLK_PMV_IMUX33_3", "INT_INTERFACE_IMUX33" ], [ "CLK_PMV_IMUX34_3", "INT_INTERFACE_IMUX34" ], [ "CLK_PMV_IMUX35_3", "INT_INTERFACE_IMUX35" ], [ "CLK_PMV_IMUX36_3", "INT_INTERFACE_IMUX36" ], [ "CLK_PMV_IMUX37_3", "INT_INTERFACE_IMUX37" ], [ "CLK_PMV_IMUX38_3", "INT_INTERFACE_IMUX38" ], [ "CLK_PMV_IMUX39_3", "INT_INTERFACE_IMUX39" ], [ "CLK_PMV_IMUX40_3", "INT_INTERFACE_IMUX40" ], [ "CLK_PMV_IMUX41_3", "INT_INTERFACE_IMUX41" ], [ "CLK_PMV_IMUX42_3", "INT_INTERFACE_IMUX42" ], [ "CLK_PMV_IMUX43_3", "INT_INTERFACE_IMUX43" ], [ "CLK_PMV_IMUX44_3", "INT_INTERFACE_IMUX44" ], [ "CLK_PMV_IMUX45_3", "INT_INTERFACE_IMUX45" ], [ "CLK_PMV_IMUX46_3", "INT_INTERFACE_IMUX46" ], [ "CLK_PMV_IMUX47_3", "INT_INTERFACE_IMUX47" ], [ "CLK_PMV_LH1_3", "INT_INTERFACE_LH1" ], [ "CLK_PMV_LH2_3", "INT_INTERFACE_LH2" ], [ "CLK_PMV_LH3_3", "INT_INTERFACE_LH3" ], [ "CLK_PMV_LH4_3", "INT_INTERFACE_LH4" ], [ "CLK_PMV_LH5_3", "INT_INTERFACE_LH5" ], [ "CLK_PMV_LH6_3", "INT_INTERFACE_LH6" ], [ "CLK_PMV_LH7_3", "INT_INTERFACE_LH7" ], [ "CLK_PMV_LH8_3", "INT_INTERFACE_LH8" ], [ "CLK_PMV_LH9_3", "INT_INTERFACE_LH9" ], [ "CLK_PMV_LH10_3", "INT_INTERFACE_LH10" ], [ "CLK_PMV_LH11_3", "INT_INTERFACE_LH11" ], [ "CLK_PMV_LH12_3", "INT_INTERFACE_LH12" ], [ "CLK_PMV_LOGIC_OUTS1_3", "INT_INTERFACE_LOGIC_OUTS_B1" ], [ "CLK_PMV_LOGIC_OUTS9_3", "INT_INTERFACE_LOGIC_OUTS_B9" ], [ "CLK_PMV_LOGIC_OUTS13_3", "INT_INTERFACE_LOGIC_OUTS_B13" ], [ "CLK_PMV_NE2A0_3", "INT_INTERFACE_NE2A0" ], [ "CLK_PMV_NE2A1_3", "INT_INTERFACE_NE2A1" ], [ "CLK_PMV_NE2A2_3", "INT_INTERFACE_NE2A2" ], [ "CLK_PMV_NE2A3_3", "INT_INTERFACE_NE2A3" ], [ "CLK_PMV_NE4BEG0_3", "INT_INTERFACE_NE4BEG0" ], [ "CLK_PMV_NE4BEG1_3", "INT_INTERFACE_NE4BEG1" ], [ "CLK_PMV_NE4BEG2_3", "INT_INTERFACE_NE4BEG2" ], [ "CLK_PMV_NE4BEG3_3", "INT_INTERFACE_NE4BEG3" ], [ "CLK_PMV_NE4C0_3", "INT_INTERFACE_NE4C0" ], [ "CLK_PMV_NE4C1_3", "INT_INTERFACE_NE4C1" ], [ "CLK_PMV_NE4C2_3", "INT_INTERFACE_NE4C2" ], [ "CLK_PMV_NE4C3_3", "INT_INTERFACE_NE4C3" ], [ "CLK_PMV_NW2A0_3", "INT_INTERFACE_NW2A0" ], [ "CLK_PMV_NW2A1_3", "INT_INTERFACE_NW2A1" ], [ "CLK_PMV_NW2A2_3", "INT_INTERFACE_NW2A2" ], [ "CLK_PMV_NW2A3_3", "INT_INTERFACE_NW2A3" ], [ "CLK_PMV_NW4A0_3", "INT_INTERFACE_NW4A0" ], [ "CLK_PMV_NW4A1_3", "INT_INTERFACE_NW4A1" ], [ "CLK_PMV_NW4A2_3", "INT_INTERFACE_NW4A2" ], [ "CLK_PMV_NW4A3_3", "INT_INTERFACE_NW4A3" ], [ "CLK_PMV_NW4END0_3", "INT_INTERFACE_NW4END0" ], [ "CLK_PMV_NW4END1_3", "INT_INTERFACE_NW4END1" ], [ "CLK_PMV_NW4END2_3", "INT_INTERFACE_NW4END2" ], [ "CLK_PMV_NW4END3_3", "INT_INTERFACE_NW4END3" ], [ "CLK_PMV_SE2A0_3", "INT_INTERFACE_SE2A0" ], [ "CLK_PMV_SE2A1_3", "INT_INTERFACE_SE2A1" ], [ "CLK_PMV_SE2A2_3", "INT_INTERFACE_SE2A2" ], [ "CLK_PMV_SE2A3_3", "INT_INTERFACE_SE2A3" ], [ "CLK_PMV_SE4BEG0_3", "INT_INTERFACE_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_3", "INT_INTERFACE_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_3", "INT_INTERFACE_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_3", "INT_INTERFACE_SE4BEG3" ], [ "CLK_PMV_SE4C0_3", "INT_INTERFACE_SE4C0" ], [ "CLK_PMV_SE4C1_3", "INT_INTERFACE_SE4C1" ], [ "CLK_PMV_SE4C2_3", "INT_INTERFACE_SE4C2" ], [ "CLK_PMV_SE4C3_3", "INT_INTERFACE_SE4C3" ], [ "CLK_PMV_SW2A0_3", "INT_INTERFACE_SW2A0" ], [ "CLK_PMV_SW2A1_3", "INT_INTERFACE_SW2A1" ], [ "CLK_PMV_SW2A2_3", "INT_INTERFACE_SW2A2" ], [ "CLK_PMV_SW2A3_3", "INT_INTERFACE_SW2A3" ], [ "CLK_PMV_SW4A0_3", "INT_INTERFACE_SW4A0" ], [ "CLK_PMV_SW4A1_3", "INT_INTERFACE_SW4A1" ], [ "CLK_PMV_SW4A2_3", "INT_INTERFACE_SW4A2" ], [ "CLK_PMV_SW4A3_3", "INT_INTERFACE_SW4A3" ], [ "CLK_PMV_SW4END0_3", "INT_INTERFACE_SW4END0" ], [ "CLK_PMV_SW4END1_3", "INT_INTERFACE_SW4END1" ], [ "CLK_PMV_SW4END2_3", "INT_INTERFACE_SW4END2" ], [ "CLK_PMV_SW4END3_3", "INT_INTERFACE_SW4END3" ], [ "CLK_PMV_WL1END0_3", "INT_INTERFACE_WL1END0" ], [ "CLK_PMV_WL1END1_3", "INT_INTERFACE_WL1END1" ], [ "CLK_PMV_WL1END2_3", "INT_INTERFACE_WL1END2" ], [ "CLK_PMV_WL1END3_3", "INT_INTERFACE_WL1END3" ], [ "CLK_PMV_WR1END0_3", "INT_INTERFACE_WR1END0" ], [ "CLK_PMV_WR1END1_3", "INT_INTERFACE_WR1END1" ], [ "CLK_PMV_WR1END2_3", "INT_INTERFACE_WR1END2" ], [ "CLK_PMV_WR1END3_3", "INT_INTERFACE_WR1END3" ], [ "CLK_PMV_WW2A0_3", "INT_INTERFACE_WW2A0" ], [ "CLK_PMV_WW2A1_3", "INT_INTERFACE_WW2A1" ], [ "CLK_PMV_WW2A2_3", "INT_INTERFACE_WW2A2" ], [ "CLK_PMV_WW2A3_3", "INT_INTERFACE_WW2A3" ], [ "CLK_PMV_WW2END0_3", "INT_INTERFACE_WW2END0" ], [ "CLK_PMV_WW2END1_3", "INT_INTERFACE_WW2END1" ], [ "CLK_PMV_WW2END2_3", "INT_INTERFACE_WW2END2" ], [ "CLK_PMV_WW2END3_3", "INT_INTERFACE_WW2END3" ], [ "CLK_PMV_WW4A0_3", "INT_INTERFACE_WW4A0" ], [ "CLK_PMV_WW4A1_3", "INT_INTERFACE_WW4A1" ], [ "CLK_PMV_WW4A2_3", "INT_INTERFACE_WW4A2" ], [ "CLK_PMV_WW4A3_3", "INT_INTERFACE_WW4A3" ], [ "CLK_PMV_WW4B0_3", "INT_INTERFACE_WW4B0" ], [ "CLK_PMV_WW4B1_3", "INT_INTERFACE_WW4B1" ], [ "CLK_PMV_WW4B2_3", "INT_INTERFACE_WW4B2" ], [ "CLK_PMV_WW4B3_3", "INT_INTERFACE_WW4B3" ], [ "CLK_PMV_WW4C0_3", "INT_INTERFACE_WW4C0" ], [ "CLK_PMV_WW4C1_3", "INT_INTERFACE_WW4C1" ], [ "CLK_PMV_WW4C2_3", "INT_INTERFACE_WW4C2" ], [ "CLK_PMV_WW4C3_3", "INT_INTERFACE_WW4C3" ], [ "CLK_PMV_WW4END0_3", "INT_INTERFACE_WW4END0" ], [ "CLK_PMV_WW4END1_3", "INT_INTERFACE_WW4END1" ], [ "CLK_PMV_WW4END2_3", "INT_INTERFACE_WW4END2" ], [ "CLK_PMV_WW4END3_3", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -2 ], "tile_types": [ "CLK_PMV", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_PMV_BYP0_2", "INT_INTERFACE_BYP0" ], [ "CLK_PMV_BYP1_2", "INT_INTERFACE_BYP1" ], [ "CLK_PMV_BYP2_2", "INT_INTERFACE_BYP2" ], [ "CLK_PMV_BYP3_2", "INT_INTERFACE_BYP3" ], [ "CLK_PMV_BYP4_2", "INT_INTERFACE_BYP4" ], [ "CLK_PMV_BYP5_2", "INT_INTERFACE_BYP5" ], [ "CLK_PMV_BYP6_2", "INT_INTERFACE_BYP6" ], [ "CLK_PMV_BYP7_2", "INT_INTERFACE_BYP7" ], [ "CLK_PMV_CLK0_2", "INT_INTERFACE_CLK0" ], [ "CLK_PMV_CLK1_2", "INT_INTERFACE_CLK1" ], [ "CLK_PMV_CTRL0_2", "INT_INTERFACE_CTRL0" ], [ "CLK_PMV_CTRL1_2", "INT_INTERFACE_CTRL1" ], [ "CLK_PMV_EE2A0_2", "INT_INTERFACE_EE2A0" ], [ "CLK_PMV_EE2A1_2", "INT_INTERFACE_EE2A1" ], [ "CLK_PMV_EE2A2_2", "INT_INTERFACE_EE2A2" ], [ "CLK_PMV_EE2A3_2", "INT_INTERFACE_EE2A3" ], [ "CLK_PMV_EE2BEG0_2", "INT_INTERFACE_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_2", "INT_INTERFACE_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_2", "INT_INTERFACE_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_2", "INT_INTERFACE_EE2BEG3" ], [ "CLK_PMV_EE4A0_2", "INT_INTERFACE_EE4A0" ], [ "CLK_PMV_EE4A1_2", "INT_INTERFACE_EE4A1" ], [ "CLK_PMV_EE4A2_2", "INT_INTERFACE_EE4A2" ], [ "CLK_PMV_EE4A3_2", "INT_INTERFACE_EE4A3" ], [ "CLK_PMV_EE4B0_2", "INT_INTERFACE_EE4B0" ], [ "CLK_PMV_EE4B1_2", "INT_INTERFACE_EE4B1" ], [ "CLK_PMV_EE4B2_2", "INT_INTERFACE_EE4B2" ], [ "CLK_PMV_EE4B3_2", "INT_INTERFACE_EE4B3" ], [ "CLK_PMV_EE4BEG0_2", "INT_INTERFACE_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_2", "INT_INTERFACE_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_2", "INT_INTERFACE_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_2", "INT_INTERFACE_EE4BEG3" ], [ "CLK_PMV_EE4C0_2", "INT_INTERFACE_EE4C0" ], [ "CLK_PMV_EE4C1_2", "INT_INTERFACE_EE4C1" ], [ "CLK_PMV_EE4C2_2", "INT_INTERFACE_EE4C2" ], [ "CLK_PMV_EE4C3_2", "INT_INTERFACE_EE4C3" ], [ "CLK_PMV_EL1BEG0_2", "INT_INTERFACE_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_2", "INT_INTERFACE_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_2", "INT_INTERFACE_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_2", "INT_INTERFACE_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_2", "INT_INTERFACE_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_2", "INT_INTERFACE_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_2", "INT_INTERFACE_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_2", "INT_INTERFACE_ER1BEG3" ], [ "CLK_PMV_FAN0_2", "INT_INTERFACE_FAN0" ], [ "CLK_PMV_FAN1_2", "INT_INTERFACE_FAN1" ], [ "CLK_PMV_FAN2_2", "INT_INTERFACE_FAN2" ], [ "CLK_PMV_FAN3_2", "INT_INTERFACE_FAN3" ], [ "CLK_PMV_FAN4_2", "INT_INTERFACE_FAN4" ], [ "CLK_PMV_FAN5_2", "INT_INTERFACE_FAN5" ], [ "CLK_PMV_FAN6_2", "INT_INTERFACE_FAN6" ], [ "CLK_PMV_FAN7_2", "INT_INTERFACE_FAN7" ], [ "CLK_PMV_IMUX0_2", "INT_INTERFACE_IMUX0" ], [ "CLK_PMV_IMUX1_2", "INT_INTERFACE_IMUX1" ], [ "CLK_PMV_IMUX2_2", "INT_INTERFACE_IMUX2" ], [ "CLK_PMV_IMUX3_2", "INT_INTERFACE_IMUX3" ], [ "CLK_PMV_IMUX4_2", "INT_INTERFACE_IMUX4" ], [ "CLK_PMV_IMUX5_2", "INT_INTERFACE_IMUX5" ], [ "CLK_PMV_IMUX6_2", "INT_INTERFACE_IMUX6" ], [ "CLK_PMV_IMUX7_2", "INT_INTERFACE_IMUX7" ], [ "CLK_PMV_IMUX8_2", "INT_INTERFACE_IMUX8" ], [ "CLK_PMV_IMUX9_2", "INT_INTERFACE_IMUX9" ], [ "CLK_PMV_IMUX10_2", "INT_INTERFACE_IMUX10" ], [ "CLK_PMV_IMUX11_2", "INT_INTERFACE_IMUX11" ], [ "CLK_PMV_IMUX12_2", "INT_INTERFACE_IMUX12" ], [ "CLK_PMV_IMUX13_2", "INT_INTERFACE_IMUX13" ], [ "CLK_PMV_IMUX14_2", "INT_INTERFACE_IMUX14" ], [ "CLK_PMV_IMUX15_2", "INT_INTERFACE_IMUX15" ], [ "CLK_PMV_IMUX16_2", "INT_INTERFACE_IMUX16" ], [ "CLK_PMV_IMUX17_2", "INT_INTERFACE_IMUX17" ], [ "CLK_PMV_IMUX18_2", "INT_INTERFACE_IMUX18" ], [ "CLK_PMV_IMUX19_2", "INT_INTERFACE_IMUX19" ], [ "CLK_PMV_IMUX20_2", "INT_INTERFACE_IMUX20" ], [ "CLK_PMV_IMUX21_2", "INT_INTERFACE_IMUX21" ], [ "CLK_PMV_IMUX22_2", "INT_INTERFACE_IMUX22" ], [ "CLK_PMV_IMUX23_2", "INT_INTERFACE_IMUX23" ], [ "CLK_PMV_IMUX24_2", "INT_INTERFACE_IMUX24" ], [ "CLK_PMV_IMUX25_2", "INT_INTERFACE_IMUX25" ], [ "CLK_PMV_IMUX26_2", "INT_INTERFACE_IMUX26" ], [ "CLK_PMV_IMUX27_2", "INT_INTERFACE_IMUX27" ], [ "CLK_PMV_IMUX28_2", "INT_INTERFACE_IMUX28" ], [ "CLK_PMV_IMUX29_2", "INT_INTERFACE_IMUX29" ], [ "CLK_PMV_IMUX30_2", "INT_INTERFACE_IMUX30" ], [ "CLK_PMV_IMUX31_2", "INT_INTERFACE_IMUX31" ], [ "CLK_PMV_IMUX32_2", "INT_INTERFACE_IMUX32" ], [ "CLK_PMV_IMUX33_2", "INT_INTERFACE_IMUX33" ], [ "CLK_PMV_IMUX34_2", "INT_INTERFACE_IMUX34" ], [ "CLK_PMV_IMUX35_2", "INT_INTERFACE_IMUX35" ], [ "CLK_PMV_IMUX36_2", "INT_INTERFACE_IMUX36" ], [ "CLK_PMV_IMUX37_2", "INT_INTERFACE_IMUX37" ], [ "CLK_PMV_IMUX38_2", "INT_INTERFACE_IMUX38" ], [ "CLK_PMV_IMUX39_2", "INT_INTERFACE_IMUX39" ], [ "CLK_PMV_IMUX40_2", "INT_INTERFACE_IMUX40" ], [ "CLK_PMV_IMUX41_2", "INT_INTERFACE_IMUX41" ], [ "CLK_PMV_IMUX42_2", "INT_INTERFACE_IMUX42" ], [ "CLK_PMV_IMUX43_2", "INT_INTERFACE_IMUX43" ], [ "CLK_PMV_IMUX44_2", "INT_INTERFACE_IMUX44" ], [ "CLK_PMV_IMUX45_2", "INT_INTERFACE_IMUX45" ], [ "CLK_PMV_IMUX46_2", "INT_INTERFACE_IMUX46" ], [ "CLK_PMV_IMUX47_2", "INT_INTERFACE_IMUX47" ], [ "CLK_PMV_LH1_2", "INT_INTERFACE_LH1" ], [ "CLK_PMV_LH2_2", "INT_INTERFACE_LH2" ], [ "CLK_PMV_LH3_2", "INT_INTERFACE_LH3" ], [ "CLK_PMV_LH4_2", "INT_INTERFACE_LH4" ], [ "CLK_PMV_LH5_2", "INT_INTERFACE_LH5" ], [ "CLK_PMV_LH6_2", "INT_INTERFACE_LH6" ], [ "CLK_PMV_LH7_2", "INT_INTERFACE_LH7" ], [ "CLK_PMV_LH8_2", "INT_INTERFACE_LH8" ], [ "CLK_PMV_LH9_2", "INT_INTERFACE_LH9" ], [ "CLK_PMV_LH10_2", "INT_INTERFACE_LH10" ], [ "CLK_PMV_LH11_2", "INT_INTERFACE_LH11" ], [ "CLK_PMV_LH12_2", "INT_INTERFACE_LH12" ], [ "CLK_PMV_MONITOR_N_2", "INT_INTERFACE_MONITOR_N" ], [ "CLK_PMV_MONITOR_P_2", "INT_INTERFACE_MONITOR_P" ], [ "CLK_PMV_NE2A0_2", "INT_INTERFACE_NE2A0" ], [ "CLK_PMV_NE2A1_2", "INT_INTERFACE_NE2A1" ], [ "CLK_PMV_NE2A2_2", "INT_INTERFACE_NE2A2" ], [ "CLK_PMV_NE2A3_2", "INT_INTERFACE_NE2A3" ], [ "CLK_PMV_NE4BEG0_2", "INT_INTERFACE_NE4BEG0" ], [ "CLK_PMV_NE4BEG1_2", "INT_INTERFACE_NE4BEG1" ], [ "CLK_PMV_NE4BEG2_2", "INT_INTERFACE_NE4BEG2" ], [ "CLK_PMV_NE4BEG3_2", "INT_INTERFACE_NE4BEG3" ], [ "CLK_PMV_NE4C0_2", "INT_INTERFACE_NE4C0" ], [ "CLK_PMV_NE4C1_2", "INT_INTERFACE_NE4C1" ], [ "CLK_PMV_NE4C2_2", "INT_INTERFACE_NE4C2" ], [ "CLK_PMV_NE4C3_2", "INT_INTERFACE_NE4C3" ], [ "CLK_PMV_NW2A0_2", "INT_INTERFACE_NW2A0" ], [ "CLK_PMV_NW2A1_2", "INT_INTERFACE_NW2A1" ], [ "CLK_PMV_NW2A2_2", "INT_INTERFACE_NW2A2" ], [ "CLK_PMV_NW2A3_2", "INT_INTERFACE_NW2A3" ], [ "CLK_PMV_NW4A0_2", "INT_INTERFACE_NW4A0" ], [ "CLK_PMV_NW4A1_2", "INT_INTERFACE_NW4A1" ], [ "CLK_PMV_NW4A2_2", "INT_INTERFACE_NW4A2" ], [ "CLK_PMV_NW4A3_2", "INT_INTERFACE_NW4A3" ], [ "CLK_PMV_NW4END0_2", "INT_INTERFACE_NW4END0" ], [ "CLK_PMV_NW4END1_2", "INT_INTERFACE_NW4END1" ], [ "CLK_PMV_NW4END2_2", "INT_INTERFACE_NW4END2" ], [ "CLK_PMV_NW4END3_2", "INT_INTERFACE_NW4END3" ], [ "CLK_PMV_SE2A0_2", "INT_INTERFACE_SE2A0" ], [ "CLK_PMV_SE2A1_2", "INT_INTERFACE_SE2A1" ], [ "CLK_PMV_SE2A2_2", "INT_INTERFACE_SE2A2" ], [ "CLK_PMV_SE2A3_2", "INT_INTERFACE_SE2A3" ], [ "CLK_PMV_SE4BEG0_2", "INT_INTERFACE_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_2", "INT_INTERFACE_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_2", "INT_INTERFACE_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_2", "INT_INTERFACE_SE4BEG3" ], [ "CLK_PMV_SE4C0_2", "INT_INTERFACE_SE4C0" ], [ "CLK_PMV_SE4C1_2", "INT_INTERFACE_SE4C1" ], [ "CLK_PMV_SE4C2_2", "INT_INTERFACE_SE4C2" ], [ "CLK_PMV_SE4C3_2", "INT_INTERFACE_SE4C3" ], [ "CLK_PMV_SW2A0_2", "INT_INTERFACE_SW2A0" ], [ "CLK_PMV_SW2A1_2", "INT_INTERFACE_SW2A1" ], [ "CLK_PMV_SW2A2_2", "INT_INTERFACE_SW2A2" ], [ "CLK_PMV_SW2A3_2", "INT_INTERFACE_SW2A3" ], [ "CLK_PMV_SW4A0_2", "INT_INTERFACE_SW4A0" ], [ "CLK_PMV_SW4A1_2", "INT_INTERFACE_SW4A1" ], [ "CLK_PMV_SW4A2_2", "INT_INTERFACE_SW4A2" ], [ "CLK_PMV_SW4A3_2", "INT_INTERFACE_SW4A3" ], [ "CLK_PMV_SW4END0_2", "INT_INTERFACE_SW4END0" ], [ "CLK_PMV_SW4END1_2", "INT_INTERFACE_SW4END1" ], [ "CLK_PMV_SW4END2_2", "INT_INTERFACE_SW4END2" ], [ "CLK_PMV_SW4END3_2", "INT_INTERFACE_SW4END3" ], [ "CLK_PMV_WL1END0_2", "INT_INTERFACE_WL1END0" ], [ "CLK_PMV_WL1END1_2", "INT_INTERFACE_WL1END1" ], [ "CLK_PMV_WL1END2_2", "INT_INTERFACE_WL1END2" ], [ "CLK_PMV_WL1END3_2", "INT_INTERFACE_WL1END3" ], [ "CLK_PMV_WR1END0_2", "INT_INTERFACE_WR1END0" ], [ "CLK_PMV_WR1END1_2", "INT_INTERFACE_WR1END1" ], [ "CLK_PMV_WR1END2_2", "INT_INTERFACE_WR1END2" ], [ "CLK_PMV_WR1END3_2", "INT_INTERFACE_WR1END3" ], [ "CLK_PMV_WW2A0_2", "INT_INTERFACE_WW2A0" ], [ "CLK_PMV_WW2A1_2", "INT_INTERFACE_WW2A1" ], [ "CLK_PMV_WW2A2_2", "INT_INTERFACE_WW2A2" ], [ "CLK_PMV_WW2A3_2", "INT_INTERFACE_WW2A3" ], [ "CLK_PMV_WW2END0_2", "INT_INTERFACE_WW2END0" ], [ "CLK_PMV_WW2END1_2", "INT_INTERFACE_WW2END1" ], [ "CLK_PMV_WW2END2_2", "INT_INTERFACE_WW2END2" ], [ "CLK_PMV_WW2END3_2", "INT_INTERFACE_WW2END3" ], [ "CLK_PMV_WW4A0_2", "INT_INTERFACE_WW4A0" ], [ "CLK_PMV_WW4A1_2", "INT_INTERFACE_WW4A1" ], [ "CLK_PMV_WW4A2_2", "INT_INTERFACE_WW4A2" ], [ "CLK_PMV_WW4A3_2", "INT_INTERFACE_WW4A3" ], [ "CLK_PMV_WW4B0_2", "INT_INTERFACE_WW4B0" ], [ "CLK_PMV_WW4B1_2", "INT_INTERFACE_WW4B1" ], [ "CLK_PMV_WW4B2_2", "INT_INTERFACE_WW4B2" ], [ "CLK_PMV_WW4B3_2", "INT_INTERFACE_WW4B3" ], [ "CLK_PMV_WW4C0_2", "INT_INTERFACE_WW4C0" ], [ "CLK_PMV_WW4C1_2", "INT_INTERFACE_WW4C1" ], [ "CLK_PMV_WW4C2_2", "INT_INTERFACE_WW4C2" ], [ "CLK_PMV_WW4C3_2", "INT_INTERFACE_WW4C3" ], [ "CLK_PMV_WW4END0_2", "INT_INTERFACE_WW4END0" ], [ "CLK_PMV_WW4END1_2", "INT_INTERFACE_WW4END1" ], [ "CLK_PMV_WW4END2_2", "INT_INTERFACE_WW4END2" ], [ "CLK_PMV_WW4END3_2", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, -1 ], "tile_types": [ "CLK_PMV", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_PMV_BYP0_1", "INT_INTERFACE_BYP0" ], [ "CLK_PMV_BYP1_1", "INT_INTERFACE_BYP1" ], [ "CLK_PMV_BYP2_1", "INT_INTERFACE_BYP2" ], [ "CLK_PMV_BYP3_1", "INT_INTERFACE_BYP3" ], [ "CLK_PMV_BYP4_1", "INT_INTERFACE_BYP4" ], [ "CLK_PMV_BYP5_1", "INT_INTERFACE_BYP5" ], [ "CLK_PMV_BYP6_1", "INT_INTERFACE_BYP6" ], [ "CLK_PMV_BYP7_1", "INT_INTERFACE_BYP7" ], [ "CLK_PMV_CLK0_1", "INT_INTERFACE_CLK0" ], [ "CLK_PMV_CLK1_1", "INT_INTERFACE_CLK1" ], [ "CLK_PMV_CTRL0_1", "INT_INTERFACE_CTRL0" ], [ "CLK_PMV_CTRL1_1", "INT_INTERFACE_CTRL1" ], [ "CLK_PMV_EE2A0_1", "INT_INTERFACE_EE2A0" ], [ "CLK_PMV_EE2A1_1", "INT_INTERFACE_EE2A1" ], [ "CLK_PMV_EE2A2_1", "INT_INTERFACE_EE2A2" ], [ "CLK_PMV_EE2A3_1", "INT_INTERFACE_EE2A3" ], [ "CLK_PMV_EE2BEG0_1", "INT_INTERFACE_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_1", "INT_INTERFACE_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_1", "INT_INTERFACE_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_1", "INT_INTERFACE_EE2BEG3" ], [ "CLK_PMV_EE4A0_1", "INT_INTERFACE_EE4A0" ], [ "CLK_PMV_EE4A1_1", "INT_INTERFACE_EE4A1" ], [ "CLK_PMV_EE4A2_1", "INT_INTERFACE_EE4A2" ], [ "CLK_PMV_EE4A3_1", "INT_INTERFACE_EE4A3" ], [ "CLK_PMV_EE4B0_1", "INT_INTERFACE_EE4B0" ], [ "CLK_PMV_EE4B1_1", "INT_INTERFACE_EE4B1" ], [ "CLK_PMV_EE4B2_1", "INT_INTERFACE_EE4B2" ], [ "CLK_PMV_EE4B3_1", "INT_INTERFACE_EE4B3" ], [ "CLK_PMV_EE4BEG0_1", "INT_INTERFACE_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_1", "INT_INTERFACE_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_1", "INT_INTERFACE_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_1", "INT_INTERFACE_EE4BEG3" ], [ "CLK_PMV_EE4C0_1", "INT_INTERFACE_EE4C0" ], [ "CLK_PMV_EE4C1_1", "INT_INTERFACE_EE4C1" ], [ "CLK_PMV_EE4C2_1", "INT_INTERFACE_EE4C2" ], [ "CLK_PMV_EE4C3_1", "INT_INTERFACE_EE4C3" ], [ "CLK_PMV_EL1BEG0_1", "INT_INTERFACE_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_1", "INT_INTERFACE_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_1", "INT_INTERFACE_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_1", "INT_INTERFACE_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_1", "INT_INTERFACE_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_1", "INT_INTERFACE_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_1", "INT_INTERFACE_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_1", "INT_INTERFACE_ER1BEG3" ], [ "CLK_PMV_FAN0_1", "INT_INTERFACE_FAN0" ], [ "CLK_PMV_FAN1_1", "INT_INTERFACE_FAN1" ], [ "CLK_PMV_FAN2_1", "INT_INTERFACE_FAN2" ], [ "CLK_PMV_FAN3_1", "INT_INTERFACE_FAN3" ], [ "CLK_PMV_FAN4_1", "INT_INTERFACE_FAN4" ], [ "CLK_PMV_FAN5_1", "INT_INTERFACE_FAN5" ], [ "CLK_PMV_FAN6_1", "INT_INTERFACE_FAN6" ], [ "CLK_PMV_FAN7_1", "INT_INTERFACE_FAN7" ], [ "CLK_PMV_IMUX0_1", "INT_INTERFACE_IMUX0" ], [ "CLK_PMV_IMUX1_1", "INT_INTERFACE_IMUX1" ], [ "CLK_PMV_IMUX2_1", "INT_INTERFACE_IMUX2" ], [ "CLK_PMV_IMUX3_1", "INT_INTERFACE_IMUX3" ], [ "CLK_PMV_IMUX4_1", "INT_INTERFACE_IMUX4" ], [ "CLK_PMV_IMUX5_1", "INT_INTERFACE_IMUX5" ], [ "CLK_PMV_IMUX6_1", "INT_INTERFACE_IMUX6" ], [ "CLK_PMV_IMUX7_1", "INT_INTERFACE_IMUX7" ], [ "CLK_PMV_IMUX8_1", "INT_INTERFACE_IMUX8" ], [ "CLK_PMV_IMUX9_1", "INT_INTERFACE_IMUX9" ], [ "CLK_PMV_IMUX10_1", "INT_INTERFACE_IMUX10" ], [ "CLK_PMV_IMUX11_1", "INT_INTERFACE_IMUX11" ], [ "CLK_PMV_IMUX12_1", "INT_INTERFACE_IMUX12" ], [ "CLK_PMV_IMUX13_1", "INT_INTERFACE_IMUX13" ], [ "CLK_PMV_IMUX14_1", "INT_INTERFACE_IMUX14" ], [ "CLK_PMV_IMUX15_1", "INT_INTERFACE_IMUX15" ], [ "CLK_PMV_IMUX16_1", "INT_INTERFACE_IMUX16" ], [ "CLK_PMV_IMUX17_1", "INT_INTERFACE_IMUX17" ], [ "CLK_PMV_IMUX18_1", "INT_INTERFACE_IMUX18" ], [ "CLK_PMV_IMUX19_1", "INT_INTERFACE_IMUX19" ], [ "CLK_PMV_IMUX20_1", "INT_INTERFACE_IMUX20" ], [ "CLK_PMV_IMUX21_1", "INT_INTERFACE_IMUX21" ], [ "CLK_PMV_IMUX22_1", "INT_INTERFACE_IMUX22" ], [ "CLK_PMV_IMUX23_1", "INT_INTERFACE_IMUX23" ], [ "CLK_PMV_IMUX24_1", "INT_INTERFACE_IMUX24" ], [ "CLK_PMV_IMUX25_1", "INT_INTERFACE_IMUX25" ], [ "CLK_PMV_IMUX26_1", "INT_INTERFACE_IMUX26" ], [ "CLK_PMV_IMUX27_1", "INT_INTERFACE_IMUX27" ], [ "CLK_PMV_IMUX28_1", "INT_INTERFACE_IMUX28" ], [ "CLK_PMV_IMUX29_1", "INT_INTERFACE_IMUX29" ], [ "CLK_PMV_IMUX30_1", "INT_INTERFACE_IMUX30" ], [ "CLK_PMV_IMUX31_1", "INT_INTERFACE_IMUX31" ], [ "CLK_PMV_IMUX32_1", "INT_INTERFACE_IMUX32" ], [ "CLK_PMV_IMUX33_1", "INT_INTERFACE_IMUX33" ], [ "CLK_PMV_IMUX34_1", "INT_INTERFACE_IMUX34" ], [ "CLK_PMV_IMUX35_1", "INT_INTERFACE_IMUX35" ], [ "CLK_PMV_IMUX36_1", "INT_INTERFACE_IMUX36" ], [ "CLK_PMV_IMUX37_1", "INT_INTERFACE_IMUX37" ], [ "CLK_PMV_IMUX38_1", "INT_INTERFACE_IMUX38" ], [ "CLK_PMV_IMUX39_1", "INT_INTERFACE_IMUX39" ], [ "CLK_PMV_IMUX40_1", "INT_INTERFACE_IMUX40" ], [ "CLK_PMV_IMUX41_1", "INT_INTERFACE_IMUX41" ], [ "CLK_PMV_IMUX42_1", "INT_INTERFACE_IMUX42" ], [ "CLK_PMV_IMUX43_1", "INT_INTERFACE_IMUX43" ], [ "CLK_PMV_IMUX44_1", "INT_INTERFACE_IMUX44" ], [ "CLK_PMV_IMUX45_1", "INT_INTERFACE_IMUX45" ], [ "CLK_PMV_IMUX46_1", "INT_INTERFACE_IMUX46" ], [ "CLK_PMV_IMUX47_1", "INT_INTERFACE_IMUX47" ], [ "CLK_PMV_LH1_1", "INT_INTERFACE_LH1" ], [ "CLK_PMV_LH2_1", "INT_INTERFACE_LH2" ], [ "CLK_PMV_LH3_1", "INT_INTERFACE_LH3" ], [ "CLK_PMV_LH4_1", "INT_INTERFACE_LH4" ], [ "CLK_PMV_LH5_1", "INT_INTERFACE_LH5" ], [ "CLK_PMV_LH6_1", "INT_INTERFACE_LH6" ], [ "CLK_PMV_LH7_1", "INT_INTERFACE_LH7" ], [ "CLK_PMV_LH8_1", "INT_INTERFACE_LH8" ], [ "CLK_PMV_LH9_1", "INT_INTERFACE_LH9" ], [ "CLK_PMV_LH10_1", "INT_INTERFACE_LH10" ], [ "CLK_PMV_LH11_1", "INT_INTERFACE_LH11" ], [ "CLK_PMV_LH12_1", "INT_INTERFACE_LH12" ], [ "CLK_PMV_NE2A0_1", "INT_INTERFACE_NE2A0" ], [ "CLK_PMV_NE2A1_1", "INT_INTERFACE_NE2A1" ], [ "CLK_PMV_NE2A2_1", "INT_INTERFACE_NE2A2" ], [ "CLK_PMV_NE2A3_1", "INT_INTERFACE_NE2A3" ], [ "CLK_PMV_NE4BEG0_1", "INT_INTERFACE_NE4BEG0" ], [ "CLK_PMV_NE4BEG1_1", "INT_INTERFACE_NE4BEG1" ], [ "CLK_PMV_NE4BEG2_1", "INT_INTERFACE_NE4BEG2" ], [ "CLK_PMV_NE4BEG3_1", "INT_INTERFACE_NE4BEG3" ], [ "CLK_PMV_NE4C0_1", "INT_INTERFACE_NE4C0" ], [ "CLK_PMV_NE4C1_1", "INT_INTERFACE_NE4C1" ], [ "CLK_PMV_NE4C2_1", "INT_INTERFACE_NE4C2" ], [ "CLK_PMV_NE4C3_1", "INT_INTERFACE_NE4C3" ], [ "CLK_PMV_NW2A0_1", "INT_INTERFACE_NW2A0" ], [ "CLK_PMV_NW2A1_1", "INT_INTERFACE_NW2A1" ], [ "CLK_PMV_NW2A2_1", "INT_INTERFACE_NW2A2" ], [ "CLK_PMV_NW2A3_1", "INT_INTERFACE_NW2A3" ], [ "CLK_PMV_NW4A0_1", "INT_INTERFACE_NW4A0" ], [ "CLK_PMV_NW4A1_1", "INT_INTERFACE_NW4A1" ], [ "CLK_PMV_NW4A2_1", "INT_INTERFACE_NW4A2" ], [ "CLK_PMV_NW4A3_1", "INT_INTERFACE_NW4A3" ], [ "CLK_PMV_NW4END0_1", "INT_INTERFACE_NW4END0" ], [ "CLK_PMV_NW4END1_1", "INT_INTERFACE_NW4END1" ], [ "CLK_PMV_NW4END2_1", "INT_INTERFACE_NW4END2" ], [ "CLK_PMV_NW4END3_1", "INT_INTERFACE_NW4END3" ], [ "CLK_PMV_SE2A0_1", "INT_INTERFACE_SE2A0" ], [ "CLK_PMV_SE2A1_1", "INT_INTERFACE_SE2A1" ], [ "CLK_PMV_SE2A2_1", "INT_INTERFACE_SE2A2" ], [ "CLK_PMV_SE2A3_1", "INT_INTERFACE_SE2A3" ], [ "CLK_PMV_SE4BEG0_1", "INT_INTERFACE_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_1", "INT_INTERFACE_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_1", "INT_INTERFACE_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_1", "INT_INTERFACE_SE4BEG3" ], [ "CLK_PMV_SE4C0_1", "INT_INTERFACE_SE4C0" ], [ "CLK_PMV_SE4C1_1", "INT_INTERFACE_SE4C1" ], [ "CLK_PMV_SE4C2_1", "INT_INTERFACE_SE4C2" ], [ "CLK_PMV_SE4C3_1", "INT_INTERFACE_SE4C3" ], [ "CLK_PMV_SW2A0_1", "INT_INTERFACE_SW2A0" ], [ "CLK_PMV_SW2A1_1", "INT_INTERFACE_SW2A1" ], [ "CLK_PMV_SW2A2_1", "INT_INTERFACE_SW2A2" ], [ "CLK_PMV_SW2A3_1", "INT_INTERFACE_SW2A3" ], [ "CLK_PMV_SW4A0_1", "INT_INTERFACE_SW4A0" ], [ "CLK_PMV_SW4A1_1", "INT_INTERFACE_SW4A1" ], [ "CLK_PMV_SW4A2_1", "INT_INTERFACE_SW4A2" ], [ "CLK_PMV_SW4A3_1", "INT_INTERFACE_SW4A3" ], [ "CLK_PMV_SW4END0_1", "INT_INTERFACE_SW4END0" ], [ "CLK_PMV_SW4END1_1", "INT_INTERFACE_SW4END1" ], [ "CLK_PMV_SW4END2_1", "INT_INTERFACE_SW4END2" ], [ "CLK_PMV_SW4END3_1", "INT_INTERFACE_SW4END3" ], [ "CLK_PMV_WL1END0_1", "INT_INTERFACE_WL1END0" ], [ "CLK_PMV_WL1END1_1", "INT_INTERFACE_WL1END1" ], [ "CLK_PMV_WL1END2_1", "INT_INTERFACE_WL1END2" ], [ "CLK_PMV_WL1END3_1", "INT_INTERFACE_WL1END3" ], [ "CLK_PMV_WR1END0_1", "INT_INTERFACE_WR1END0" ], [ "CLK_PMV_WR1END1_1", "INT_INTERFACE_WR1END1" ], [ "CLK_PMV_WR1END2_1", "INT_INTERFACE_WR1END2" ], [ "CLK_PMV_WR1END3_1", "INT_INTERFACE_WR1END3" ], [ "CLK_PMV_WW2A0_1", "INT_INTERFACE_WW2A0" ], [ "CLK_PMV_WW2A1_1", "INT_INTERFACE_WW2A1" ], [ "CLK_PMV_WW2A2_1", "INT_INTERFACE_WW2A2" ], [ "CLK_PMV_WW2A3_1", "INT_INTERFACE_WW2A3" ], [ "CLK_PMV_WW2END0_1", "INT_INTERFACE_WW2END0" ], [ "CLK_PMV_WW2END1_1", "INT_INTERFACE_WW2END1" ], [ "CLK_PMV_WW2END2_1", "INT_INTERFACE_WW2END2" ], [ "CLK_PMV_WW2END3_1", "INT_INTERFACE_WW2END3" ], [ "CLK_PMV_WW4A0_1", "INT_INTERFACE_WW4A0" ], [ "CLK_PMV_WW4A1_1", "INT_INTERFACE_WW4A1" ], [ "CLK_PMV_WW4A2_1", "INT_INTERFACE_WW4A2" ], [ "CLK_PMV_WW4A3_1", "INT_INTERFACE_WW4A3" ], [ "CLK_PMV_WW4B0_1", "INT_INTERFACE_WW4B0" ], [ "CLK_PMV_WW4B1_1", "INT_INTERFACE_WW4B1" ], [ "CLK_PMV_WW4B2_1", "INT_INTERFACE_WW4B2" ], [ "CLK_PMV_WW4B3_1", "INT_INTERFACE_WW4B3" ], [ "CLK_PMV_WW4C0_1", "INT_INTERFACE_WW4C0" ], [ "CLK_PMV_WW4C1_1", "INT_INTERFACE_WW4C1" ], [ "CLK_PMV_WW4C2_1", "INT_INTERFACE_WW4C2" ], [ "CLK_PMV_WW4C3_1", "INT_INTERFACE_WW4C3" ], [ "CLK_PMV_WW4END0_1", "INT_INTERFACE_WW4END0" ], [ "CLK_PMV_WW4END1_1", "INT_INTERFACE_WW4END1" ], [ "CLK_PMV_WW4END2_1", "INT_INTERFACE_WW4END2" ], [ "CLK_PMV_WW4END3_1", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "CLK_PMV", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_PMV_BYP0_0", "INT_INTERFACE_BYP0" ], [ "CLK_PMV_BYP1_0", "INT_INTERFACE_BYP1" ], [ "CLK_PMV_BYP2_0", "INT_INTERFACE_BYP2" ], [ "CLK_PMV_BYP3_0", "INT_INTERFACE_BYP3" ], [ "CLK_PMV_BYP4_0", "INT_INTERFACE_BYP4" ], [ "CLK_PMV_BYP5_0", "INT_INTERFACE_BYP5" ], [ "CLK_PMV_BYP6_0", "INT_INTERFACE_BYP6" ], [ "CLK_PMV_BYP7_0", "INT_INTERFACE_BYP7" ], [ "CLK_PMV_CLK0_0", "INT_INTERFACE_CLK0" ], [ "CLK_PMV_CLK1_0", "INT_INTERFACE_CLK1" ], [ "CLK_PMV_CTRL0_0", "INT_INTERFACE_CTRL0" ], [ "CLK_PMV_CTRL1_0", "INT_INTERFACE_CTRL1" ], [ "CLK_PMV_EE2A0_0", "INT_INTERFACE_EE2A0" ], [ "CLK_PMV_EE2A1_0", "INT_INTERFACE_EE2A1" ], [ "CLK_PMV_EE2A2_0", "INT_INTERFACE_EE2A2" ], [ "CLK_PMV_EE2A3_0", "INT_INTERFACE_EE2A3" ], [ "CLK_PMV_EE2BEG0_0", "INT_INTERFACE_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_0", "INT_INTERFACE_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_0", "INT_INTERFACE_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_0", "INT_INTERFACE_EE2BEG3" ], [ "CLK_PMV_EE4A0_0", "INT_INTERFACE_EE4A0" ], [ "CLK_PMV_EE4A1_0", "INT_INTERFACE_EE4A1" ], [ "CLK_PMV_EE4A2_0", "INT_INTERFACE_EE4A2" ], [ "CLK_PMV_EE4A3_0", "INT_INTERFACE_EE4A3" ], [ "CLK_PMV_EE4B0_0", "INT_INTERFACE_EE4B0" ], [ "CLK_PMV_EE4B1_0", "INT_INTERFACE_EE4B1" ], [ "CLK_PMV_EE4B2_0", "INT_INTERFACE_EE4B2" ], [ "CLK_PMV_EE4B3_0", "INT_INTERFACE_EE4B3" ], [ "CLK_PMV_EE4BEG0_0", "INT_INTERFACE_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_0", "INT_INTERFACE_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_0", "INT_INTERFACE_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_0", "INT_INTERFACE_EE4BEG3" ], [ "CLK_PMV_EE4C0_0", "INT_INTERFACE_EE4C0" ], [ "CLK_PMV_EE4C1_0", "INT_INTERFACE_EE4C1" ], [ "CLK_PMV_EE4C2_0", "INT_INTERFACE_EE4C2" ], [ "CLK_PMV_EE4C3_0", "INT_INTERFACE_EE4C3" ], [ "CLK_PMV_EL1BEG0_0", "INT_INTERFACE_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_0", "INT_INTERFACE_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_0", "INT_INTERFACE_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_0", "INT_INTERFACE_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_0", "INT_INTERFACE_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_0", "INT_INTERFACE_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_0", "INT_INTERFACE_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_0", "INT_INTERFACE_ER1BEG3" ], [ "CLK_PMV_FAN0_0", "INT_INTERFACE_FAN0" ], [ "CLK_PMV_FAN1_0", "INT_INTERFACE_FAN1" ], [ "CLK_PMV_FAN2_0", "INT_INTERFACE_FAN2" ], [ "CLK_PMV_FAN3_0", "INT_INTERFACE_FAN3" ], [ "CLK_PMV_FAN4_0", "INT_INTERFACE_FAN4" ], [ "CLK_PMV_FAN5_0", "INT_INTERFACE_FAN5" ], [ "CLK_PMV_FAN6_0", "INT_INTERFACE_FAN6" ], [ "CLK_PMV_FAN7_0", "INT_INTERFACE_FAN7" ], [ "CLK_PMV_IMUX0_0", "INT_INTERFACE_IMUX0" ], [ "CLK_PMV_IMUX1_0", "INT_INTERFACE_IMUX1" ], [ "CLK_PMV_IMUX2_0", "INT_INTERFACE_IMUX2" ], [ "CLK_PMV_IMUX3_0", "INT_INTERFACE_IMUX3" ], [ "CLK_PMV_IMUX4_0", "INT_INTERFACE_IMUX4" ], [ "CLK_PMV_IMUX5_0", "INT_INTERFACE_IMUX5" ], [ "CLK_PMV_IMUX6_0", "INT_INTERFACE_IMUX6" ], [ "CLK_PMV_IMUX7_0", "INT_INTERFACE_IMUX7" ], [ "CLK_PMV_IMUX8_0", "INT_INTERFACE_IMUX8" ], [ "CLK_PMV_IMUX9_0", "INT_INTERFACE_IMUX9" ], [ "CLK_PMV_IMUX10_0", "INT_INTERFACE_IMUX10" ], [ "CLK_PMV_IMUX11_0", "INT_INTERFACE_IMUX11" ], [ "CLK_PMV_IMUX12_0", "INT_INTERFACE_IMUX12" ], [ "CLK_PMV_IMUX13_0", "INT_INTERFACE_IMUX13" ], [ "CLK_PMV_IMUX14_0", "INT_INTERFACE_IMUX14" ], [ "CLK_PMV_IMUX15_0", "INT_INTERFACE_IMUX15" ], [ "CLK_PMV_IMUX16_0", "INT_INTERFACE_IMUX16" ], [ "CLK_PMV_IMUX17_0", "INT_INTERFACE_IMUX17" ], [ "CLK_PMV_IMUX18_0", "INT_INTERFACE_IMUX18" ], [ "CLK_PMV_IMUX19_0", "INT_INTERFACE_IMUX19" ], [ "CLK_PMV_IMUX20_0", "INT_INTERFACE_IMUX20" ], [ "CLK_PMV_IMUX21_0", "INT_INTERFACE_IMUX21" ], [ "CLK_PMV_IMUX22_0", "INT_INTERFACE_IMUX22" ], [ "CLK_PMV_IMUX23_0", "INT_INTERFACE_IMUX23" ], [ "CLK_PMV_IMUX24_0", "INT_INTERFACE_IMUX24" ], [ "CLK_PMV_IMUX25_0", "INT_INTERFACE_IMUX25" ], [ "CLK_PMV_IMUX26_0", "INT_INTERFACE_IMUX26" ], [ "CLK_PMV_IMUX27_0", "INT_INTERFACE_IMUX27" ], [ "CLK_PMV_IMUX28_0", "INT_INTERFACE_IMUX28" ], [ "CLK_PMV_IMUX29_0", "INT_INTERFACE_IMUX29" ], [ "CLK_PMV_IMUX30_0", "INT_INTERFACE_IMUX30" ], [ "CLK_PMV_IMUX31_0", "INT_INTERFACE_IMUX31" ], [ "CLK_PMV_IMUX32_0", "INT_INTERFACE_IMUX32" ], [ "CLK_PMV_IMUX33_0", "INT_INTERFACE_IMUX33" ], [ "CLK_PMV_IMUX34_0", "INT_INTERFACE_IMUX34" ], [ "CLK_PMV_IMUX35_0", "INT_INTERFACE_IMUX35" ], [ "CLK_PMV_IMUX36_0", "INT_INTERFACE_IMUX36" ], [ "CLK_PMV_IMUX37_0", "INT_INTERFACE_IMUX37" ], [ "CLK_PMV_IMUX38_0", "INT_INTERFACE_IMUX38" ], [ "CLK_PMV_IMUX39_0", "INT_INTERFACE_IMUX39" ], [ "CLK_PMV_IMUX40_0", "INT_INTERFACE_IMUX40" ], [ "CLK_PMV_IMUX41_0", "INT_INTERFACE_IMUX41" ], [ "CLK_PMV_IMUX42_0", "INT_INTERFACE_IMUX42" ], [ "CLK_PMV_IMUX43_0", "INT_INTERFACE_IMUX43" ], [ "CLK_PMV_IMUX44_0", "INT_INTERFACE_IMUX44" ], [ "CLK_PMV_IMUX45_0", "INT_INTERFACE_IMUX45" ], [ "CLK_PMV_IMUX46_0", "INT_INTERFACE_IMUX46" ], [ "CLK_PMV_IMUX47_0", "INT_INTERFACE_IMUX47" ], [ "CLK_PMV_LH1_0", "INT_INTERFACE_LH1" ], [ "CLK_PMV_LH2_0", "INT_INTERFACE_LH2" ], [ "CLK_PMV_LH3_0", "INT_INTERFACE_LH3" ], [ "CLK_PMV_LH4_0", "INT_INTERFACE_LH4" ], [ "CLK_PMV_LH5_0", "INT_INTERFACE_LH5" ], [ "CLK_PMV_LH6_0", "INT_INTERFACE_LH6" ], [ "CLK_PMV_LH7_0", "INT_INTERFACE_LH7" ], [ "CLK_PMV_LH8_0", "INT_INTERFACE_LH8" ], [ "CLK_PMV_LH9_0", "INT_INTERFACE_LH9" ], [ "CLK_PMV_LH10_0", "INT_INTERFACE_LH10" ], [ "CLK_PMV_LH11_0", "INT_INTERFACE_LH11" ], [ "CLK_PMV_LH12_0", "INT_INTERFACE_LH12" ], [ "CLK_PMV_MONITOR_N_0", "INT_INTERFACE_MONITOR_N" ], [ "CLK_PMV_MONITOR_P_0", "INT_INTERFACE_MONITOR_P" ], [ "CLK_PMV_NE2A0_0", "INT_INTERFACE_NE2A0" ], [ "CLK_PMV_NE2A1_0", "INT_INTERFACE_NE2A1" ], [ "CLK_PMV_NE2A2_0", "INT_INTERFACE_NE2A2" ], [ "CLK_PMV_NE2A3_0", "INT_INTERFACE_NE2A3" ], [ "CLK_PMV_NE4BEG0_0", "INT_INTERFACE_NE4BEG0" ], [ "CLK_PMV_NE4BEG1_0", "INT_INTERFACE_NE4BEG1" ], [ "CLK_PMV_NE4BEG2_0", "INT_INTERFACE_NE4BEG2" ], [ "CLK_PMV_NE4BEG3_0", "INT_INTERFACE_NE4BEG3" ], [ "CLK_PMV_NE4C0_0", "INT_INTERFACE_NE4C0" ], [ "CLK_PMV_NE4C1_0", "INT_INTERFACE_NE4C1" ], [ "CLK_PMV_NE4C2_0", "INT_INTERFACE_NE4C2" ], [ "CLK_PMV_NE4C3_0", "INT_INTERFACE_NE4C3" ], [ "CLK_PMV_NW2A0_0", "INT_INTERFACE_NW2A0" ], [ "CLK_PMV_NW2A1_0", "INT_INTERFACE_NW2A1" ], [ "CLK_PMV_NW2A2_0", "INT_INTERFACE_NW2A2" ], [ "CLK_PMV_NW2A3_0", "INT_INTERFACE_NW2A3" ], [ "CLK_PMV_NW4A0_0", "INT_INTERFACE_NW4A0" ], [ "CLK_PMV_NW4A1_0", "INT_INTERFACE_NW4A1" ], [ "CLK_PMV_NW4A2_0", "INT_INTERFACE_NW4A2" ], [ "CLK_PMV_NW4A3_0", "INT_INTERFACE_NW4A3" ], [ "CLK_PMV_NW4END0_0", "INT_INTERFACE_NW4END0" ], [ "CLK_PMV_NW4END1_0", "INT_INTERFACE_NW4END1" ], [ "CLK_PMV_NW4END2_0", "INT_INTERFACE_NW4END2" ], [ "CLK_PMV_NW4END3_0", "INT_INTERFACE_NW4END3" ], [ "CLK_PMV_SE2A0_0", "INT_INTERFACE_SE2A0" ], [ "CLK_PMV_SE2A1_0", "INT_INTERFACE_SE2A1" ], [ "CLK_PMV_SE2A2_0", "INT_INTERFACE_SE2A2" ], [ "CLK_PMV_SE2A3_0", "INT_INTERFACE_SE2A3" ], [ "CLK_PMV_SE4BEG0_0", "INT_INTERFACE_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_0", "INT_INTERFACE_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_0", "INT_INTERFACE_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_0", "INT_INTERFACE_SE4BEG3" ], [ "CLK_PMV_SE4C0_0", "INT_INTERFACE_SE4C0" ], [ "CLK_PMV_SE4C1_0", "INT_INTERFACE_SE4C1" ], [ "CLK_PMV_SE4C2_0", "INT_INTERFACE_SE4C2" ], [ "CLK_PMV_SE4C3_0", "INT_INTERFACE_SE4C3" ], [ "CLK_PMV_SW2A0_0", "INT_INTERFACE_SW2A0" ], [ "CLK_PMV_SW2A1_0", "INT_INTERFACE_SW2A1" ], [ "CLK_PMV_SW2A2_0", "INT_INTERFACE_SW2A2" ], [ "CLK_PMV_SW2A3_0", "INT_INTERFACE_SW2A3" ], [ "CLK_PMV_SW4A0_0", "INT_INTERFACE_SW4A0" ], [ "CLK_PMV_SW4A1_0", "INT_INTERFACE_SW4A1" ], [ "CLK_PMV_SW4A2_0", "INT_INTERFACE_SW4A2" ], [ "CLK_PMV_SW4A3_0", "INT_INTERFACE_SW4A3" ], [ "CLK_PMV_SW4END0_0", "INT_INTERFACE_SW4END0" ], [ "CLK_PMV_SW4END1_0", "INT_INTERFACE_SW4END1" ], [ "CLK_PMV_SW4END2_0", "INT_INTERFACE_SW4END2" ], [ "CLK_PMV_SW4END3_0", "INT_INTERFACE_SW4END3" ], [ "CLK_PMV_WL1END0_0", "INT_INTERFACE_WL1END0" ], [ "CLK_PMV_WL1END1_0", "INT_INTERFACE_WL1END1" ], [ "CLK_PMV_WL1END2_0", "INT_INTERFACE_WL1END2" ], [ "CLK_PMV_WL1END3_0", "INT_INTERFACE_WL1END3" ], [ "CLK_PMV_WR1END0_0", "INT_INTERFACE_WR1END0" ], [ "CLK_PMV_WR1END1_0", "INT_INTERFACE_WR1END1" ], [ "CLK_PMV_WR1END2_0", "INT_INTERFACE_WR1END2" ], [ "CLK_PMV_WR1END3_0", "INT_INTERFACE_WR1END3" ], [ "CLK_PMV_WW2A0_0", "INT_INTERFACE_WW2A0" ], [ "CLK_PMV_WW2A1_0", "INT_INTERFACE_WW2A1" ], [ "CLK_PMV_WW2A2_0", "INT_INTERFACE_WW2A2" ], [ "CLK_PMV_WW2A3_0", "INT_INTERFACE_WW2A3" ], [ "CLK_PMV_WW2END0_0", "INT_INTERFACE_WW2END0" ], [ "CLK_PMV_WW2END1_0", "INT_INTERFACE_WW2END1" ], [ "CLK_PMV_WW2END2_0", "INT_INTERFACE_WW2END2" ], [ "CLK_PMV_WW2END3_0", "INT_INTERFACE_WW2END3" ], [ "CLK_PMV_WW4A0_0", "INT_INTERFACE_WW4A0" ], [ "CLK_PMV_WW4A1_0", "INT_INTERFACE_WW4A1" ], [ "CLK_PMV_WW4A2_0", "INT_INTERFACE_WW4A2" ], [ "CLK_PMV_WW4A3_0", "INT_INTERFACE_WW4A3" ], [ "CLK_PMV_WW4B0_0", "INT_INTERFACE_WW4B0" ], [ "CLK_PMV_WW4B1_0", "INT_INTERFACE_WW4B1" ], [ "CLK_PMV_WW4B2_0", "INT_INTERFACE_WW4B2" ], [ "CLK_PMV_WW4B3_0", "INT_INTERFACE_WW4B3" ], [ "CLK_PMV_WW4C0_0", "INT_INTERFACE_WW4C0" ], [ "CLK_PMV_WW4C1_0", "INT_INTERFACE_WW4C1" ], [ "CLK_PMV_WW4C2_0", "INT_INTERFACE_WW4C2" ], [ "CLK_PMV_WW4C3_0", "INT_INTERFACE_WW4C3" ], [ "CLK_PMV_WW4END0_0", "INT_INTERFACE_WW4END0" ], [ "CLK_PMV_WW4END1_0", "INT_INTERFACE_WW4END1" ], [ "CLK_PMV_WW4END2_0", "INT_INTERFACE_WW4END2" ], [ "CLK_PMV_WW4END3_0", "INT_INTERFACE_WW4END3" ] ] }, { "grid_deltas": [ 1, -6 ], "tile_types": [ "CLK_PMV", "VBRK" ], "wire_pairs": [ [ "CLK_PMV_EE2A0_6", "VBRK_EE2A0" ], [ "CLK_PMV_EE2A1_6", "VBRK_EE2A1" ], [ "CLK_PMV_EE2A2_6", "VBRK_EE2A2" ], [ "CLK_PMV_EE2A3_6", "VBRK_EE2A3" ], [ "CLK_PMV_EE2BEG0_6", "VBRK_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_6", "VBRK_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_6", "VBRK_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_6", "VBRK_EE2BEG3" ], [ "CLK_PMV_EE4A0_6", "VBRK_EE4A0" ], [ "CLK_PMV_EE4A1_6", "VBRK_EE4A1" ], [ "CLK_PMV_EE4A2_6", "VBRK_EE4A2" ], [ "CLK_PMV_EE4A3_6", "VBRK_EE4A3" ], [ "CLK_PMV_EE4B0_6", "VBRK_EE4B0" ], [ "CLK_PMV_EE4B1_6", "VBRK_EE4B1" ], [ "CLK_PMV_EE4B2_6", "VBRK_EE4B2" ], [ "CLK_PMV_EE4B3_6", "VBRK_EE4B3" ], [ "CLK_PMV_EE4BEG0_6", "VBRK_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_6", "VBRK_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_6", "VBRK_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_6", "VBRK_EE4BEG3" ], [ "CLK_PMV_EE4C0_6", "VBRK_EE4C0" ], [ "CLK_PMV_EE4C1_6", "VBRK_EE4C1" ], [ "CLK_PMV_EE4C2_6", "VBRK_EE4C2" ], [ "CLK_PMV_EE4C3_6", "VBRK_EE4C3" ], [ "CLK_PMV_EL1BEG0_6", "VBRK_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_6", "VBRK_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_6", "VBRK_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_6", "VBRK_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_6", "VBRK_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_6", "VBRK_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_6", "VBRK_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_6", "VBRK_ER1BEG3" ], [ "CLK_PMV_LH1_6", "VBRK_LH1" ], [ "CLK_PMV_LH2_6", "VBRK_LH2" ], [ "CLK_PMV_LH3_6", "VBRK_LH3" ], [ "CLK_PMV_LH4_6", "VBRK_LH4" ], [ "CLK_PMV_LH5_6", "VBRK_LH5" ], [ "CLK_PMV_LH6_6", "VBRK_LH6" ], [ "CLK_PMV_LH7_6", "VBRK_LH7" ], [ "CLK_PMV_LH8_6", "VBRK_LH8" ], [ "CLK_PMV_LH9_6", "VBRK_LH9" ], [ "CLK_PMV_LH10_6", "VBRK_LH10" ], [ "CLK_PMV_LH11_6", "VBRK_LH11" ], [ "CLK_PMV_LH12_6", "VBRK_LH12" ], [ "CLK_PMV_MONITOR_N_6", "VBRK_MONITOR_N" ], [ "CLK_PMV_MONITOR_P_6", "VBRK_MONITOR_P" ], [ "CLK_PMV_NE2A0_6", "VBRK_NE2A0" ], [ "CLK_PMV_NE2A1_6", "VBRK_NE2A1" ], [ "CLK_PMV_NE2A2_6", "VBRK_NE2A2" ], [ "CLK_PMV_NE2A3_6", "VBRK_NE2A3" ], [ "CLK_PMV_NE4BEG0_6", "VBRK_NE4BEG0" ], [ "CLK_PMV_NE4BEG1_6", "VBRK_NE4BEG1" ], [ "CLK_PMV_NE4BEG2_6", "VBRK_NE4BEG2" ], [ "CLK_PMV_NE4BEG3_6", "VBRK_NE4BEG3" ], [ "CLK_PMV_NE4C0_6", "VBRK_NE4C0" ], [ "CLK_PMV_NE4C1_6", "VBRK_NE4C1" ], [ "CLK_PMV_NE4C2_6", "VBRK_NE4C2" ], [ "CLK_PMV_NE4C3_6", "VBRK_NE4C3" ], [ "CLK_PMV_NW2A0_6", "VBRK_NW2A0" ], [ "CLK_PMV_NW2A1_6", "VBRK_NW2A1" ], [ "CLK_PMV_NW2A2_6", "VBRK_NW2A2" ], [ "CLK_PMV_NW2A3_6", "VBRK_NW2A3" ], [ "CLK_PMV_NW4A0_6", "VBRK_NW4A0" ], [ "CLK_PMV_NW4A1_6", "VBRK_NW4A1" ], [ "CLK_PMV_NW4A2_6", "VBRK_NW4A2" ], [ "CLK_PMV_NW4A3_6", "VBRK_NW4A3" ], [ "CLK_PMV_NW4END0_6", "VBRK_NW4END0" ], [ "CLK_PMV_NW4END1_6", "VBRK_NW4END1" ], [ "CLK_PMV_NW4END2_6", "VBRK_NW4END2" ], [ "CLK_PMV_NW4END3_6", "VBRK_NW4END3" ], [ "CLK_PMV_SE2A0_6", "VBRK_SE2A0" ], [ "CLK_PMV_SE2A1_6", "VBRK_SE2A1" ], [ "CLK_PMV_SE2A2_6", "VBRK_SE2A2" ], [ "CLK_PMV_SE2A3_6", "VBRK_SE2A3" ], [ "CLK_PMV_SE4BEG0_6", "VBRK_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_6", "VBRK_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_6", "VBRK_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_6", "VBRK_SE4BEG3" ], [ "CLK_PMV_SE4C0_6", "VBRK_SE4C0" ], [ "CLK_PMV_SE4C1_6", "VBRK_SE4C1" ], [ "CLK_PMV_SE4C2_6", "VBRK_SE4C2" ], [ "CLK_PMV_SE4C3_6", "VBRK_SE4C3" ], [ "CLK_PMV_SW2A0_6", "VBRK_SW2A0" ], [ "CLK_PMV_SW2A1_6", "VBRK_SW2A1" ], [ "CLK_PMV_SW2A2_6", "VBRK_SW2A2" ], [ "CLK_PMV_SW2A3_6", "VBRK_SW2A3" ], [ "CLK_PMV_SW4A0_6", "VBRK_SW4A0" ], [ "CLK_PMV_SW4A1_6", "VBRK_SW4A1" ], [ "CLK_PMV_SW4A2_6", "VBRK_SW4A2" ], [ "CLK_PMV_SW4A3_6", "VBRK_SW4A3" ], [ "CLK_PMV_SW4END0_6", "VBRK_SW4END0" ], [ "CLK_PMV_SW4END1_6", "VBRK_SW4END1" ], [ "CLK_PMV_SW4END2_6", "VBRK_SW4END2" ], [ "CLK_PMV_SW4END3_6", "VBRK_SW4END3" ], [ "CLK_PMV_WL1END0_6", "VBRK_WL1END0" ], [ "CLK_PMV_WL1END1_6", "VBRK_WL1END1" ], [ "CLK_PMV_WL1END2_6", "VBRK_WL1END2" ], [ "CLK_PMV_WL1END3_6", "VBRK_WL1END3" ], [ "CLK_PMV_WR1END0_6", "VBRK_WR1END0" ], [ "CLK_PMV_WR1END1_6", "VBRK_WR1END1" ], [ "CLK_PMV_WR1END2_6", "VBRK_WR1END2" ], [ "CLK_PMV_WR1END3_6", "VBRK_WR1END3" ], [ "CLK_PMV_WW2A0_6", "VBRK_WW2A0" ], [ "CLK_PMV_WW2A1_6", "VBRK_WW2A1" ], [ "CLK_PMV_WW2A2_6", "VBRK_WW2A2" ], [ "CLK_PMV_WW2A3_6", "VBRK_WW2A3" ], [ "CLK_PMV_WW2END0_6", "VBRK_WW2END0" ], [ "CLK_PMV_WW2END1_6", "VBRK_WW2END1" ], [ "CLK_PMV_WW2END2_6", "VBRK_WW2END2" ], [ "CLK_PMV_WW2END3_6", "VBRK_WW2END3" ], [ "CLK_PMV_WW4A0_6", "VBRK_WW4A0" ], [ "CLK_PMV_WW4A1_6", "VBRK_WW4A1" ], [ "CLK_PMV_WW4A2_6", "VBRK_WW4A2" ], [ "CLK_PMV_WW4A3_6", "VBRK_WW4A3" ], [ "CLK_PMV_WW4B0_6", "VBRK_WW4B0" ], [ "CLK_PMV_WW4B1_6", "VBRK_WW4B1" ], [ "CLK_PMV_WW4B2_6", "VBRK_WW4B2" ], [ "CLK_PMV_WW4B3_6", "VBRK_WW4B3" ], [ "CLK_PMV_WW4C0_6", "VBRK_WW4C0" ], [ "CLK_PMV_WW4C1_6", "VBRK_WW4C1" ], [ "CLK_PMV_WW4C2_6", "VBRK_WW4C2" ], [ "CLK_PMV_WW4C3_6", "VBRK_WW4C3" ], [ "CLK_PMV_WW4END0_6", "VBRK_WW4END0" ], [ "CLK_PMV_WW4END1_6", "VBRK_WW4END1" ], [ "CLK_PMV_WW4END2_6", "VBRK_WW4END2" ], [ "CLK_PMV_WW4END3_6", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -5 ], "tile_types": [ "CLK_PMV", "VBRK" ], "wire_pairs": [ [ "CLK_PMV_EE2A0_5", "VBRK_EE2A0" ], [ "CLK_PMV_EE2A1_5", "VBRK_EE2A1" ], [ "CLK_PMV_EE2A2_5", "VBRK_EE2A2" ], [ "CLK_PMV_EE2A3_5", "VBRK_EE2A3" ], [ "CLK_PMV_EE2BEG0_5", "VBRK_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_5", "VBRK_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_5", "VBRK_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_5", "VBRK_EE2BEG3" ], [ "CLK_PMV_EE4A0_5", "VBRK_EE4A0" ], [ "CLK_PMV_EE4A1_5", "VBRK_EE4A1" ], [ "CLK_PMV_EE4A2_5", "VBRK_EE4A2" ], [ "CLK_PMV_EE4A3_5", "VBRK_EE4A3" ], [ "CLK_PMV_EE4B0_5", "VBRK_EE4B0" ], [ "CLK_PMV_EE4B1_5", "VBRK_EE4B1" ], [ "CLK_PMV_EE4B2_5", "VBRK_EE4B2" ], [ "CLK_PMV_EE4B3_5", "VBRK_EE4B3" ], [ "CLK_PMV_EE4BEG0_5", "VBRK_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_5", "VBRK_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_5", "VBRK_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_5", "VBRK_EE4BEG3" ], [ "CLK_PMV_EE4C0_5", "VBRK_EE4C0" ], [ "CLK_PMV_EE4C1_5", "VBRK_EE4C1" ], [ "CLK_PMV_EE4C2_5", "VBRK_EE4C2" ], [ "CLK_PMV_EE4C3_5", "VBRK_EE4C3" ], [ "CLK_PMV_EL1BEG0_5", "VBRK_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_5", "VBRK_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_5", "VBRK_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_5", "VBRK_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_5", "VBRK_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_5", "VBRK_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_5", "VBRK_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_5", "VBRK_ER1BEG3" ], [ "CLK_PMV_LH1_5", "VBRK_LH1" ], [ "CLK_PMV_LH2_5", "VBRK_LH2" ], [ "CLK_PMV_LH3_5", "VBRK_LH3" ], [ "CLK_PMV_LH4_5", "VBRK_LH4" ], [ "CLK_PMV_LH5_5", "VBRK_LH5" ], [ "CLK_PMV_LH6_5", "VBRK_LH6" ], [ "CLK_PMV_LH7_5", "VBRK_LH7" ], [ "CLK_PMV_LH8_5", "VBRK_LH8" ], [ "CLK_PMV_LH9_5", "VBRK_LH9" ], [ "CLK_PMV_LH10_5", "VBRK_LH10" ], [ "CLK_PMV_LH11_5", "VBRK_LH11" ], [ "CLK_PMV_LH12_5", "VBRK_LH12" ], [ "CLK_PMV_NE2A0_5", "VBRK_NE2A0" ], [ "CLK_PMV_NE2A1_5", "VBRK_NE2A1" ], [ "CLK_PMV_NE2A2_5", "VBRK_NE2A2" ], [ "CLK_PMV_NE2A3_5", "VBRK_NE2A3" ], [ "CLK_PMV_NE4BEG0_5", "VBRK_NE4BEG0" ], [ "CLK_PMV_NE4BEG1_5", "VBRK_NE4BEG1" ], [ "CLK_PMV_NE4BEG2_5", "VBRK_NE4BEG2" ], [ "CLK_PMV_NE4BEG3_5", "VBRK_NE4BEG3" ], [ "CLK_PMV_NE4C0_5", "VBRK_NE4C0" ], [ "CLK_PMV_NE4C1_5", "VBRK_NE4C1" ], [ "CLK_PMV_NE4C2_5", "VBRK_NE4C2" ], [ "CLK_PMV_NE4C3_5", "VBRK_NE4C3" ], [ "CLK_PMV_NW2A0_5", "VBRK_NW2A0" ], [ "CLK_PMV_NW2A1_5", "VBRK_NW2A1" ], [ "CLK_PMV_NW2A2_5", "VBRK_NW2A2" ], [ "CLK_PMV_NW2A3_5", "VBRK_NW2A3" ], [ "CLK_PMV_NW4A0_5", "VBRK_NW4A0" ], [ "CLK_PMV_NW4A1_5", "VBRK_NW4A1" ], [ "CLK_PMV_NW4A2_5", "VBRK_NW4A2" ], [ "CLK_PMV_NW4A3_5", "VBRK_NW4A3" ], [ "CLK_PMV_NW4END0_5", "VBRK_NW4END0" ], [ "CLK_PMV_NW4END1_5", "VBRK_NW4END1" ], [ "CLK_PMV_NW4END2_5", "VBRK_NW4END2" ], [ "CLK_PMV_NW4END3_5", "VBRK_NW4END3" ], [ "CLK_PMV_SE2A0_5", "VBRK_SE2A0" ], [ "CLK_PMV_SE2A1_5", "VBRK_SE2A1" ], [ "CLK_PMV_SE2A2_5", "VBRK_SE2A2" ], [ "CLK_PMV_SE2A3_5", "VBRK_SE2A3" ], [ "CLK_PMV_SE4BEG0_5", "VBRK_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_5", "VBRK_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_5", "VBRK_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_5", "VBRK_SE4BEG3" ], [ "CLK_PMV_SE4C0_5", "VBRK_SE4C0" ], [ "CLK_PMV_SE4C1_5", "VBRK_SE4C1" ], [ "CLK_PMV_SE4C2_5", "VBRK_SE4C2" ], [ "CLK_PMV_SE4C3_5", "VBRK_SE4C3" ], [ "CLK_PMV_SW2A0_5", "VBRK_SW2A0" ], [ "CLK_PMV_SW2A1_5", "VBRK_SW2A1" ], [ "CLK_PMV_SW2A2_5", "VBRK_SW2A2" ], [ "CLK_PMV_SW2A3_5", "VBRK_SW2A3" ], [ "CLK_PMV_SW4A0_5", "VBRK_SW4A0" ], [ "CLK_PMV_SW4A1_5", "VBRK_SW4A1" ], [ "CLK_PMV_SW4A2_5", "VBRK_SW4A2" ], [ "CLK_PMV_SW4A3_5", "VBRK_SW4A3" ], [ "CLK_PMV_SW4END0_5", "VBRK_SW4END0" ], [ "CLK_PMV_SW4END1_5", "VBRK_SW4END1" ], [ "CLK_PMV_SW4END2_5", "VBRK_SW4END2" ], [ "CLK_PMV_SW4END3_5", "VBRK_SW4END3" ], [ "CLK_PMV_WL1END0_5", "VBRK_WL1END0" ], [ "CLK_PMV_WL1END1_5", "VBRK_WL1END1" ], [ "CLK_PMV_WL1END2_5", "VBRK_WL1END2" ], [ "CLK_PMV_WL1END3_5", "VBRK_WL1END3" ], [ "CLK_PMV_WR1END0_5", "VBRK_WR1END0" ], [ "CLK_PMV_WR1END1_5", "VBRK_WR1END1" ], [ "CLK_PMV_WR1END2_5", "VBRK_WR1END2" ], [ "CLK_PMV_WR1END3_5", "VBRK_WR1END3" ], [ "CLK_PMV_WW2A0_5", "VBRK_WW2A0" ], [ "CLK_PMV_WW2A1_5", "VBRK_WW2A1" ], [ "CLK_PMV_WW2A2_5", "VBRK_WW2A2" ], [ "CLK_PMV_WW2A3_5", "VBRK_WW2A3" ], [ "CLK_PMV_WW2END0_5", "VBRK_WW2END0" ], [ "CLK_PMV_WW2END1_5", "VBRK_WW2END1" ], [ "CLK_PMV_WW2END2_5", "VBRK_WW2END2" ], [ "CLK_PMV_WW2END3_5", "VBRK_WW2END3" ], [ "CLK_PMV_WW4A0_5", "VBRK_WW4A0" ], [ "CLK_PMV_WW4A1_5", "VBRK_WW4A1" ], [ "CLK_PMV_WW4A2_5", "VBRK_WW4A2" ], [ "CLK_PMV_WW4A3_5", "VBRK_WW4A3" ], [ "CLK_PMV_WW4B0_5", "VBRK_WW4B0" ], [ "CLK_PMV_WW4B1_5", "VBRK_WW4B1" ], [ "CLK_PMV_WW4B2_5", "VBRK_WW4B2" ], [ "CLK_PMV_WW4B3_5", "VBRK_WW4B3" ], [ "CLK_PMV_WW4C0_5", "VBRK_WW4C0" ], [ "CLK_PMV_WW4C1_5", "VBRK_WW4C1" ], [ "CLK_PMV_WW4C2_5", "VBRK_WW4C2" ], [ "CLK_PMV_WW4C3_5", "VBRK_WW4C3" ], [ "CLK_PMV_WW4END0_5", "VBRK_WW4END0" ], [ "CLK_PMV_WW4END1_5", "VBRK_WW4END1" ], [ "CLK_PMV_WW4END2_5", "VBRK_WW4END2" ], [ "CLK_PMV_WW4END3_5", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -4 ], "tile_types": [ "CLK_PMV", "VBRK" ], "wire_pairs": [ [ "CLK_PMV_EE2A0_4", "VBRK_EE2A0" ], [ "CLK_PMV_EE2A1_4", "VBRK_EE2A1" ], [ "CLK_PMV_EE2A2_4", "VBRK_EE2A2" ], [ "CLK_PMV_EE2A3_4", "VBRK_EE2A3" ], [ "CLK_PMV_EE2BEG0_4", "VBRK_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_4", "VBRK_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_4", "VBRK_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_4", "VBRK_EE2BEG3" ], [ "CLK_PMV_EE4A0_4", "VBRK_EE4A0" ], [ "CLK_PMV_EE4A1_4", "VBRK_EE4A1" ], [ "CLK_PMV_EE4A2_4", "VBRK_EE4A2" ], [ "CLK_PMV_EE4A3_4", "VBRK_EE4A3" ], [ "CLK_PMV_EE4B0_4", "VBRK_EE4B0" ], [ "CLK_PMV_EE4B1_4", "VBRK_EE4B1" ], [ "CLK_PMV_EE4B2_4", "VBRK_EE4B2" ], [ "CLK_PMV_EE4B3_4", "VBRK_EE4B3" ], [ "CLK_PMV_EE4BEG0_4", "VBRK_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_4", "VBRK_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_4", "VBRK_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_4", "VBRK_EE4BEG3" ], [ "CLK_PMV_EE4C0_4", "VBRK_EE4C0" ], [ "CLK_PMV_EE4C1_4", "VBRK_EE4C1" ], [ "CLK_PMV_EE4C2_4", "VBRK_EE4C2" ], [ "CLK_PMV_EE4C3_4", "VBRK_EE4C3" ], [ "CLK_PMV_EL1BEG0_4", "VBRK_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_4", "VBRK_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_4", "VBRK_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_4", "VBRK_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_4", "VBRK_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_4", "VBRK_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_4", "VBRK_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_4", "VBRK_ER1BEG3" ], [ "CLK_PMV_LH1_4", "VBRK_LH1" ], [ "CLK_PMV_LH2_4", "VBRK_LH2" ], [ "CLK_PMV_LH3_4", "VBRK_LH3" ], [ "CLK_PMV_LH4_4", "VBRK_LH4" ], [ "CLK_PMV_LH5_4", "VBRK_LH5" ], [ "CLK_PMV_LH6_4", "VBRK_LH6" ], [ "CLK_PMV_LH7_4", "VBRK_LH7" ], [ "CLK_PMV_LH8_4", "VBRK_LH8" ], [ "CLK_PMV_LH9_4", "VBRK_LH9" ], [ "CLK_PMV_LH10_4", "VBRK_LH10" ], [ "CLK_PMV_LH11_4", "VBRK_LH11" ], [ "CLK_PMV_LH12_4", "VBRK_LH12" ], [ "CLK_PMV_MONITOR_N_4", "VBRK_MONITOR_N" ], [ "CLK_PMV_MONITOR_P_4", "VBRK_MONITOR_P" ], [ "CLK_PMV_NE2A0_4", "VBRK_NE2A0" ], [ "CLK_PMV_NE2A1_4", "VBRK_NE2A1" ], [ "CLK_PMV_NE2A2_4", "VBRK_NE2A2" ], [ "CLK_PMV_NE2A3_4", "VBRK_NE2A3" ], [ "CLK_PMV_NE4BEG0_4", "VBRK_NE4BEG0" ], [ "CLK_PMV_NE4BEG1_4", "VBRK_NE4BEG1" ], [ "CLK_PMV_NE4BEG2_4", "VBRK_NE4BEG2" ], [ "CLK_PMV_NE4BEG3_4", "VBRK_NE4BEG3" ], [ "CLK_PMV_NE4C0_4", "VBRK_NE4C0" ], [ "CLK_PMV_NE4C1_4", "VBRK_NE4C1" ], [ "CLK_PMV_NE4C2_4", "VBRK_NE4C2" ], [ "CLK_PMV_NE4C3_4", "VBRK_NE4C3" ], [ "CLK_PMV_NW2A0_4", "VBRK_NW2A0" ], [ "CLK_PMV_NW2A1_4", "VBRK_NW2A1" ], [ "CLK_PMV_NW2A2_4", "VBRK_NW2A2" ], [ "CLK_PMV_NW2A3_4", "VBRK_NW2A3" ], [ "CLK_PMV_NW4A0_4", "VBRK_NW4A0" ], [ "CLK_PMV_NW4A1_4", "VBRK_NW4A1" ], [ "CLK_PMV_NW4A2_4", "VBRK_NW4A2" ], [ "CLK_PMV_NW4A3_4", "VBRK_NW4A3" ], [ "CLK_PMV_NW4END0_4", "VBRK_NW4END0" ], [ "CLK_PMV_NW4END1_4", "VBRK_NW4END1" ], [ "CLK_PMV_NW4END2_4", "VBRK_NW4END2" ], [ "CLK_PMV_NW4END3_4", "VBRK_NW4END3" ], [ "CLK_PMV_SE2A0_4", "VBRK_SE2A0" ], [ "CLK_PMV_SE2A1_4", "VBRK_SE2A1" ], [ "CLK_PMV_SE2A2_4", "VBRK_SE2A2" ], [ "CLK_PMV_SE2A3_4", "VBRK_SE2A3" ], [ "CLK_PMV_SE4BEG0_4", "VBRK_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_4", "VBRK_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_4", "VBRK_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_4", "VBRK_SE4BEG3" ], [ "CLK_PMV_SE4C0_4", "VBRK_SE4C0" ], [ "CLK_PMV_SE4C1_4", "VBRK_SE4C1" ], [ "CLK_PMV_SE4C2_4", "VBRK_SE4C2" ], [ "CLK_PMV_SE4C3_4", "VBRK_SE4C3" ], [ "CLK_PMV_SW2A0_4", "VBRK_SW2A0" ], [ "CLK_PMV_SW2A1_4", "VBRK_SW2A1" ], [ "CLK_PMV_SW2A2_4", "VBRK_SW2A2" ], [ "CLK_PMV_SW2A3_4", "VBRK_SW2A3" ], [ "CLK_PMV_SW4A0_4", "VBRK_SW4A0" ], [ "CLK_PMV_SW4A1_4", "VBRK_SW4A1" ], [ "CLK_PMV_SW4A2_4", "VBRK_SW4A2" ], [ "CLK_PMV_SW4A3_4", "VBRK_SW4A3" ], [ "CLK_PMV_SW4END0_4", "VBRK_SW4END0" ], [ "CLK_PMV_SW4END1_4", "VBRK_SW4END1" ], [ "CLK_PMV_SW4END2_4", "VBRK_SW4END2" ], [ "CLK_PMV_SW4END3_4", "VBRK_SW4END3" ], [ "CLK_PMV_WL1END0_4", "VBRK_WL1END0" ], [ "CLK_PMV_WL1END1_4", "VBRK_WL1END1" ], [ "CLK_PMV_WL1END2_4", "VBRK_WL1END2" ], [ "CLK_PMV_WL1END3_4", "VBRK_WL1END3" ], [ "CLK_PMV_WR1END0_4", "VBRK_WR1END0" ], [ "CLK_PMV_WR1END1_4", "VBRK_WR1END1" ], [ "CLK_PMV_WR1END2_4", "VBRK_WR1END2" ], [ "CLK_PMV_WR1END3_4", "VBRK_WR1END3" ], [ "CLK_PMV_WW2A0_4", "VBRK_WW2A0" ], [ "CLK_PMV_WW2A1_4", "VBRK_WW2A1" ], [ "CLK_PMV_WW2A2_4", "VBRK_WW2A2" ], [ "CLK_PMV_WW2A3_4", "VBRK_WW2A3" ], [ "CLK_PMV_WW2END0_4", "VBRK_WW2END0" ], [ "CLK_PMV_WW2END1_4", "VBRK_WW2END1" ], [ "CLK_PMV_WW2END2_4", "VBRK_WW2END2" ], [ "CLK_PMV_WW2END3_4", "VBRK_WW2END3" ], [ "CLK_PMV_WW4A0_4", "VBRK_WW4A0" ], [ "CLK_PMV_WW4A1_4", "VBRK_WW4A1" ], [ "CLK_PMV_WW4A2_4", "VBRK_WW4A2" ], [ "CLK_PMV_WW4A3_4", "VBRK_WW4A3" ], [ "CLK_PMV_WW4B0_4", "VBRK_WW4B0" ], [ "CLK_PMV_WW4B1_4", "VBRK_WW4B1" ], [ "CLK_PMV_WW4B2_4", "VBRK_WW4B2" ], [ "CLK_PMV_WW4B3_4", "VBRK_WW4B3" ], [ "CLK_PMV_WW4C0_4", "VBRK_WW4C0" ], [ "CLK_PMV_WW4C1_4", "VBRK_WW4C1" ], [ "CLK_PMV_WW4C2_4", "VBRK_WW4C2" ], [ "CLK_PMV_WW4C3_4", "VBRK_WW4C3" ], [ "CLK_PMV_WW4END0_4", "VBRK_WW4END0" ], [ "CLK_PMV_WW4END1_4", "VBRK_WW4END1" ], [ "CLK_PMV_WW4END2_4", "VBRK_WW4END2" ], [ "CLK_PMV_WW4END3_4", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -3 ], "tile_types": [ "CLK_PMV", "VBRK" ], "wire_pairs": [ [ "CLK_PMV_EE2A0_3", "VBRK_EE2A0" ], [ "CLK_PMV_EE2A1_3", "VBRK_EE2A1" ], [ "CLK_PMV_EE2A2_3", "VBRK_EE2A2" ], [ "CLK_PMV_EE2A3_3", "VBRK_EE2A3" ], [ "CLK_PMV_EE2BEG0_3", "VBRK_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_3", "VBRK_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_3", "VBRK_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_3", "VBRK_EE2BEG3" ], [ "CLK_PMV_EE4A0_3", "VBRK_EE4A0" ], [ "CLK_PMV_EE4A1_3", "VBRK_EE4A1" ], [ "CLK_PMV_EE4A2_3", "VBRK_EE4A2" ], [ "CLK_PMV_EE4A3_3", "VBRK_EE4A3" ], [ "CLK_PMV_EE4B0_3", "VBRK_EE4B0" ], [ "CLK_PMV_EE4B1_3", "VBRK_EE4B1" ], [ "CLK_PMV_EE4B2_3", "VBRK_EE4B2" ], [ "CLK_PMV_EE4B3_3", "VBRK_EE4B3" ], [ "CLK_PMV_EE4BEG0_3", "VBRK_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_3", "VBRK_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_3", "VBRK_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_3", "VBRK_EE4BEG3" ], [ "CLK_PMV_EE4C0_3", "VBRK_EE4C0" ], [ "CLK_PMV_EE4C1_3", "VBRK_EE4C1" ], [ "CLK_PMV_EE4C2_3", "VBRK_EE4C2" ], [ "CLK_PMV_EE4C3_3", "VBRK_EE4C3" ], [ "CLK_PMV_EL1BEG0_3", "VBRK_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_3", "VBRK_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_3", "VBRK_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_3", "VBRK_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_3", "VBRK_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_3", "VBRK_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_3", "VBRK_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_3", "VBRK_ER1BEG3" ], [ "CLK_PMV_LH1_3", "VBRK_LH1" ], [ "CLK_PMV_LH2_3", "VBRK_LH2" ], [ "CLK_PMV_LH3_3", "VBRK_LH3" ], [ "CLK_PMV_LH4_3", "VBRK_LH4" ], [ "CLK_PMV_LH5_3", "VBRK_LH5" ], [ "CLK_PMV_LH6_3", "VBRK_LH6" ], [ "CLK_PMV_LH7_3", "VBRK_LH7" ], [ "CLK_PMV_LH8_3", "VBRK_LH8" ], [ "CLK_PMV_LH9_3", "VBRK_LH9" ], [ "CLK_PMV_LH10_3", "VBRK_LH10" ], [ "CLK_PMV_LH11_3", "VBRK_LH11" ], [ "CLK_PMV_LH12_3", "VBRK_LH12" ], [ "CLK_PMV_NE2A0_3", "VBRK_NE2A0" ], [ "CLK_PMV_NE2A1_3", "VBRK_NE2A1" ], [ "CLK_PMV_NE2A2_3", "VBRK_NE2A2" ], [ "CLK_PMV_NE2A3_3", "VBRK_NE2A3" ], [ "CLK_PMV_NE4BEG0_3", "VBRK_NE4BEG0" ], [ "CLK_PMV_NE4BEG1_3", "VBRK_NE4BEG1" ], [ "CLK_PMV_NE4BEG2_3", "VBRK_NE4BEG2" ], [ "CLK_PMV_NE4BEG3_3", "VBRK_NE4BEG3" ], [ "CLK_PMV_NE4C0_3", "VBRK_NE4C0" ], [ "CLK_PMV_NE4C1_3", "VBRK_NE4C1" ], [ "CLK_PMV_NE4C2_3", "VBRK_NE4C2" ], [ "CLK_PMV_NE4C3_3", "VBRK_NE4C3" ], [ "CLK_PMV_NW2A0_3", "VBRK_NW2A0" ], [ "CLK_PMV_NW2A1_3", "VBRK_NW2A1" ], [ "CLK_PMV_NW2A2_3", "VBRK_NW2A2" ], [ "CLK_PMV_NW2A3_3", "VBRK_NW2A3" ], [ "CLK_PMV_NW4A0_3", "VBRK_NW4A0" ], [ "CLK_PMV_NW4A1_3", "VBRK_NW4A1" ], [ "CLK_PMV_NW4A2_3", "VBRK_NW4A2" ], [ "CLK_PMV_NW4A3_3", "VBRK_NW4A3" ], [ "CLK_PMV_NW4END0_3", "VBRK_NW4END0" ], [ "CLK_PMV_NW4END1_3", "VBRK_NW4END1" ], [ "CLK_PMV_NW4END2_3", "VBRK_NW4END2" ], [ "CLK_PMV_NW4END3_3", "VBRK_NW4END3" ], [ "CLK_PMV_SE2A0_3", "VBRK_SE2A0" ], [ "CLK_PMV_SE2A1_3", "VBRK_SE2A1" ], [ "CLK_PMV_SE2A2_3", "VBRK_SE2A2" ], [ "CLK_PMV_SE2A3_3", "VBRK_SE2A3" ], [ "CLK_PMV_SE4BEG0_3", "VBRK_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_3", "VBRK_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_3", "VBRK_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_3", "VBRK_SE4BEG3" ], [ "CLK_PMV_SE4C0_3", "VBRK_SE4C0" ], [ "CLK_PMV_SE4C1_3", "VBRK_SE4C1" ], [ "CLK_PMV_SE4C2_3", "VBRK_SE4C2" ], [ "CLK_PMV_SE4C3_3", "VBRK_SE4C3" ], [ "CLK_PMV_SW2A0_3", "VBRK_SW2A0" ], [ "CLK_PMV_SW2A1_3", "VBRK_SW2A1" ], [ "CLK_PMV_SW2A2_3", "VBRK_SW2A2" ], [ "CLK_PMV_SW2A3_3", "VBRK_SW2A3" ], [ "CLK_PMV_SW4A0_3", "VBRK_SW4A0" ], [ "CLK_PMV_SW4A1_3", "VBRK_SW4A1" ], [ "CLK_PMV_SW4A2_3", "VBRK_SW4A2" ], [ "CLK_PMV_SW4A3_3", "VBRK_SW4A3" ], [ "CLK_PMV_SW4END0_3", "VBRK_SW4END0" ], [ "CLK_PMV_SW4END1_3", "VBRK_SW4END1" ], [ "CLK_PMV_SW4END2_3", "VBRK_SW4END2" ], [ "CLK_PMV_SW4END3_3", "VBRK_SW4END3" ], [ "CLK_PMV_WL1END0_3", "VBRK_WL1END0" ], [ "CLK_PMV_WL1END1_3", "VBRK_WL1END1" ], [ "CLK_PMV_WL1END2_3", "VBRK_WL1END2" ], [ "CLK_PMV_WL1END3_3", "VBRK_WL1END3" ], [ "CLK_PMV_WR1END0_3", "VBRK_WR1END0" ], [ "CLK_PMV_WR1END1_3", "VBRK_WR1END1" ], [ "CLK_PMV_WR1END2_3", "VBRK_WR1END2" ], [ "CLK_PMV_WR1END3_3", "VBRK_WR1END3" ], [ "CLK_PMV_WW2A0_3", "VBRK_WW2A0" ], [ "CLK_PMV_WW2A1_3", "VBRK_WW2A1" ], [ "CLK_PMV_WW2A2_3", "VBRK_WW2A2" ], [ "CLK_PMV_WW2A3_3", "VBRK_WW2A3" ], [ "CLK_PMV_WW2END0_3", "VBRK_WW2END0" ], [ "CLK_PMV_WW2END1_3", "VBRK_WW2END1" ], [ "CLK_PMV_WW2END2_3", "VBRK_WW2END2" ], [ "CLK_PMV_WW2END3_3", "VBRK_WW2END3" ], [ "CLK_PMV_WW4A0_3", "VBRK_WW4A0" ], [ "CLK_PMV_WW4A1_3", "VBRK_WW4A1" ], [ "CLK_PMV_WW4A2_3", "VBRK_WW4A2" ], [ "CLK_PMV_WW4A3_3", "VBRK_WW4A3" ], [ "CLK_PMV_WW4B0_3", "VBRK_WW4B0" ], [ "CLK_PMV_WW4B1_3", "VBRK_WW4B1" ], [ "CLK_PMV_WW4B2_3", "VBRK_WW4B2" ], [ "CLK_PMV_WW4B3_3", "VBRK_WW4B3" ], [ "CLK_PMV_WW4C0_3", "VBRK_WW4C0" ], [ "CLK_PMV_WW4C1_3", "VBRK_WW4C1" ], [ "CLK_PMV_WW4C2_3", "VBRK_WW4C2" ], [ "CLK_PMV_WW4C3_3", "VBRK_WW4C3" ], [ "CLK_PMV_WW4END0_3", "VBRK_WW4END0" ], [ "CLK_PMV_WW4END1_3", "VBRK_WW4END1" ], [ "CLK_PMV_WW4END2_3", "VBRK_WW4END2" ], [ "CLK_PMV_WW4END3_3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -2 ], "tile_types": [ "CLK_PMV", "VBRK" ], "wire_pairs": [ [ "CLK_PMV_EE2A0_2", "VBRK_EE2A0" ], [ "CLK_PMV_EE2A1_2", "VBRK_EE2A1" ], [ "CLK_PMV_EE2A2_2", "VBRK_EE2A2" ], [ "CLK_PMV_EE2A3_2", "VBRK_EE2A3" ], [ "CLK_PMV_EE2BEG0_2", "VBRK_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_2", "VBRK_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_2", "VBRK_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_2", "VBRK_EE2BEG3" ], [ "CLK_PMV_EE4A0_2", "VBRK_EE4A0" ], [ "CLK_PMV_EE4A1_2", "VBRK_EE4A1" ], [ "CLK_PMV_EE4A2_2", "VBRK_EE4A2" ], [ "CLK_PMV_EE4A3_2", "VBRK_EE4A3" ], [ "CLK_PMV_EE4B0_2", "VBRK_EE4B0" ], [ "CLK_PMV_EE4B1_2", "VBRK_EE4B1" ], [ "CLK_PMV_EE4B2_2", "VBRK_EE4B2" ], [ "CLK_PMV_EE4B3_2", "VBRK_EE4B3" ], [ "CLK_PMV_EE4BEG0_2", "VBRK_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_2", "VBRK_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_2", "VBRK_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_2", "VBRK_EE4BEG3" ], [ "CLK_PMV_EE4C0_2", "VBRK_EE4C0" ], [ "CLK_PMV_EE4C1_2", "VBRK_EE4C1" ], [ "CLK_PMV_EE4C2_2", "VBRK_EE4C2" ], [ "CLK_PMV_EE4C3_2", "VBRK_EE4C3" ], [ "CLK_PMV_EL1BEG0_2", "VBRK_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_2", "VBRK_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_2", "VBRK_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_2", "VBRK_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_2", "VBRK_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_2", "VBRK_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_2", "VBRK_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_2", "VBRK_ER1BEG3" ], [ "CLK_PMV_LH1_2", "VBRK_LH1" ], [ "CLK_PMV_LH2_2", "VBRK_LH2" ], [ "CLK_PMV_LH3_2", "VBRK_LH3" ], [ "CLK_PMV_LH4_2", "VBRK_LH4" ], [ "CLK_PMV_LH5_2", "VBRK_LH5" ], [ "CLK_PMV_LH6_2", "VBRK_LH6" ], [ "CLK_PMV_LH7_2", "VBRK_LH7" ], [ "CLK_PMV_LH8_2", "VBRK_LH8" ], [ "CLK_PMV_LH9_2", "VBRK_LH9" ], [ "CLK_PMV_LH10_2", "VBRK_LH10" ], [ "CLK_PMV_LH11_2", "VBRK_LH11" ], [ "CLK_PMV_LH12_2", "VBRK_LH12" ], [ "CLK_PMV_MONITOR_N_2", "VBRK_MONITOR_N" ], [ "CLK_PMV_MONITOR_P_2", "VBRK_MONITOR_P" ], [ "CLK_PMV_NE2A0_2", "VBRK_NE2A0" ], [ "CLK_PMV_NE2A1_2", "VBRK_NE2A1" ], [ "CLK_PMV_NE2A2_2", "VBRK_NE2A2" ], [ "CLK_PMV_NE2A3_2", "VBRK_NE2A3" ], [ "CLK_PMV_NE4BEG0_2", "VBRK_NE4BEG0" ], [ "CLK_PMV_NE4BEG1_2", "VBRK_NE4BEG1" ], [ "CLK_PMV_NE4BEG2_2", "VBRK_NE4BEG2" ], [ "CLK_PMV_NE4BEG3_2", "VBRK_NE4BEG3" ], [ "CLK_PMV_NE4C0_2", "VBRK_NE4C0" ], [ "CLK_PMV_NE4C1_2", "VBRK_NE4C1" ], [ "CLK_PMV_NE4C2_2", "VBRK_NE4C2" ], [ "CLK_PMV_NE4C3_2", "VBRK_NE4C3" ], [ "CLK_PMV_NW2A0_2", "VBRK_NW2A0" ], [ "CLK_PMV_NW2A1_2", "VBRK_NW2A1" ], [ "CLK_PMV_NW2A2_2", "VBRK_NW2A2" ], [ "CLK_PMV_NW2A3_2", "VBRK_NW2A3" ], [ "CLK_PMV_NW4A0_2", "VBRK_NW4A0" ], [ "CLK_PMV_NW4A1_2", "VBRK_NW4A1" ], [ "CLK_PMV_NW4A2_2", "VBRK_NW4A2" ], [ "CLK_PMV_NW4A3_2", "VBRK_NW4A3" ], [ "CLK_PMV_NW4END0_2", "VBRK_NW4END0" ], [ "CLK_PMV_NW4END1_2", "VBRK_NW4END1" ], [ "CLK_PMV_NW4END2_2", "VBRK_NW4END2" ], [ "CLK_PMV_NW4END3_2", "VBRK_NW4END3" ], [ "CLK_PMV_SE2A0_2", "VBRK_SE2A0" ], [ "CLK_PMV_SE2A1_2", "VBRK_SE2A1" ], [ "CLK_PMV_SE2A2_2", "VBRK_SE2A2" ], [ "CLK_PMV_SE2A3_2", "VBRK_SE2A3" ], [ "CLK_PMV_SE4BEG0_2", "VBRK_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_2", "VBRK_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_2", "VBRK_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_2", "VBRK_SE4BEG3" ], [ "CLK_PMV_SE4C0_2", "VBRK_SE4C0" ], [ "CLK_PMV_SE4C1_2", "VBRK_SE4C1" ], [ "CLK_PMV_SE4C2_2", "VBRK_SE4C2" ], [ "CLK_PMV_SE4C3_2", "VBRK_SE4C3" ], [ "CLK_PMV_SW2A0_2", "VBRK_SW2A0" ], [ "CLK_PMV_SW2A1_2", "VBRK_SW2A1" ], [ "CLK_PMV_SW2A2_2", "VBRK_SW2A2" ], [ "CLK_PMV_SW2A3_2", "VBRK_SW2A3" ], [ "CLK_PMV_SW4A0_2", "VBRK_SW4A0" ], [ "CLK_PMV_SW4A1_2", "VBRK_SW4A1" ], [ "CLK_PMV_SW4A2_2", "VBRK_SW4A2" ], [ "CLK_PMV_SW4A3_2", "VBRK_SW4A3" ], [ "CLK_PMV_SW4END0_2", "VBRK_SW4END0" ], [ "CLK_PMV_SW4END1_2", "VBRK_SW4END1" ], [ "CLK_PMV_SW4END2_2", "VBRK_SW4END2" ], [ "CLK_PMV_SW4END3_2", "VBRK_SW4END3" ], [ "CLK_PMV_WL1END0_2", "VBRK_WL1END0" ], [ "CLK_PMV_WL1END1_2", "VBRK_WL1END1" ], [ "CLK_PMV_WL1END2_2", "VBRK_WL1END2" ], [ "CLK_PMV_WL1END3_2", "VBRK_WL1END3" ], [ "CLK_PMV_WR1END0_2", "VBRK_WR1END0" ], [ "CLK_PMV_WR1END1_2", "VBRK_WR1END1" ], [ "CLK_PMV_WR1END2_2", "VBRK_WR1END2" ], [ "CLK_PMV_WR1END3_2", "VBRK_WR1END3" ], [ "CLK_PMV_WW2A0_2", "VBRK_WW2A0" ], [ "CLK_PMV_WW2A1_2", "VBRK_WW2A1" ], [ "CLK_PMV_WW2A2_2", "VBRK_WW2A2" ], [ "CLK_PMV_WW2A3_2", "VBRK_WW2A3" ], [ "CLK_PMV_WW2END0_2", "VBRK_WW2END0" ], [ "CLK_PMV_WW2END1_2", "VBRK_WW2END1" ], [ "CLK_PMV_WW2END2_2", "VBRK_WW2END2" ], [ "CLK_PMV_WW2END3_2", "VBRK_WW2END3" ], [ "CLK_PMV_WW4A0_2", "VBRK_WW4A0" ], [ "CLK_PMV_WW4A1_2", "VBRK_WW4A1" ], [ "CLK_PMV_WW4A2_2", "VBRK_WW4A2" ], [ "CLK_PMV_WW4A3_2", "VBRK_WW4A3" ], [ "CLK_PMV_WW4B0_2", "VBRK_WW4B0" ], [ "CLK_PMV_WW4B1_2", "VBRK_WW4B1" ], [ "CLK_PMV_WW4B2_2", "VBRK_WW4B2" ], [ "CLK_PMV_WW4B3_2", "VBRK_WW4B3" ], [ "CLK_PMV_WW4C0_2", "VBRK_WW4C0" ], [ "CLK_PMV_WW4C1_2", "VBRK_WW4C1" ], [ "CLK_PMV_WW4C2_2", "VBRK_WW4C2" ], [ "CLK_PMV_WW4C3_2", "VBRK_WW4C3" ], [ "CLK_PMV_WW4END0_2", "VBRK_WW4END0" ], [ "CLK_PMV_WW4END1_2", "VBRK_WW4END1" ], [ "CLK_PMV_WW4END2_2", "VBRK_WW4END2" ], [ "CLK_PMV_WW4END3_2", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, -1 ], "tile_types": [ "CLK_PMV", "VBRK" ], "wire_pairs": [ [ "CLK_PMV_EE2A0_1", "VBRK_EE2A0" ], [ "CLK_PMV_EE2A1_1", "VBRK_EE2A1" ], [ "CLK_PMV_EE2A2_1", "VBRK_EE2A2" ], [ "CLK_PMV_EE2A3_1", "VBRK_EE2A3" ], [ "CLK_PMV_EE2BEG0_1", "VBRK_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_1", "VBRK_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_1", "VBRK_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_1", "VBRK_EE2BEG3" ], [ "CLK_PMV_EE4A0_1", "VBRK_EE4A0" ], [ "CLK_PMV_EE4A1_1", "VBRK_EE4A1" ], [ "CLK_PMV_EE4A2_1", "VBRK_EE4A2" ], [ "CLK_PMV_EE4A3_1", "VBRK_EE4A3" ], [ "CLK_PMV_EE4B0_1", "VBRK_EE4B0" ], [ "CLK_PMV_EE4B1_1", "VBRK_EE4B1" ], [ "CLK_PMV_EE4B2_1", "VBRK_EE4B2" ], [ "CLK_PMV_EE4B3_1", "VBRK_EE4B3" ], [ "CLK_PMV_EE4BEG0_1", "VBRK_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_1", "VBRK_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_1", "VBRK_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_1", "VBRK_EE4BEG3" ], [ "CLK_PMV_EE4C0_1", "VBRK_EE4C0" ], [ "CLK_PMV_EE4C1_1", "VBRK_EE4C1" ], [ "CLK_PMV_EE4C2_1", "VBRK_EE4C2" ], [ "CLK_PMV_EE4C3_1", "VBRK_EE4C3" ], [ "CLK_PMV_EL1BEG0_1", "VBRK_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_1", "VBRK_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_1", "VBRK_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_1", "VBRK_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_1", "VBRK_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_1", "VBRK_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_1", "VBRK_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_1", "VBRK_ER1BEG3" ], [ "CLK_PMV_LH1_1", "VBRK_LH1" ], [ "CLK_PMV_LH2_1", "VBRK_LH2" ], [ "CLK_PMV_LH3_1", "VBRK_LH3" ], [ "CLK_PMV_LH4_1", "VBRK_LH4" ], [ "CLK_PMV_LH5_1", "VBRK_LH5" ], [ "CLK_PMV_LH6_1", "VBRK_LH6" ], [ "CLK_PMV_LH7_1", "VBRK_LH7" ], [ "CLK_PMV_LH8_1", "VBRK_LH8" ], [ "CLK_PMV_LH9_1", "VBRK_LH9" ], [ "CLK_PMV_LH10_1", "VBRK_LH10" ], [ "CLK_PMV_LH11_1", "VBRK_LH11" ], [ "CLK_PMV_LH12_1", "VBRK_LH12" ], [ "CLK_PMV_NE2A0_1", "VBRK_NE2A0" ], [ "CLK_PMV_NE2A1_1", "VBRK_NE2A1" ], [ "CLK_PMV_NE2A2_1", "VBRK_NE2A2" ], [ "CLK_PMV_NE2A3_1", "VBRK_NE2A3" ], [ "CLK_PMV_NE4BEG0_1", "VBRK_NE4BEG0" ], [ "CLK_PMV_NE4BEG1_1", "VBRK_NE4BEG1" ], [ "CLK_PMV_NE4BEG2_1", "VBRK_NE4BEG2" ], [ "CLK_PMV_NE4BEG3_1", "VBRK_NE4BEG3" ], [ "CLK_PMV_NE4C0_1", "VBRK_NE4C0" ], [ "CLK_PMV_NE4C1_1", "VBRK_NE4C1" ], [ "CLK_PMV_NE4C2_1", "VBRK_NE4C2" ], [ "CLK_PMV_NE4C3_1", "VBRK_NE4C3" ], [ "CLK_PMV_NW2A0_1", "VBRK_NW2A0" ], [ "CLK_PMV_NW2A1_1", "VBRK_NW2A1" ], [ "CLK_PMV_NW2A2_1", "VBRK_NW2A2" ], [ "CLK_PMV_NW2A3_1", "VBRK_NW2A3" ], [ "CLK_PMV_NW4A0_1", "VBRK_NW4A0" ], [ "CLK_PMV_NW4A1_1", "VBRK_NW4A1" ], [ "CLK_PMV_NW4A2_1", "VBRK_NW4A2" ], [ "CLK_PMV_NW4A3_1", "VBRK_NW4A3" ], [ "CLK_PMV_NW4END0_1", "VBRK_NW4END0" ], [ "CLK_PMV_NW4END1_1", "VBRK_NW4END1" ], [ "CLK_PMV_NW4END2_1", "VBRK_NW4END2" ], [ "CLK_PMV_NW4END3_1", "VBRK_NW4END3" ], [ "CLK_PMV_SE2A0_1", "VBRK_SE2A0" ], [ "CLK_PMV_SE2A1_1", "VBRK_SE2A1" ], [ "CLK_PMV_SE2A2_1", "VBRK_SE2A2" ], [ "CLK_PMV_SE2A3_1", "VBRK_SE2A3" ], [ "CLK_PMV_SE4BEG0_1", "VBRK_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_1", "VBRK_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_1", "VBRK_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_1", "VBRK_SE4BEG3" ], [ "CLK_PMV_SE4C0_1", "VBRK_SE4C0" ], [ "CLK_PMV_SE4C1_1", "VBRK_SE4C1" ], [ "CLK_PMV_SE4C2_1", "VBRK_SE4C2" ], [ "CLK_PMV_SE4C3_1", "VBRK_SE4C3" ], [ "CLK_PMV_SW2A0_1", "VBRK_SW2A0" ], [ "CLK_PMV_SW2A1_1", "VBRK_SW2A1" ], [ "CLK_PMV_SW2A2_1", "VBRK_SW2A2" ], [ "CLK_PMV_SW2A3_1", "VBRK_SW2A3" ], [ "CLK_PMV_SW4A0_1", "VBRK_SW4A0" ], [ "CLK_PMV_SW4A1_1", "VBRK_SW4A1" ], [ "CLK_PMV_SW4A2_1", "VBRK_SW4A2" ], [ "CLK_PMV_SW4A3_1", "VBRK_SW4A3" ], [ "CLK_PMV_SW4END0_1", "VBRK_SW4END0" ], [ "CLK_PMV_SW4END1_1", "VBRK_SW4END1" ], [ "CLK_PMV_SW4END2_1", "VBRK_SW4END2" ], [ "CLK_PMV_SW4END3_1", "VBRK_SW4END3" ], [ "CLK_PMV_WL1END0_1", "VBRK_WL1END0" ], [ "CLK_PMV_WL1END1_1", "VBRK_WL1END1" ], [ "CLK_PMV_WL1END2_1", "VBRK_WL1END2" ], [ "CLK_PMV_WL1END3_1", "VBRK_WL1END3" ], [ "CLK_PMV_WR1END0_1", "VBRK_WR1END0" ], [ "CLK_PMV_WR1END1_1", "VBRK_WR1END1" ], [ "CLK_PMV_WR1END2_1", "VBRK_WR1END2" ], [ "CLK_PMV_WR1END3_1", "VBRK_WR1END3" ], [ "CLK_PMV_WW2A0_1", "VBRK_WW2A0" ], [ "CLK_PMV_WW2A1_1", "VBRK_WW2A1" ], [ "CLK_PMV_WW2A2_1", "VBRK_WW2A2" ], [ "CLK_PMV_WW2A3_1", "VBRK_WW2A3" ], [ "CLK_PMV_WW2END0_1", "VBRK_WW2END0" ], [ "CLK_PMV_WW2END1_1", "VBRK_WW2END1" ], [ "CLK_PMV_WW2END2_1", "VBRK_WW2END2" ], [ "CLK_PMV_WW2END3_1", "VBRK_WW2END3" ], [ "CLK_PMV_WW4A0_1", "VBRK_WW4A0" ], [ "CLK_PMV_WW4A1_1", "VBRK_WW4A1" ], [ "CLK_PMV_WW4A2_1", "VBRK_WW4A2" ], [ "CLK_PMV_WW4A3_1", "VBRK_WW4A3" ], [ "CLK_PMV_WW4B0_1", "VBRK_WW4B0" ], [ "CLK_PMV_WW4B1_1", "VBRK_WW4B1" ], [ "CLK_PMV_WW4B2_1", "VBRK_WW4B2" ], [ "CLK_PMV_WW4B3_1", "VBRK_WW4B3" ], [ "CLK_PMV_WW4C0_1", "VBRK_WW4C0" ], [ "CLK_PMV_WW4C1_1", "VBRK_WW4C1" ], [ "CLK_PMV_WW4C2_1", "VBRK_WW4C2" ], [ "CLK_PMV_WW4C3_1", "VBRK_WW4C3" ], [ "CLK_PMV_WW4END0_1", "VBRK_WW4END0" ], [ "CLK_PMV_WW4END1_1", "VBRK_WW4END1" ], [ "CLK_PMV_WW4END2_1", "VBRK_WW4END2" ], [ "CLK_PMV_WW4END3_1", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLK_PMV", "VBRK" ], "wire_pairs": [ [ "CLK_PMV_EE2A0_0", "VBRK_EE2A0" ], [ "CLK_PMV_EE2A1_0", "VBRK_EE2A1" ], [ "CLK_PMV_EE2A2_0", "VBRK_EE2A2" ], [ "CLK_PMV_EE2A3_0", "VBRK_EE2A3" ], [ "CLK_PMV_EE2BEG0_0", "VBRK_EE2BEG0" ], [ "CLK_PMV_EE2BEG1_0", "VBRK_EE2BEG1" ], [ "CLK_PMV_EE2BEG2_0", "VBRK_EE2BEG2" ], [ "CLK_PMV_EE2BEG3_0", "VBRK_EE2BEG3" ], [ "CLK_PMV_EE4A0_0", "VBRK_EE4A0" ], [ "CLK_PMV_EE4A1_0", "VBRK_EE4A1" ], [ "CLK_PMV_EE4A2_0", "VBRK_EE4A2" ], [ "CLK_PMV_EE4A3_0", "VBRK_EE4A3" ], [ "CLK_PMV_EE4B0_0", "VBRK_EE4B0" ], [ "CLK_PMV_EE4B1_0", "VBRK_EE4B1" ], [ "CLK_PMV_EE4B2_0", "VBRK_EE4B2" ], [ "CLK_PMV_EE4B3_0", "VBRK_EE4B3" ], [ "CLK_PMV_EE4BEG0_0", "VBRK_EE4BEG0" ], [ "CLK_PMV_EE4BEG1_0", "VBRK_EE4BEG1" ], [ "CLK_PMV_EE4BEG2_0", "VBRK_EE4BEG2" ], [ "CLK_PMV_EE4BEG3_0", "VBRK_EE4BEG3" ], [ "CLK_PMV_EE4C0_0", "VBRK_EE4C0" ], [ "CLK_PMV_EE4C1_0", "VBRK_EE4C1" ], [ "CLK_PMV_EE4C2_0", "VBRK_EE4C2" ], [ "CLK_PMV_EE4C3_0", "VBRK_EE4C3" ], [ "CLK_PMV_EL1BEG0_0", "VBRK_EL1BEG0" ], [ "CLK_PMV_EL1BEG1_0", "VBRK_EL1BEG1" ], [ "CLK_PMV_EL1BEG2_0", "VBRK_EL1BEG2" ], [ "CLK_PMV_EL1BEG3_0", "VBRK_EL1BEG3" ], [ "CLK_PMV_ER1BEG0_0", "VBRK_ER1BEG0" ], [ "CLK_PMV_ER1BEG1_0", "VBRK_ER1BEG1" ], [ "CLK_PMV_ER1BEG2_0", "VBRK_ER1BEG2" ], [ "CLK_PMV_ER1BEG3_0", "VBRK_ER1BEG3" ], [ "CLK_PMV_LH1_0", "VBRK_LH1" ], [ "CLK_PMV_LH2_0", "VBRK_LH2" ], [ "CLK_PMV_LH3_0", "VBRK_LH3" ], [ "CLK_PMV_LH4_0", "VBRK_LH4" ], [ "CLK_PMV_LH5_0", "VBRK_LH5" ], [ "CLK_PMV_LH6_0", "VBRK_LH6" ], [ "CLK_PMV_LH7_0", "VBRK_LH7" ], [ "CLK_PMV_LH8_0", "VBRK_LH8" ], [ "CLK_PMV_LH9_0", "VBRK_LH9" ], [ "CLK_PMV_LH10_0", "VBRK_LH10" ], [ "CLK_PMV_LH11_0", "VBRK_LH11" ], [ "CLK_PMV_LH12_0", "VBRK_LH12" ], [ "CLK_PMV_MONITOR_N_0", "VBRK_MONITOR_N" ], [ "CLK_PMV_MONITOR_P_0", "VBRK_MONITOR_P" ], [ "CLK_PMV_NE2A0_0", "VBRK_NE2A0" ], [ "CLK_PMV_NE2A1_0", "VBRK_NE2A1" ], [ "CLK_PMV_NE2A2_0", "VBRK_NE2A2" ], [ "CLK_PMV_NE2A3_0", "VBRK_NE2A3" ], [ "CLK_PMV_NE4BEG0_0", "VBRK_NE4BEG0" ], [ "CLK_PMV_NE4BEG1_0", "VBRK_NE4BEG1" ], [ "CLK_PMV_NE4BEG2_0", "VBRK_NE4BEG2" ], [ "CLK_PMV_NE4BEG3_0", "VBRK_NE4BEG3" ], [ "CLK_PMV_NE4C0_0", "VBRK_NE4C0" ], [ "CLK_PMV_NE4C1_0", "VBRK_NE4C1" ], [ "CLK_PMV_NE4C2_0", "VBRK_NE4C2" ], [ "CLK_PMV_NE4C3_0", "VBRK_NE4C3" ], [ "CLK_PMV_NW2A0_0", "VBRK_NW2A0" ], [ "CLK_PMV_NW2A1_0", "VBRK_NW2A1" ], [ "CLK_PMV_NW2A2_0", "VBRK_NW2A2" ], [ "CLK_PMV_NW2A3_0", "VBRK_NW2A3" ], [ "CLK_PMV_NW4A0_0", "VBRK_NW4A0" ], [ "CLK_PMV_NW4A1_0", "VBRK_NW4A1" ], [ "CLK_PMV_NW4A2_0", "VBRK_NW4A2" ], [ "CLK_PMV_NW4A3_0", "VBRK_NW4A3" ], [ "CLK_PMV_NW4END0_0", "VBRK_NW4END0" ], [ "CLK_PMV_NW4END1_0", "VBRK_NW4END1" ], [ "CLK_PMV_NW4END2_0", "VBRK_NW4END2" ], [ "CLK_PMV_NW4END3_0", "VBRK_NW4END3" ], [ "CLK_PMV_SE2A0_0", "VBRK_SE2A0" ], [ "CLK_PMV_SE2A1_0", "VBRK_SE2A1" ], [ "CLK_PMV_SE2A2_0", "VBRK_SE2A2" ], [ "CLK_PMV_SE2A3_0", "VBRK_SE2A3" ], [ "CLK_PMV_SE4BEG0_0", "VBRK_SE4BEG0" ], [ "CLK_PMV_SE4BEG1_0", "VBRK_SE4BEG1" ], [ "CLK_PMV_SE4BEG2_0", "VBRK_SE4BEG2" ], [ "CLK_PMV_SE4BEG3_0", "VBRK_SE4BEG3" ], [ "CLK_PMV_SE4C0_0", "VBRK_SE4C0" ], [ "CLK_PMV_SE4C1_0", "VBRK_SE4C1" ], [ "CLK_PMV_SE4C2_0", "VBRK_SE4C2" ], [ "CLK_PMV_SE4C3_0", "VBRK_SE4C3" ], [ "CLK_PMV_SW2A0_0", "VBRK_SW2A0" ], [ "CLK_PMV_SW2A1_0", "VBRK_SW2A1" ], [ "CLK_PMV_SW2A2_0", "VBRK_SW2A2" ], [ "CLK_PMV_SW2A3_0", "VBRK_SW2A3" ], [ "CLK_PMV_SW4A0_0", "VBRK_SW4A0" ], [ "CLK_PMV_SW4A1_0", "VBRK_SW4A1" ], [ "CLK_PMV_SW4A2_0", "VBRK_SW4A2" ], [ "CLK_PMV_SW4A3_0", "VBRK_SW4A3" ], [ "CLK_PMV_SW4END0_0", "VBRK_SW4END0" ], [ "CLK_PMV_SW4END1_0", "VBRK_SW4END1" ], [ "CLK_PMV_SW4END2_0", "VBRK_SW4END2" ], [ "CLK_PMV_SW4END3_0", "VBRK_SW4END3" ], [ "CLK_PMV_WL1END0_0", "VBRK_WL1END0" ], [ "CLK_PMV_WL1END1_0", "VBRK_WL1END1" ], [ "CLK_PMV_WL1END2_0", "VBRK_WL1END2" ], [ "CLK_PMV_WL1END3_0", "VBRK_WL1END3" ], [ "CLK_PMV_WR1END0_0", "VBRK_WR1END0" ], [ "CLK_PMV_WR1END1_0", "VBRK_WR1END1" ], [ "CLK_PMV_WR1END2_0", "VBRK_WR1END2" ], [ "CLK_PMV_WR1END3_0", "VBRK_WR1END3" ], [ "CLK_PMV_WW2A0_0", "VBRK_WW2A0" ], [ "CLK_PMV_WW2A1_0", "VBRK_WW2A1" ], [ "CLK_PMV_WW2A2_0", "VBRK_WW2A2" ], [ "CLK_PMV_WW2A3_0", "VBRK_WW2A3" ], [ "CLK_PMV_WW2END0_0", "VBRK_WW2END0" ], [ "CLK_PMV_WW2END1_0", "VBRK_WW2END1" ], [ "CLK_PMV_WW2END2_0", "VBRK_WW2END2" ], [ "CLK_PMV_WW2END3_0", "VBRK_WW2END3" ], [ "CLK_PMV_WW4A0_0", "VBRK_WW4A0" ], [ "CLK_PMV_WW4A1_0", "VBRK_WW4A1" ], [ "CLK_PMV_WW4A2_0", "VBRK_WW4A2" ], [ "CLK_PMV_WW4A3_0", "VBRK_WW4A3" ], [ "CLK_PMV_WW4B0_0", "VBRK_WW4B0" ], [ "CLK_PMV_WW4B1_0", "VBRK_WW4B1" ], [ "CLK_PMV_WW4B2_0", "VBRK_WW4B2" ], [ "CLK_PMV_WW4B3_0", "VBRK_WW4B3" ], [ "CLK_PMV_WW4C0_0", "VBRK_WW4C0" ], [ "CLK_PMV_WW4C1_0", "VBRK_WW4C1" ], [ "CLK_PMV_WW4C2_0", "VBRK_WW4C2" ], [ "CLK_PMV_WW4C3_0", "VBRK_WW4C3" ], [ "CLK_PMV_WW4END0_0", "VBRK_WW4END0" ], [ "CLK_PMV_WW4END1_0", "VBRK_WW4END1" ], [ "CLK_PMV_WW4END2_0", "VBRK_WW4END2" ], [ "CLK_PMV_WW4END3_0", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "CLK_PMV2", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_FEED_EE2A0", "INT_INTERFACE_EE2A0" ], [ "CLK_FEED_EE2A1", "INT_INTERFACE_EE2A1" ], [ "CLK_FEED_EE2A2", "INT_INTERFACE_EE2A2" ], [ "CLK_FEED_EE2A3", "INT_INTERFACE_EE2A3" ], [ "CLK_FEED_EE2BEG0", "INT_INTERFACE_EE2BEG0" ], [ "CLK_FEED_EE2BEG1", "INT_INTERFACE_EE2BEG1" ], [ "CLK_FEED_EE2BEG2", "INT_INTERFACE_EE2BEG2" ], [ "CLK_FEED_EE2BEG3", "INT_INTERFACE_EE2BEG3" ], [ "CLK_FEED_EE4A0", "INT_INTERFACE_EE4A0" ], [ "CLK_FEED_EE4A1", "INT_INTERFACE_EE4A1" ], [ "CLK_FEED_EE4A2", "INT_INTERFACE_EE4A2" ], [ "CLK_FEED_EE4A3", "INT_INTERFACE_EE4A3" ], [ "CLK_FEED_EE4B0", "INT_INTERFACE_EE4B0" ], [ "CLK_FEED_EE4B1", "INT_INTERFACE_EE4B1" ], [ "CLK_FEED_EE4B2", "INT_INTERFACE_EE4B2" ], [ "CLK_FEED_EE4B3", "INT_INTERFACE_EE4B3" ], [ "CLK_FEED_EE4BEG0", "INT_INTERFACE_EE4BEG0" ], [ "CLK_FEED_EE4BEG1", "INT_INTERFACE_EE4BEG1" ], [ "CLK_FEED_EE4BEG2", "INT_INTERFACE_EE4BEG2" ], [ "CLK_FEED_EE4BEG3", "INT_INTERFACE_EE4BEG3" ], [ "CLK_FEED_EE4C0", "INT_INTERFACE_EE4C0" ], [ "CLK_FEED_EE4C1", "INT_INTERFACE_EE4C1" ], [ "CLK_FEED_EE4C2", "INT_INTERFACE_EE4C2" ], [ "CLK_FEED_EE4C3", "INT_INTERFACE_EE4C3" ], [ "CLK_FEED_EL1BEG0", "INT_INTERFACE_EL1BEG0" ], [ "CLK_FEED_EL1BEG1", "INT_INTERFACE_EL1BEG1" ], [ "CLK_FEED_EL1BEG2", "INT_INTERFACE_EL1BEG2" ], [ "CLK_FEED_EL1BEG3", "INT_INTERFACE_EL1BEG3" ], [ "CLK_FEED_ER1BEG0", "INT_INTERFACE_ER1BEG0" ], [ "CLK_FEED_ER1BEG1", "INT_INTERFACE_ER1BEG1" ], [ "CLK_FEED_ER1BEG2", "INT_INTERFACE_ER1BEG2" ], [ "CLK_FEED_ER1BEG3", "INT_INTERFACE_ER1BEG3" ], [ "CLK_FEED_LH1", "INT_INTERFACE_LH1" ], [ "CLK_FEED_LH2", "INT_INTERFACE_LH2" ], [ "CLK_FEED_LH3", "INT_INTERFACE_LH3" ], [ "CLK_FEED_LH4", "INT_INTERFACE_LH4" ], [ "CLK_FEED_LH5", "INT_INTERFACE_LH5" ], [ "CLK_FEED_LH6", "INT_INTERFACE_LH6" ], [ "CLK_FEED_LH7", "INT_INTERFACE_LH7" ], [ "CLK_FEED_LH8", "INT_INTERFACE_LH8" ], [ "CLK_FEED_LH9", "INT_INTERFACE_LH9" ], [ "CLK_FEED_LH10", "INT_INTERFACE_LH10" ], [ "CLK_FEED_LH11", "INT_INTERFACE_LH11" ], [ "CLK_FEED_LH12", "INT_INTERFACE_LH12" ], [ "CLK_FEED_MONITOR_N", "INT_INTERFACE_MONITOR_N" ], [ "CLK_FEED_MONITOR_P", "INT_INTERFACE_MONITOR_P" ], [ "CLK_FEED_NE2A0", "INT_INTERFACE_NE2A0" ], [ "CLK_FEED_NE2A1", "INT_INTERFACE_NE2A1" ], [ "CLK_FEED_NE2A2", "INT_INTERFACE_NE2A2" ], [ "CLK_FEED_NE2A3", "INT_INTERFACE_NE2A3" ], [ "CLK_FEED_NE4BEG0", "INT_INTERFACE_NE4BEG0" ], [ "CLK_FEED_NE4BEG1", "INT_INTERFACE_NE4BEG1" ], [ "CLK_FEED_NE4BEG2", "INT_INTERFACE_NE4BEG2" ], [ "CLK_FEED_NE4BEG3", "INT_INTERFACE_NE4BEG3" ], [ "CLK_FEED_NE4C0", "INT_INTERFACE_NE4C0" ], [ "CLK_FEED_NE4C1", "INT_INTERFACE_NE4C1" ], [ "CLK_FEED_NE4C2", "INT_INTERFACE_NE4C2" ], [ "CLK_FEED_NE4C3", "INT_INTERFACE_NE4C3" ], [ "CLK_FEED_NW2A0", "INT_INTERFACE_NW2A0" ], [ "CLK_FEED_NW2A1", "INT_INTERFACE_NW2A1" ], [ "CLK_FEED_NW2A2", "INT_INTERFACE_NW2A2" ], [ "CLK_FEED_NW2A3", "INT_INTERFACE_NW2A3" ], [ "CLK_FEED_NW4A0", "INT_INTERFACE_NW4A0" ], [ "CLK_FEED_NW4A1", "INT_INTERFACE_NW4A1" ], [ "CLK_FEED_NW4A2", "INT_INTERFACE_NW4A2" ], [ "CLK_FEED_NW4A3", "INT_INTERFACE_NW4A3" ], [ "CLK_FEED_NW4END0", "INT_INTERFACE_NW4END0" ], [ "CLK_FEED_NW4END1", "INT_INTERFACE_NW4END1" ], [ "CLK_FEED_NW4END2", "INT_INTERFACE_NW4END2" ], [ "CLK_FEED_NW4END3", "INT_INTERFACE_NW4END3" ], [ "CLK_FEED_SE2A0", "INT_INTERFACE_SE2A0" ], [ "CLK_FEED_SE2A1", "INT_INTERFACE_SE2A1" ], [ "CLK_FEED_SE2A2", "INT_INTERFACE_SE2A2" ], [ "CLK_FEED_SE2A3", "INT_INTERFACE_SE2A3" ], [ "CLK_FEED_SE4BEG0", "INT_INTERFACE_SE4BEG0" ], [ "CLK_FEED_SE4BEG1", "INT_INTERFACE_SE4BEG1" ], [ "CLK_FEED_SE4BEG2", "INT_INTERFACE_SE4BEG2" ], [ "CLK_FEED_SE4BEG3", "INT_INTERFACE_SE4BEG3" ], [ "CLK_FEED_SE4C0", "INT_INTERFACE_SE4C0" ], [ "CLK_FEED_SE4C1", "INT_INTERFACE_SE4C1" ], [ "CLK_FEED_SE4C2", "INT_INTERFACE_SE4C2" ], [ "CLK_FEED_SE4C3", "INT_INTERFACE_SE4C3" ], [ "CLK_FEED_SW2A0", "INT_INTERFACE_SW2A0" ], [ "CLK_FEED_SW2A1", "INT_INTERFACE_SW2A1" ], [ "CLK_FEED_SW2A2", "INT_INTERFACE_SW2A2" ], [ "CLK_FEED_SW2A3", "INT_INTERFACE_SW2A3" ], [ "CLK_FEED_SW4A0", "INT_INTERFACE_SW4A0" ], [ "CLK_FEED_SW4A1", "INT_INTERFACE_SW4A1" ], [ "CLK_FEED_SW4A2", "INT_INTERFACE_SW4A2" ], [ "CLK_FEED_SW4A3", "INT_INTERFACE_SW4A3" ], [ "CLK_FEED_SW4END0", "INT_INTERFACE_SW4END0" ], [ "CLK_FEED_SW4END1", "INT_INTERFACE_SW4END1" ], [ "CLK_FEED_SW4END2", "INT_INTERFACE_SW4END2" ], [ "CLK_FEED_SW4END3", "INT_INTERFACE_SW4END3" ], [ "CLK_FEED_WL1END0", "INT_INTERFACE_WL1END0" ], [ "CLK_FEED_WL1END1", "INT_INTERFACE_WL1END1" ], [ "CLK_FEED_WL1END2", "INT_INTERFACE_WL1END2" ], [ "CLK_FEED_WL1END3", "INT_INTERFACE_WL1END3" ], [ "CLK_FEED_WR1END0", "INT_INTERFACE_WR1END0" ], [ "CLK_FEED_WR1END1", "INT_INTERFACE_WR1END1" ], [ "CLK_FEED_WR1END2", "INT_INTERFACE_WR1END2" ], [ "CLK_FEED_WR1END3", "INT_INTERFACE_WR1END3" ], [ "CLK_FEED_WW2A0", "INT_INTERFACE_WW2A0" ], [ "CLK_FEED_WW2A1", "INT_INTERFACE_WW2A1" ], [ "CLK_FEED_WW2A2", "INT_INTERFACE_WW2A2" ], [ "CLK_FEED_WW2A3", "INT_INTERFACE_WW2A3" ], [ "CLK_FEED_WW2END0", "INT_INTERFACE_WW2END0" ], [ "CLK_FEED_WW2END1", "INT_INTERFACE_WW2END1" ], [ "CLK_FEED_WW2END2", "INT_INTERFACE_WW2END2" ], [ "CLK_FEED_WW2END3", "INT_INTERFACE_WW2END3" ], [ "CLK_FEED_WW4A0", "INT_INTERFACE_WW4A0" ], [ "CLK_FEED_WW4A1", "INT_INTERFACE_WW4A1" ], [ "CLK_FEED_WW4A2", "INT_INTERFACE_WW4A2" ], [ "CLK_FEED_WW4A3", "INT_INTERFACE_WW4A3" ], [ "CLK_FEED_WW4B0", "INT_INTERFACE_WW4B0" ], [ "CLK_FEED_WW4B1", "INT_INTERFACE_WW4B1" ], [ "CLK_FEED_WW4B2", "INT_INTERFACE_WW4B2" ], [ "CLK_FEED_WW4B3", "INT_INTERFACE_WW4B3" ], [ "CLK_FEED_WW4C0", "INT_INTERFACE_WW4C0" ], [ "CLK_FEED_WW4C1", "INT_INTERFACE_WW4C1" ], [ "CLK_FEED_WW4C2", "INT_INTERFACE_WW4C2" ], [ "CLK_FEED_WW4C3", "INT_INTERFACE_WW4C3" ], [ "CLK_FEED_WW4END0", "INT_INTERFACE_WW4END0" ], [ "CLK_FEED_WW4END1", "INT_INTERFACE_WW4END1" ], [ "CLK_FEED_WW4END2", "INT_INTERFACE_WW4END2" ], [ "CLK_FEED_WW4END3", "INT_INTERFACE_WW4END3" ], [ "CLK_PMV_BYP0_0", "INT_INTERFACE_BYP0" ], [ "CLK_PMV_BYP1_0", "INT_INTERFACE_BYP1" ], [ "CLK_PMV_BYP2_0", "INT_INTERFACE_BYP2" ], [ "CLK_PMV_BYP3_0", "INT_INTERFACE_BYP3" ], [ "CLK_PMV_BYP4_0", "INT_INTERFACE_BYP4" ], [ "CLK_PMV_BYP5_0", "INT_INTERFACE_BYP5" ], [ "CLK_PMV_BYP6_0", "INT_INTERFACE_BYP6" ], [ "CLK_PMV_BYP7_0", "INT_INTERFACE_BYP7" ], [ "CLK_PMV_CLK0_0", "INT_INTERFACE_CLK0" ], [ "CLK_PMV_CLK1_0", "INT_INTERFACE_CLK1" ], [ "CLK_PMV_CTRL0_0", "INT_INTERFACE_CTRL0" ], [ "CLK_PMV_CTRL1_0", "INT_INTERFACE_CTRL1" ], [ "CLK_PMV_FAN0_0", "INT_INTERFACE_FAN0" ], [ "CLK_PMV_FAN1_0", "INT_INTERFACE_FAN1" ], [ "CLK_PMV_FAN2_0", "INT_INTERFACE_FAN2" ], [ "CLK_PMV_FAN3_0", "INT_INTERFACE_FAN3" ], [ "CLK_PMV_FAN4_0", "INT_INTERFACE_FAN4" ], [ "CLK_PMV_FAN5_0", "INT_INTERFACE_FAN5" ], [ "CLK_PMV_FAN6_0", "INT_INTERFACE_FAN6" ], [ "CLK_PMV_FAN7_0", "INT_INTERFACE_FAN7" ], [ "CLK_PMV_IMUX0_0", "INT_INTERFACE_IMUX0" ], [ "CLK_PMV_IMUX1_0", "INT_INTERFACE_IMUX1" ], [ "CLK_PMV_IMUX2_0", "INT_INTERFACE_IMUX2" ], [ "CLK_PMV_IMUX3_0", "INT_INTERFACE_IMUX3" ], [ "CLK_PMV_IMUX4_0", "INT_INTERFACE_IMUX4" ], [ "CLK_PMV_IMUX5_0", "INT_INTERFACE_IMUX5" ], [ "CLK_PMV_IMUX6_0", "INT_INTERFACE_IMUX6" ], [ "CLK_PMV_IMUX7_0", "INT_INTERFACE_IMUX7" ], [ "CLK_PMV_IMUX8_0", "INT_INTERFACE_IMUX8" ], [ "CLK_PMV_IMUX9_0", "INT_INTERFACE_IMUX9" ], [ "CLK_PMV_IMUX10_0", "INT_INTERFACE_IMUX10" ], [ "CLK_PMV_IMUX11_0", "INT_INTERFACE_IMUX11" ], [ "CLK_PMV_IMUX12_0", "INT_INTERFACE_IMUX12" ], [ "CLK_PMV_IMUX13_0", "INT_INTERFACE_IMUX13" ], [ "CLK_PMV_IMUX14_0", "INT_INTERFACE_IMUX14" ], [ "CLK_PMV_IMUX15_0", "INT_INTERFACE_IMUX15" ], [ "CLK_PMV_IMUX16_0", "INT_INTERFACE_IMUX16" ], [ "CLK_PMV_IMUX17_0", "INT_INTERFACE_IMUX17" ], [ "CLK_PMV_IMUX18_0", "INT_INTERFACE_IMUX18" ], [ "CLK_PMV_IMUX19_0", "INT_INTERFACE_IMUX19" ], [ "CLK_PMV_IMUX20_0", "INT_INTERFACE_IMUX20" ], [ "CLK_PMV_IMUX21_0", "INT_INTERFACE_IMUX21" ], [ "CLK_PMV_IMUX22_0", "INT_INTERFACE_IMUX22" ], [ "CLK_PMV_IMUX23_0", "INT_INTERFACE_IMUX23" ], [ "CLK_PMV_IMUX24_0", "INT_INTERFACE_IMUX24" ], [ "CLK_PMV_IMUX25_0", "INT_INTERFACE_IMUX25" ], [ "CLK_PMV_IMUX26_0", "INT_INTERFACE_IMUX26" ], [ "CLK_PMV_IMUX27_0", "INT_INTERFACE_IMUX27" ], [ "CLK_PMV_IMUX28_0", "INT_INTERFACE_IMUX28" ], [ "CLK_PMV_IMUX29_0", "INT_INTERFACE_IMUX29" ], [ "CLK_PMV_IMUX30_0", "INT_INTERFACE_IMUX30" ], [ "CLK_PMV_IMUX31_0", "INT_INTERFACE_IMUX31" ], [ "CLK_PMV_IMUX32_0", "INT_INTERFACE_IMUX32" ], [ "CLK_PMV_IMUX33_0", "INT_INTERFACE_IMUX33" ], [ "CLK_PMV_IMUX34_0", "INT_INTERFACE_IMUX34" ], [ "CLK_PMV_IMUX35_0", "INT_INTERFACE_IMUX35" ], [ "CLK_PMV_IMUX36_0", "INT_INTERFACE_IMUX36" ], [ "CLK_PMV_IMUX37_0", "INT_INTERFACE_IMUX37" ], [ "CLK_PMV_IMUX38_0", "INT_INTERFACE_IMUX38" ], [ "CLK_PMV_IMUX39_0", "INT_INTERFACE_IMUX39" ], [ "CLK_PMV_IMUX40_0", "INT_INTERFACE_IMUX40" ], [ "CLK_PMV_IMUX41_0", "INT_INTERFACE_IMUX41" ], [ "CLK_PMV_IMUX42_0", "INT_INTERFACE_IMUX42" ], [ "CLK_PMV_IMUX43_0", "INT_INTERFACE_IMUX43" ], [ "CLK_PMV_IMUX44_0", "INT_INTERFACE_IMUX44" ], [ "CLK_PMV_IMUX45_0", "INT_INTERFACE_IMUX45" ], [ "CLK_PMV_IMUX46_0", "INT_INTERFACE_IMUX46" ], [ "CLK_PMV_IMUX47_0", "INT_INTERFACE_IMUX47" ], [ "CLK_PMV_LOGIC_OUTS5_0", "INT_INTERFACE_LOGIC_OUTS_B5" ], [ "CLK_PMV_LOGIC_OUTS9_0", "INT_INTERFACE_LOGIC_OUTS_B9" ], [ "CLK_PMV_LOGIC_OUTS19_0", "INT_INTERFACE_LOGIC_OUTS_B19" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLK_PMV2", "VBRK" ], "wire_pairs": [ [ "CLK_FEED_EE2A0", "VBRK_EE2A0" ], [ "CLK_FEED_EE2A1", "VBRK_EE2A1" ], [ "CLK_FEED_EE2A2", "VBRK_EE2A2" ], [ "CLK_FEED_EE2A3", "VBRK_EE2A3" ], [ "CLK_FEED_EE2BEG0", "VBRK_EE2BEG0" ], [ "CLK_FEED_EE2BEG1", "VBRK_EE2BEG1" ], [ "CLK_FEED_EE2BEG2", "VBRK_EE2BEG2" ], [ "CLK_FEED_EE2BEG3", "VBRK_EE2BEG3" ], [ "CLK_FEED_EE4A0", "VBRK_EE4A0" ], [ "CLK_FEED_EE4A1", "VBRK_EE4A1" ], [ "CLK_FEED_EE4A2", "VBRK_EE4A2" ], [ "CLK_FEED_EE4A3", "VBRK_EE4A3" ], [ "CLK_FEED_EE4B0", "VBRK_EE4B0" ], [ "CLK_FEED_EE4B1", "VBRK_EE4B1" ], [ "CLK_FEED_EE4B2", "VBRK_EE4B2" ], [ "CLK_FEED_EE4B3", "VBRK_EE4B3" ], [ "CLK_FEED_EE4BEG0", "VBRK_EE4BEG0" ], [ "CLK_FEED_EE4BEG1", "VBRK_EE4BEG1" ], [ "CLK_FEED_EE4BEG2", "VBRK_EE4BEG2" ], [ "CLK_FEED_EE4BEG3", "VBRK_EE4BEG3" ], [ "CLK_FEED_EE4C0", "VBRK_EE4C0" ], [ "CLK_FEED_EE4C1", "VBRK_EE4C1" ], [ "CLK_FEED_EE4C2", "VBRK_EE4C2" ], [ "CLK_FEED_EE4C3", "VBRK_EE4C3" ], [ "CLK_FEED_EL1BEG0", "VBRK_EL1BEG0" ], [ "CLK_FEED_EL1BEG1", "VBRK_EL1BEG1" ], [ "CLK_FEED_EL1BEG2", "VBRK_EL1BEG2" ], [ "CLK_FEED_EL1BEG3", "VBRK_EL1BEG3" ], [ "CLK_FEED_ER1BEG0", "VBRK_ER1BEG0" ], [ "CLK_FEED_ER1BEG1", "VBRK_ER1BEG1" ], [ "CLK_FEED_ER1BEG2", "VBRK_ER1BEG2" ], [ "CLK_FEED_ER1BEG3", "VBRK_ER1BEG3" ], [ "CLK_FEED_LH1", "VBRK_LH1" ], [ "CLK_FEED_LH2", "VBRK_LH2" ], [ "CLK_FEED_LH3", "VBRK_LH3" ], [ "CLK_FEED_LH4", "VBRK_LH4" ], [ "CLK_FEED_LH5", "VBRK_LH5" ], [ "CLK_FEED_LH6", "VBRK_LH6" ], [ "CLK_FEED_LH7", "VBRK_LH7" ], [ "CLK_FEED_LH8", "VBRK_LH8" ], [ "CLK_FEED_LH9", "VBRK_LH9" ], [ "CLK_FEED_LH10", "VBRK_LH10" ], [ "CLK_FEED_LH11", "VBRK_LH11" ], [ "CLK_FEED_LH12", "VBRK_LH12" ], [ "CLK_FEED_MONITOR_N", "VBRK_MONITOR_N" ], [ "CLK_FEED_MONITOR_P", "VBRK_MONITOR_P" ], [ "CLK_FEED_NE2A0", "VBRK_NE2A0" ], [ "CLK_FEED_NE2A1", "VBRK_NE2A1" ], [ "CLK_FEED_NE2A2", "VBRK_NE2A2" ], [ "CLK_FEED_NE2A3", "VBRK_NE2A3" ], [ "CLK_FEED_NE4BEG0", "VBRK_NE4BEG0" ], [ "CLK_FEED_NE4BEG1", "VBRK_NE4BEG1" ], [ "CLK_FEED_NE4BEG2", "VBRK_NE4BEG2" ], [ "CLK_FEED_NE4BEG3", "VBRK_NE4BEG3" ], [ "CLK_FEED_NE4C0", "VBRK_NE4C0" ], [ "CLK_FEED_NE4C1", "VBRK_NE4C1" ], [ "CLK_FEED_NE4C2", "VBRK_NE4C2" ], [ "CLK_FEED_NE4C3", "VBRK_NE4C3" ], [ "CLK_FEED_NW2A0", "VBRK_NW2A0" ], [ "CLK_FEED_NW2A1", "VBRK_NW2A1" ], [ "CLK_FEED_NW2A2", "VBRK_NW2A2" ], [ "CLK_FEED_NW2A3", "VBRK_NW2A3" ], [ "CLK_FEED_NW4A0", "VBRK_NW4A0" ], [ "CLK_FEED_NW4A1", "VBRK_NW4A1" ], [ "CLK_FEED_NW4A2", "VBRK_NW4A2" ], [ "CLK_FEED_NW4A3", "VBRK_NW4A3" ], [ "CLK_FEED_NW4END0", "VBRK_NW4END0" ], [ "CLK_FEED_NW4END1", "VBRK_NW4END1" ], [ "CLK_FEED_NW4END2", "VBRK_NW4END2" ], [ "CLK_FEED_NW4END3", "VBRK_NW4END3" ], [ "CLK_FEED_SE2A0", "VBRK_SE2A0" ], [ "CLK_FEED_SE2A1", "VBRK_SE2A1" ], [ "CLK_FEED_SE2A2", "VBRK_SE2A2" ], [ "CLK_FEED_SE2A3", "VBRK_SE2A3" ], [ "CLK_FEED_SE4BEG0", "VBRK_SE4BEG0" ], [ "CLK_FEED_SE4BEG1", "VBRK_SE4BEG1" ], [ "CLK_FEED_SE4BEG2", "VBRK_SE4BEG2" ], [ "CLK_FEED_SE4BEG3", "VBRK_SE4BEG3" ], [ "CLK_FEED_SE4C0", "VBRK_SE4C0" ], [ "CLK_FEED_SE4C1", "VBRK_SE4C1" ], [ "CLK_FEED_SE4C2", "VBRK_SE4C2" ], [ "CLK_FEED_SE4C3", "VBRK_SE4C3" ], [ "CLK_FEED_SW2A0", "VBRK_SW2A0" ], [ "CLK_FEED_SW2A1", "VBRK_SW2A1" ], [ "CLK_FEED_SW2A2", "VBRK_SW2A2" ], [ "CLK_FEED_SW2A3", "VBRK_SW2A3" ], [ "CLK_FEED_SW4A0", "VBRK_SW4A0" ], [ "CLK_FEED_SW4A1", "VBRK_SW4A1" ], [ "CLK_FEED_SW4A2", "VBRK_SW4A2" ], [ "CLK_FEED_SW4A3", "VBRK_SW4A3" ], [ "CLK_FEED_SW4END0", "VBRK_SW4END0" ], [ "CLK_FEED_SW4END1", "VBRK_SW4END1" ], [ "CLK_FEED_SW4END2", "VBRK_SW4END2" ], [ "CLK_FEED_SW4END3", "VBRK_SW4END3" ], [ "CLK_FEED_WL1END0", "VBRK_WL1END0" ], [ "CLK_FEED_WL1END1", "VBRK_WL1END1" ], [ "CLK_FEED_WL1END2", "VBRK_WL1END2" ], [ "CLK_FEED_WL1END3", "VBRK_WL1END3" ], [ "CLK_FEED_WR1END0", "VBRK_WR1END0" ], [ "CLK_FEED_WR1END1", "VBRK_WR1END1" ], [ "CLK_FEED_WR1END2", "VBRK_WR1END2" ], [ "CLK_FEED_WR1END3", "VBRK_WR1END3" ], [ "CLK_FEED_WW2A0", "VBRK_WW2A0" ], [ "CLK_FEED_WW2A1", "VBRK_WW2A1" ], [ "CLK_FEED_WW2A2", "VBRK_WW2A2" ], [ "CLK_FEED_WW2A3", "VBRK_WW2A3" ], [ "CLK_FEED_WW2END0", "VBRK_WW2END0" ], [ "CLK_FEED_WW2END1", "VBRK_WW2END1" ], [ "CLK_FEED_WW2END2", "VBRK_WW2END2" ], [ "CLK_FEED_WW2END3", "VBRK_WW2END3" ], [ "CLK_FEED_WW4A0", "VBRK_WW4A0" ], [ "CLK_FEED_WW4A1", "VBRK_WW4A1" ], [ "CLK_FEED_WW4A2", "VBRK_WW4A2" ], [ "CLK_FEED_WW4A3", "VBRK_WW4A3" ], [ "CLK_FEED_WW4B0", "VBRK_WW4B0" ], [ "CLK_FEED_WW4B1", "VBRK_WW4B1" ], [ "CLK_FEED_WW4B2", "VBRK_WW4B2" ], [ "CLK_FEED_WW4B3", "VBRK_WW4B3" ], [ "CLK_FEED_WW4C0", "VBRK_WW4C0" ], [ "CLK_FEED_WW4C1", "VBRK_WW4C1" ], [ "CLK_FEED_WW4C2", "VBRK_WW4C2" ], [ "CLK_FEED_WW4C3", "VBRK_WW4C3" ], [ "CLK_FEED_WW4END0", "VBRK_WW4END0" ], [ "CLK_FEED_WW4END1", "VBRK_WW4END1" ], [ "CLK_FEED_WW4END2", "VBRK_WW4END2" ], [ "CLK_FEED_WW4END3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "CLK_PMV2_SVT", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_FEED_EE2A0", "INT_INTERFACE_EE2A0" ], [ "CLK_FEED_EE2A1", "INT_INTERFACE_EE2A1" ], [ "CLK_FEED_EE2A2", "INT_INTERFACE_EE2A2" ], [ "CLK_FEED_EE2A3", "INT_INTERFACE_EE2A3" ], [ "CLK_FEED_EE2BEG0", "INT_INTERFACE_EE2BEG0" ], [ "CLK_FEED_EE2BEG1", "INT_INTERFACE_EE2BEG1" ], [ "CLK_FEED_EE2BEG2", "INT_INTERFACE_EE2BEG2" ], [ "CLK_FEED_EE2BEG3", "INT_INTERFACE_EE2BEG3" ], [ "CLK_FEED_EE4A0", "INT_INTERFACE_EE4A0" ], [ "CLK_FEED_EE4A1", "INT_INTERFACE_EE4A1" ], [ "CLK_FEED_EE4A2", "INT_INTERFACE_EE4A2" ], [ "CLK_FEED_EE4A3", "INT_INTERFACE_EE4A3" ], [ "CLK_FEED_EE4B0", "INT_INTERFACE_EE4B0" ], [ "CLK_FEED_EE4B1", "INT_INTERFACE_EE4B1" ], [ "CLK_FEED_EE4B2", "INT_INTERFACE_EE4B2" ], [ "CLK_FEED_EE4B3", "INT_INTERFACE_EE4B3" ], [ "CLK_FEED_EE4BEG0", "INT_INTERFACE_EE4BEG0" ], [ "CLK_FEED_EE4BEG1", "INT_INTERFACE_EE4BEG1" ], [ "CLK_FEED_EE4BEG2", "INT_INTERFACE_EE4BEG2" ], [ "CLK_FEED_EE4BEG3", "INT_INTERFACE_EE4BEG3" ], [ "CLK_FEED_EE4C0", "INT_INTERFACE_EE4C0" ], [ "CLK_FEED_EE4C1", "INT_INTERFACE_EE4C1" ], [ "CLK_FEED_EE4C2", "INT_INTERFACE_EE4C2" ], [ "CLK_FEED_EE4C3", "INT_INTERFACE_EE4C3" ], [ "CLK_FEED_EL1BEG0", "INT_INTERFACE_EL1BEG0" ], [ "CLK_FEED_EL1BEG1", "INT_INTERFACE_EL1BEG1" ], [ "CLK_FEED_EL1BEG2", "INT_INTERFACE_EL1BEG2" ], [ "CLK_FEED_EL1BEG3", "INT_INTERFACE_EL1BEG3" ], [ "CLK_FEED_ER1BEG0", "INT_INTERFACE_ER1BEG0" ], [ "CLK_FEED_ER1BEG1", "INT_INTERFACE_ER1BEG1" ], [ "CLK_FEED_ER1BEG2", "INT_INTERFACE_ER1BEG2" ], [ "CLK_FEED_ER1BEG3", "INT_INTERFACE_ER1BEG3" ], [ "CLK_FEED_LH1", "INT_INTERFACE_LH1" ], [ "CLK_FEED_LH2", "INT_INTERFACE_LH2" ], [ "CLK_FEED_LH3", "INT_INTERFACE_LH3" ], [ "CLK_FEED_LH4", "INT_INTERFACE_LH4" ], [ "CLK_FEED_LH5", "INT_INTERFACE_LH5" ], [ "CLK_FEED_LH6", "INT_INTERFACE_LH6" ], [ "CLK_FEED_LH7", "INT_INTERFACE_LH7" ], [ "CLK_FEED_LH8", "INT_INTERFACE_LH8" ], [ "CLK_FEED_LH9", "INT_INTERFACE_LH9" ], [ "CLK_FEED_LH10", "INT_INTERFACE_LH10" ], [ "CLK_FEED_LH11", "INT_INTERFACE_LH11" ], [ "CLK_FEED_LH12", "INT_INTERFACE_LH12" ], [ "CLK_FEED_NE2A0", "INT_INTERFACE_NE2A0" ], [ "CLK_FEED_NE2A1", "INT_INTERFACE_NE2A1" ], [ "CLK_FEED_NE2A2", "INT_INTERFACE_NE2A2" ], [ "CLK_FEED_NE2A3", "INT_INTERFACE_NE2A3" ], [ "CLK_FEED_NE4BEG0", "INT_INTERFACE_NE4BEG0" ], [ "CLK_FEED_NE4BEG1", "INT_INTERFACE_NE4BEG1" ], [ "CLK_FEED_NE4BEG2", "INT_INTERFACE_NE4BEG2" ], [ "CLK_FEED_NE4BEG3", "INT_INTERFACE_NE4BEG3" ], [ "CLK_FEED_NE4C0", "INT_INTERFACE_NE4C0" ], [ "CLK_FEED_NE4C1", "INT_INTERFACE_NE4C1" ], [ "CLK_FEED_NE4C2", "INT_INTERFACE_NE4C2" ], [ "CLK_FEED_NE4C3", "INT_INTERFACE_NE4C3" ], [ "CLK_FEED_NW2A0", "INT_INTERFACE_NW2A0" ], [ "CLK_FEED_NW2A1", "INT_INTERFACE_NW2A1" ], [ "CLK_FEED_NW2A2", "INT_INTERFACE_NW2A2" ], [ "CLK_FEED_NW2A3", "INT_INTERFACE_NW2A3" ], [ "CLK_FEED_NW4A0", "INT_INTERFACE_NW4A0" ], [ "CLK_FEED_NW4A1", "INT_INTERFACE_NW4A1" ], [ "CLK_FEED_NW4A2", "INT_INTERFACE_NW4A2" ], [ "CLK_FEED_NW4A3", "INT_INTERFACE_NW4A3" ], [ "CLK_FEED_NW4END0", "INT_INTERFACE_NW4END0" ], [ "CLK_FEED_NW4END1", "INT_INTERFACE_NW4END1" ], [ "CLK_FEED_NW4END2", "INT_INTERFACE_NW4END2" ], [ "CLK_FEED_NW4END3", "INT_INTERFACE_NW4END3" ], [ "CLK_FEED_SE2A0", "INT_INTERFACE_SE2A0" ], [ "CLK_FEED_SE2A1", "INT_INTERFACE_SE2A1" ], [ "CLK_FEED_SE2A2", "INT_INTERFACE_SE2A2" ], [ "CLK_FEED_SE2A3", "INT_INTERFACE_SE2A3" ], [ "CLK_FEED_SE4BEG0", "INT_INTERFACE_SE4BEG0" ], [ "CLK_FEED_SE4BEG1", "INT_INTERFACE_SE4BEG1" ], [ "CLK_FEED_SE4BEG2", "INT_INTERFACE_SE4BEG2" ], [ "CLK_FEED_SE4BEG3", "INT_INTERFACE_SE4BEG3" ], [ "CLK_FEED_SE4C0", "INT_INTERFACE_SE4C0" ], [ "CLK_FEED_SE4C1", "INT_INTERFACE_SE4C1" ], [ "CLK_FEED_SE4C2", "INT_INTERFACE_SE4C2" ], [ "CLK_FEED_SE4C3", "INT_INTERFACE_SE4C3" ], [ "CLK_FEED_SW2A0", "INT_INTERFACE_SW2A0" ], [ "CLK_FEED_SW2A1", "INT_INTERFACE_SW2A1" ], [ "CLK_FEED_SW2A2", "INT_INTERFACE_SW2A2" ], [ "CLK_FEED_SW2A3", "INT_INTERFACE_SW2A3" ], [ "CLK_FEED_SW4A0", "INT_INTERFACE_SW4A0" ], [ "CLK_FEED_SW4A1", "INT_INTERFACE_SW4A1" ], [ "CLK_FEED_SW4A2", "INT_INTERFACE_SW4A2" ], [ "CLK_FEED_SW4A3", "INT_INTERFACE_SW4A3" ], [ "CLK_FEED_SW4END0", "INT_INTERFACE_SW4END0" ], [ "CLK_FEED_SW4END1", "INT_INTERFACE_SW4END1" ], [ "CLK_FEED_SW4END2", "INT_INTERFACE_SW4END2" ], [ "CLK_FEED_SW4END3", "INT_INTERFACE_SW4END3" ], [ "CLK_FEED_WL1END0", "INT_INTERFACE_WL1END0" ], [ "CLK_FEED_WL1END1", "INT_INTERFACE_WL1END1" ], [ "CLK_FEED_WL1END2", "INT_INTERFACE_WL1END2" ], [ "CLK_FEED_WL1END3", "INT_INTERFACE_WL1END3" ], [ "CLK_FEED_WR1END0", "INT_INTERFACE_WR1END0" ], [ "CLK_FEED_WR1END1", "INT_INTERFACE_WR1END1" ], [ "CLK_FEED_WR1END2", "INT_INTERFACE_WR1END2" ], [ "CLK_FEED_WR1END3", "INT_INTERFACE_WR1END3" ], [ "CLK_FEED_WW2A0", "INT_INTERFACE_WW2A0" ], [ "CLK_FEED_WW2A1", "INT_INTERFACE_WW2A1" ], [ "CLK_FEED_WW2A2", "INT_INTERFACE_WW2A2" ], [ "CLK_FEED_WW2A3", "INT_INTERFACE_WW2A3" ], [ "CLK_FEED_WW2END0", "INT_INTERFACE_WW2END0" ], [ "CLK_FEED_WW2END1", "INT_INTERFACE_WW2END1" ], [ "CLK_FEED_WW2END2", "INT_INTERFACE_WW2END2" ], [ "CLK_FEED_WW2END3", "INT_INTERFACE_WW2END3" ], [ "CLK_FEED_WW4A0", "INT_INTERFACE_WW4A0" ], [ "CLK_FEED_WW4A1", "INT_INTERFACE_WW4A1" ], [ "CLK_FEED_WW4A2", "INT_INTERFACE_WW4A2" ], [ "CLK_FEED_WW4A3", "INT_INTERFACE_WW4A3" ], [ "CLK_FEED_WW4B0", "INT_INTERFACE_WW4B0" ], [ "CLK_FEED_WW4B1", "INT_INTERFACE_WW4B1" ], [ "CLK_FEED_WW4B2", "INT_INTERFACE_WW4B2" ], [ "CLK_FEED_WW4B3", "INT_INTERFACE_WW4B3" ], [ "CLK_FEED_WW4C0", "INT_INTERFACE_WW4C0" ], [ "CLK_FEED_WW4C1", "INT_INTERFACE_WW4C1" ], [ "CLK_FEED_WW4C2", "INT_INTERFACE_WW4C2" ], [ "CLK_FEED_WW4C3", "INT_INTERFACE_WW4C3" ], [ "CLK_FEED_WW4END0", "INT_INTERFACE_WW4END0" ], [ "CLK_FEED_WW4END1", "INT_INTERFACE_WW4END1" ], [ "CLK_FEED_WW4END2", "INT_INTERFACE_WW4END2" ], [ "CLK_FEED_WW4END3", "INT_INTERFACE_WW4END3" ], [ "CLK_PMV_BYP0_0", "INT_INTERFACE_BYP0" ], [ "CLK_PMV_BYP1_0", "INT_INTERFACE_BYP1" ], [ "CLK_PMV_BYP2_0", "INT_INTERFACE_BYP2" ], [ "CLK_PMV_BYP3_0", "INT_INTERFACE_BYP3" ], [ "CLK_PMV_BYP4_0", "INT_INTERFACE_BYP4" ], [ "CLK_PMV_BYP5_0", "INT_INTERFACE_BYP5" ], [ "CLK_PMV_BYP6_0", "INT_INTERFACE_BYP6" ], [ "CLK_PMV_BYP7_0", "INT_INTERFACE_BYP7" ], [ "CLK_PMV_CLK0_0", "INT_INTERFACE_CLK0" ], [ "CLK_PMV_CLK1_0", "INT_INTERFACE_CLK1" ], [ "CLK_PMV_CTRL0_0", "INT_INTERFACE_CTRL0" ], [ "CLK_PMV_CTRL1_0", "INT_INTERFACE_CTRL1" ], [ "CLK_PMV_FAN0_0", "INT_INTERFACE_FAN0" ], [ "CLK_PMV_FAN1_0", "INT_INTERFACE_FAN1" ], [ "CLK_PMV_FAN2_0", "INT_INTERFACE_FAN2" ], [ "CLK_PMV_FAN3_0", "INT_INTERFACE_FAN3" ], [ "CLK_PMV_FAN4_0", "INT_INTERFACE_FAN4" ], [ "CLK_PMV_FAN5_0", "INT_INTERFACE_FAN5" ], [ "CLK_PMV_FAN6_0", "INT_INTERFACE_FAN6" ], [ "CLK_PMV_FAN7_0", "INT_INTERFACE_FAN7" ], [ "CLK_PMV_IMUX0_0", "INT_INTERFACE_IMUX0" ], [ "CLK_PMV_IMUX1_0", "INT_INTERFACE_IMUX1" ], [ "CLK_PMV_IMUX2_0", "INT_INTERFACE_IMUX2" ], [ "CLK_PMV_IMUX3_0", "INT_INTERFACE_IMUX3" ], [ "CLK_PMV_IMUX4_0", "INT_INTERFACE_IMUX4" ], [ "CLK_PMV_IMUX5_0", "INT_INTERFACE_IMUX5" ], [ "CLK_PMV_IMUX6_0", "INT_INTERFACE_IMUX6" ], [ "CLK_PMV_IMUX7_0", "INT_INTERFACE_IMUX7" ], [ "CLK_PMV_IMUX8_0", "INT_INTERFACE_IMUX8" ], [ "CLK_PMV_IMUX9_0", "INT_INTERFACE_IMUX9" ], [ "CLK_PMV_IMUX10_0", "INT_INTERFACE_IMUX10" ], [ "CLK_PMV_IMUX11_0", "INT_INTERFACE_IMUX11" ], [ "CLK_PMV_IMUX12_0", "INT_INTERFACE_IMUX12" ], [ "CLK_PMV_IMUX13_0", "INT_INTERFACE_IMUX13" ], [ "CLK_PMV_IMUX14_0", "INT_INTERFACE_IMUX14" ], [ "CLK_PMV_IMUX15_0", "INT_INTERFACE_IMUX15" ], [ "CLK_PMV_IMUX16_0", "INT_INTERFACE_IMUX16" ], [ "CLK_PMV_IMUX17_0", "INT_INTERFACE_IMUX17" ], [ "CLK_PMV_IMUX18_0", "INT_INTERFACE_IMUX18" ], [ "CLK_PMV_IMUX19_0", "INT_INTERFACE_IMUX19" ], [ "CLK_PMV_IMUX20_0", "INT_INTERFACE_IMUX20" ], [ "CLK_PMV_IMUX21_0", "INT_INTERFACE_IMUX21" ], [ "CLK_PMV_IMUX22_0", "INT_INTERFACE_IMUX22" ], [ "CLK_PMV_IMUX23_0", "INT_INTERFACE_IMUX23" ], [ "CLK_PMV_IMUX24_0", "INT_INTERFACE_IMUX24" ], [ "CLK_PMV_IMUX25_0", "INT_INTERFACE_IMUX25" ], [ "CLK_PMV_IMUX26_0", "INT_INTERFACE_IMUX26" ], [ "CLK_PMV_IMUX27_0", "INT_INTERFACE_IMUX27" ], [ "CLK_PMV_IMUX28_0", "INT_INTERFACE_IMUX28" ], [ "CLK_PMV_IMUX29_0", "INT_INTERFACE_IMUX29" ], [ "CLK_PMV_IMUX30_0", "INT_INTERFACE_IMUX30" ], [ "CLK_PMV_IMUX31_0", "INT_INTERFACE_IMUX31" ], [ "CLK_PMV_IMUX32_0", "INT_INTERFACE_IMUX32" ], [ "CLK_PMV_IMUX33_0", "INT_INTERFACE_IMUX33" ], [ "CLK_PMV_IMUX34_0", "INT_INTERFACE_IMUX34" ], [ "CLK_PMV_IMUX35_0", "INT_INTERFACE_IMUX35" ], [ "CLK_PMV_IMUX36_0", "INT_INTERFACE_IMUX36" ], [ "CLK_PMV_IMUX37_0", "INT_INTERFACE_IMUX37" ], [ "CLK_PMV_IMUX38_0", "INT_INTERFACE_IMUX38" ], [ "CLK_PMV_IMUX39_0", "INT_INTERFACE_IMUX39" ], [ "CLK_PMV_IMUX40_0", "INT_INTERFACE_IMUX40" ], [ "CLK_PMV_IMUX41_0", "INT_INTERFACE_IMUX41" ], [ "CLK_PMV_IMUX42_0", "INT_INTERFACE_IMUX42" ], [ "CLK_PMV_IMUX43_0", "INT_INTERFACE_IMUX43" ], [ "CLK_PMV_IMUX44_0", "INT_INTERFACE_IMUX44" ], [ "CLK_PMV_IMUX45_0", "INT_INTERFACE_IMUX45" ], [ "CLK_PMV_IMUX46_0", "INT_INTERFACE_IMUX46" ], [ "CLK_PMV_IMUX47_0", "INT_INTERFACE_IMUX47" ], [ "CLK_PMV_LOGIC_OUTS5_0", "INT_INTERFACE_LOGIC_OUTS_B5" ], [ "CLK_PMV_LOGIC_OUTS9_0", "INT_INTERFACE_LOGIC_OUTS_B9" ], [ "CLK_PMV_LOGIC_OUTS19_0", "INT_INTERFACE_LOGIC_OUTS_B19" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLK_PMV2_SVT", "VBRK" ], "wire_pairs": [ [ "CLK_FEED_EE2A0", "VBRK_EE2A0" ], [ "CLK_FEED_EE2A1", "VBRK_EE2A1" ], [ "CLK_FEED_EE2A2", "VBRK_EE2A2" ], [ "CLK_FEED_EE2A3", "VBRK_EE2A3" ], [ "CLK_FEED_EE2BEG0", "VBRK_EE2BEG0" ], [ "CLK_FEED_EE2BEG1", "VBRK_EE2BEG1" ], [ "CLK_FEED_EE2BEG2", "VBRK_EE2BEG2" ], [ "CLK_FEED_EE2BEG3", "VBRK_EE2BEG3" ], [ "CLK_FEED_EE4A0", "VBRK_EE4A0" ], [ "CLK_FEED_EE4A1", "VBRK_EE4A1" ], [ "CLK_FEED_EE4A2", "VBRK_EE4A2" ], [ "CLK_FEED_EE4A3", "VBRK_EE4A3" ], [ "CLK_FEED_EE4B0", "VBRK_EE4B0" ], [ "CLK_FEED_EE4B1", "VBRK_EE4B1" ], [ "CLK_FEED_EE4B2", "VBRK_EE4B2" ], [ "CLK_FEED_EE4B3", "VBRK_EE4B3" ], [ "CLK_FEED_EE4BEG0", "VBRK_EE4BEG0" ], [ "CLK_FEED_EE4BEG1", "VBRK_EE4BEG1" ], [ "CLK_FEED_EE4BEG2", "VBRK_EE4BEG2" ], [ "CLK_FEED_EE4BEG3", "VBRK_EE4BEG3" ], [ "CLK_FEED_EE4C0", "VBRK_EE4C0" ], [ "CLK_FEED_EE4C1", "VBRK_EE4C1" ], [ "CLK_FEED_EE4C2", "VBRK_EE4C2" ], [ "CLK_FEED_EE4C3", "VBRK_EE4C3" ], [ "CLK_FEED_EL1BEG0", "VBRK_EL1BEG0" ], [ "CLK_FEED_EL1BEG1", "VBRK_EL1BEG1" ], [ "CLK_FEED_EL1BEG2", "VBRK_EL1BEG2" ], [ "CLK_FEED_EL1BEG3", "VBRK_EL1BEG3" ], [ "CLK_FEED_ER1BEG0", "VBRK_ER1BEG0" ], [ "CLK_FEED_ER1BEG1", "VBRK_ER1BEG1" ], [ "CLK_FEED_ER1BEG2", "VBRK_ER1BEG2" ], [ "CLK_FEED_ER1BEG3", "VBRK_ER1BEG3" ], [ "CLK_FEED_LH1", "VBRK_LH1" ], [ "CLK_FEED_LH2", "VBRK_LH2" ], [ "CLK_FEED_LH3", "VBRK_LH3" ], [ "CLK_FEED_LH4", "VBRK_LH4" ], [ "CLK_FEED_LH5", "VBRK_LH5" ], [ "CLK_FEED_LH6", "VBRK_LH6" ], [ "CLK_FEED_LH7", "VBRK_LH7" ], [ "CLK_FEED_LH8", "VBRK_LH8" ], [ "CLK_FEED_LH9", "VBRK_LH9" ], [ "CLK_FEED_LH10", "VBRK_LH10" ], [ "CLK_FEED_LH11", "VBRK_LH11" ], [ "CLK_FEED_LH12", "VBRK_LH12" ], [ "CLK_FEED_NE2A0", "VBRK_NE2A0" ], [ "CLK_FEED_NE2A1", "VBRK_NE2A1" ], [ "CLK_FEED_NE2A2", "VBRK_NE2A2" ], [ "CLK_FEED_NE2A3", "VBRK_NE2A3" ], [ "CLK_FEED_NE4BEG0", "VBRK_NE4BEG0" ], [ "CLK_FEED_NE4BEG1", "VBRK_NE4BEG1" ], [ "CLK_FEED_NE4BEG2", "VBRK_NE4BEG2" ], [ "CLK_FEED_NE4BEG3", "VBRK_NE4BEG3" ], [ "CLK_FEED_NE4C0", "VBRK_NE4C0" ], [ "CLK_FEED_NE4C1", "VBRK_NE4C1" ], [ "CLK_FEED_NE4C2", "VBRK_NE4C2" ], [ "CLK_FEED_NE4C3", "VBRK_NE4C3" ], [ "CLK_FEED_NW2A0", "VBRK_NW2A0" ], [ "CLK_FEED_NW2A1", "VBRK_NW2A1" ], [ "CLK_FEED_NW2A2", "VBRK_NW2A2" ], [ "CLK_FEED_NW2A3", "VBRK_NW2A3" ], [ "CLK_FEED_NW4A0", "VBRK_NW4A0" ], [ "CLK_FEED_NW4A1", "VBRK_NW4A1" ], [ "CLK_FEED_NW4A2", "VBRK_NW4A2" ], [ "CLK_FEED_NW4A3", "VBRK_NW4A3" ], [ "CLK_FEED_NW4END0", "VBRK_NW4END0" ], [ "CLK_FEED_NW4END1", "VBRK_NW4END1" ], [ "CLK_FEED_NW4END2", "VBRK_NW4END2" ], [ "CLK_FEED_NW4END3", "VBRK_NW4END3" ], [ "CLK_FEED_SE2A0", "VBRK_SE2A0" ], [ "CLK_FEED_SE2A1", "VBRK_SE2A1" ], [ "CLK_FEED_SE2A2", "VBRK_SE2A2" ], [ "CLK_FEED_SE2A3", "VBRK_SE2A3" ], [ "CLK_FEED_SE4BEG0", "VBRK_SE4BEG0" ], [ "CLK_FEED_SE4BEG1", "VBRK_SE4BEG1" ], [ "CLK_FEED_SE4BEG2", "VBRK_SE4BEG2" ], [ "CLK_FEED_SE4BEG3", "VBRK_SE4BEG3" ], [ "CLK_FEED_SE4C0", "VBRK_SE4C0" ], [ "CLK_FEED_SE4C1", "VBRK_SE4C1" ], [ "CLK_FEED_SE4C2", "VBRK_SE4C2" ], [ "CLK_FEED_SE4C3", "VBRK_SE4C3" ], [ "CLK_FEED_SW2A0", "VBRK_SW2A0" ], [ "CLK_FEED_SW2A1", "VBRK_SW2A1" ], [ "CLK_FEED_SW2A2", "VBRK_SW2A2" ], [ "CLK_FEED_SW2A3", "VBRK_SW2A3" ], [ "CLK_FEED_SW4A0", "VBRK_SW4A0" ], [ "CLK_FEED_SW4A1", "VBRK_SW4A1" ], [ "CLK_FEED_SW4A2", "VBRK_SW4A2" ], [ "CLK_FEED_SW4A3", "VBRK_SW4A3" ], [ "CLK_FEED_SW4END0", "VBRK_SW4END0" ], [ "CLK_FEED_SW4END1", "VBRK_SW4END1" ], [ "CLK_FEED_SW4END2", "VBRK_SW4END2" ], [ "CLK_FEED_SW4END3", "VBRK_SW4END3" ], [ "CLK_FEED_WL1END0", "VBRK_WL1END0" ], [ "CLK_FEED_WL1END1", "VBRK_WL1END1" ], [ "CLK_FEED_WL1END2", "VBRK_WL1END2" ], [ "CLK_FEED_WL1END3", "VBRK_WL1END3" ], [ "CLK_FEED_WR1END0", "VBRK_WR1END0" ], [ "CLK_FEED_WR1END1", "VBRK_WR1END1" ], [ "CLK_FEED_WR1END2", "VBRK_WR1END2" ], [ "CLK_FEED_WR1END3", "VBRK_WR1END3" ], [ "CLK_FEED_WW2A0", "VBRK_WW2A0" ], [ "CLK_FEED_WW2A1", "VBRK_WW2A1" ], [ "CLK_FEED_WW2A2", "VBRK_WW2A2" ], [ "CLK_FEED_WW2A3", "VBRK_WW2A3" ], [ "CLK_FEED_WW2END0", "VBRK_WW2END0" ], [ "CLK_FEED_WW2END1", "VBRK_WW2END1" ], [ "CLK_FEED_WW2END2", "VBRK_WW2END2" ], [ "CLK_FEED_WW2END3", "VBRK_WW2END3" ], [ "CLK_FEED_WW4A0", "VBRK_WW4A0" ], [ "CLK_FEED_WW4A1", "VBRK_WW4A1" ], [ "CLK_FEED_WW4A2", "VBRK_WW4A2" ], [ "CLK_FEED_WW4A3", "VBRK_WW4A3" ], [ "CLK_FEED_WW4B0", "VBRK_WW4B0" ], [ "CLK_FEED_WW4B1", "VBRK_WW4B1" ], [ "CLK_FEED_WW4B2", "VBRK_WW4B2" ], [ "CLK_FEED_WW4B3", "VBRK_WW4B3" ], [ "CLK_FEED_WW4C0", "VBRK_WW4C0" ], [ "CLK_FEED_WW4C1", "VBRK_WW4C1" ], [ "CLK_FEED_WW4C2", "VBRK_WW4C2" ], [ "CLK_FEED_WW4C3", "VBRK_WW4C3" ], [ "CLK_FEED_WW4END0", "VBRK_WW4END0" ], [ "CLK_FEED_WW4END1", "VBRK_WW4END1" ], [ "CLK_FEED_WW4END2", "VBRK_WW4END2" ], [ "CLK_FEED_WW4END3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, 0 ], "tile_types": [ "CLK_PMVIOB", "INT_INTERFACE_R" ], "wire_pairs": [ [ "CLK_FEED_EE2A0", "INT_INTERFACE_EE2A0" ], [ "CLK_FEED_EE2A1", "INT_INTERFACE_EE2A1" ], [ "CLK_FEED_EE2A2", "INT_INTERFACE_EE2A2" ], [ "CLK_FEED_EE2A3", "INT_INTERFACE_EE2A3" ], [ "CLK_FEED_EE2BEG0", "INT_INTERFACE_EE2BEG0" ], [ "CLK_FEED_EE2BEG1", "INT_INTERFACE_EE2BEG1" ], [ "CLK_FEED_EE2BEG2", "INT_INTERFACE_EE2BEG2" ], [ "CLK_FEED_EE2BEG3", "INT_INTERFACE_EE2BEG3" ], [ "CLK_FEED_EE4A0", "INT_INTERFACE_EE4A0" ], [ "CLK_FEED_EE4A1", "INT_INTERFACE_EE4A1" ], [ "CLK_FEED_EE4A2", "INT_INTERFACE_EE4A2" ], [ "CLK_FEED_EE4A3", "INT_INTERFACE_EE4A3" ], [ "CLK_FEED_EE4B0", "INT_INTERFACE_EE4B0" ], [ "CLK_FEED_EE4B1", "INT_INTERFACE_EE4B1" ], [ "CLK_FEED_EE4B2", "INT_INTERFACE_EE4B2" ], [ "CLK_FEED_EE4B3", "INT_INTERFACE_EE4B3" ], [ "CLK_FEED_EE4BEG0", "INT_INTERFACE_EE4BEG0" ], [ "CLK_FEED_EE4BEG1", "INT_INTERFACE_EE4BEG1" ], [ "CLK_FEED_EE4BEG2", "INT_INTERFACE_EE4BEG2" ], [ "CLK_FEED_EE4BEG3", "INT_INTERFACE_EE4BEG3" ], [ "CLK_FEED_EE4C0", "INT_INTERFACE_EE4C0" ], [ "CLK_FEED_EE4C1", "INT_INTERFACE_EE4C1" ], [ "CLK_FEED_EE4C2", "INT_INTERFACE_EE4C2" ], [ "CLK_FEED_EE4C3", "INT_INTERFACE_EE4C3" ], [ "CLK_FEED_EL1BEG0", "INT_INTERFACE_EL1BEG0" ], [ "CLK_FEED_EL1BEG1", "INT_INTERFACE_EL1BEG1" ], [ "CLK_FEED_EL1BEG2", "INT_INTERFACE_EL1BEG2" ], [ "CLK_FEED_EL1BEG3", "INT_INTERFACE_EL1BEG3" ], [ "CLK_FEED_ER1BEG0", "INT_INTERFACE_ER1BEG0" ], [ "CLK_FEED_ER1BEG1", "INT_INTERFACE_ER1BEG1" ], [ "CLK_FEED_ER1BEG2", "INT_INTERFACE_ER1BEG2" ], [ "CLK_FEED_ER1BEG3", "INT_INTERFACE_ER1BEG3" ], [ "CLK_FEED_LH1", "INT_INTERFACE_LH1" ], [ "CLK_FEED_LH2", "INT_INTERFACE_LH2" ], [ "CLK_FEED_LH3", "INT_INTERFACE_LH3" ], [ "CLK_FEED_LH4", "INT_INTERFACE_LH4" ], [ "CLK_FEED_LH5", "INT_INTERFACE_LH5" ], [ "CLK_FEED_LH6", "INT_INTERFACE_LH6" ], [ "CLK_FEED_LH7", "INT_INTERFACE_LH7" ], [ "CLK_FEED_LH8", "INT_INTERFACE_LH8" ], [ "CLK_FEED_LH9", "INT_INTERFACE_LH9" ], [ "CLK_FEED_LH10", "INT_INTERFACE_LH10" ], [ "CLK_FEED_LH11", "INT_INTERFACE_LH11" ], [ "CLK_FEED_LH12", "INT_INTERFACE_LH12" ], [ "CLK_FEED_MONITOR_N", "INT_INTERFACE_MONITOR_N" ], [ "CLK_FEED_MONITOR_P", "INT_INTERFACE_MONITOR_P" ], [ "CLK_FEED_NE2A0", "INT_INTERFACE_NE2A0" ], [ "CLK_FEED_NE2A1", "INT_INTERFACE_NE2A1" ], [ "CLK_FEED_NE2A2", "INT_INTERFACE_NE2A2" ], [ "CLK_FEED_NE2A3", "INT_INTERFACE_NE2A3" ], [ "CLK_FEED_NE4BEG0", "INT_INTERFACE_NE4BEG0" ], [ "CLK_FEED_NE4BEG1", "INT_INTERFACE_NE4BEG1" ], [ "CLK_FEED_NE4BEG2", "INT_INTERFACE_NE4BEG2" ], [ "CLK_FEED_NE4BEG3", "INT_INTERFACE_NE4BEG3" ], [ "CLK_FEED_NE4C0", "INT_INTERFACE_NE4C0" ], [ "CLK_FEED_NE4C1", "INT_INTERFACE_NE4C1" ], [ "CLK_FEED_NE4C2", "INT_INTERFACE_NE4C2" ], [ "CLK_FEED_NE4C3", "INT_INTERFACE_NE4C3" ], [ "CLK_FEED_NW2A0", "INT_INTERFACE_NW2A0" ], [ "CLK_FEED_NW2A1", "INT_INTERFACE_NW2A1" ], [ "CLK_FEED_NW2A2", "INT_INTERFACE_NW2A2" ], [ "CLK_FEED_NW2A3", "INT_INTERFACE_NW2A3" ], [ "CLK_FEED_NW4A0", "INT_INTERFACE_NW4A0" ], [ "CLK_FEED_NW4A1", "INT_INTERFACE_NW4A1" ], [ "CLK_FEED_NW4A2", "INT_INTERFACE_NW4A2" ], [ "CLK_FEED_NW4A3", "INT_INTERFACE_NW4A3" ], [ "CLK_FEED_NW4END0", "INT_INTERFACE_NW4END0" ], [ "CLK_FEED_NW4END1", "INT_INTERFACE_NW4END1" ], [ "CLK_FEED_NW4END2", "INT_INTERFACE_NW4END2" ], [ "CLK_FEED_NW4END3", "INT_INTERFACE_NW4END3" ], [ "CLK_FEED_SE2A0", "INT_INTERFACE_SE2A0" ], [ "CLK_FEED_SE2A1", "INT_INTERFACE_SE2A1" ], [ "CLK_FEED_SE2A2", "INT_INTERFACE_SE2A2" ], [ "CLK_FEED_SE2A3", "INT_INTERFACE_SE2A3" ], [ "CLK_FEED_SE4BEG0", "INT_INTERFACE_SE4BEG0" ], [ "CLK_FEED_SE4BEG1", "INT_INTERFACE_SE4BEG1" ], [ "CLK_FEED_SE4BEG2", "INT_INTERFACE_SE4BEG2" ], [ "CLK_FEED_SE4BEG3", "INT_INTERFACE_SE4BEG3" ], [ "CLK_FEED_SE4C0", "INT_INTERFACE_SE4C0" ], [ "CLK_FEED_SE4C1", "INT_INTERFACE_SE4C1" ], [ "CLK_FEED_SE4C2", "INT_INTERFACE_SE4C2" ], [ "CLK_FEED_SE4C3", "INT_INTERFACE_SE4C3" ], [ "CLK_FEED_SW2A0", "INT_INTERFACE_SW2A0" ], [ "CLK_FEED_SW2A1", "INT_INTERFACE_SW2A1" ], [ "CLK_FEED_SW2A2", "INT_INTERFACE_SW2A2" ], [ "CLK_FEED_SW2A3", "INT_INTERFACE_SW2A3" ], [ "CLK_FEED_SW4A0", "INT_INTERFACE_SW4A0" ], [ "CLK_FEED_SW4A1", "INT_INTERFACE_SW4A1" ], [ "CLK_FEED_SW4A2", "INT_INTERFACE_SW4A2" ], [ "CLK_FEED_SW4A3", "INT_INTERFACE_SW4A3" ], [ "CLK_FEED_SW4END0", "INT_INTERFACE_SW4END0" ], [ "CLK_FEED_SW4END1", "INT_INTERFACE_SW4END1" ], [ "CLK_FEED_SW4END2", "INT_INTERFACE_SW4END2" ], [ "CLK_FEED_SW4END3", "INT_INTERFACE_SW4END3" ], [ "CLK_FEED_WL1END0", "INT_INTERFACE_WL1END0" ], [ "CLK_FEED_WL1END1", "INT_INTERFACE_WL1END1" ], [ "CLK_FEED_WL1END2", "INT_INTERFACE_WL1END2" ], [ "CLK_FEED_WL1END3", "INT_INTERFACE_WL1END3" ], [ "CLK_FEED_WR1END0", "INT_INTERFACE_WR1END0" ], [ "CLK_FEED_WR1END1", "INT_INTERFACE_WR1END1" ], [ "CLK_FEED_WR1END2", "INT_INTERFACE_WR1END2" ], [ "CLK_FEED_WR1END3", "INT_INTERFACE_WR1END3" ], [ "CLK_FEED_WW2A0", "INT_INTERFACE_WW2A0" ], [ "CLK_FEED_WW2A1", "INT_INTERFACE_WW2A1" ], [ "CLK_FEED_WW2A2", "INT_INTERFACE_WW2A2" ], [ "CLK_FEED_WW2A3", "INT_INTERFACE_WW2A3" ], [ "CLK_FEED_WW2END0", "INT_INTERFACE_WW2END0" ], [ "CLK_FEED_WW2END1", "INT_INTERFACE_WW2END1" ], [ "CLK_FEED_WW2END2", "INT_INTERFACE_WW2END2" ], [ "CLK_FEED_WW2END3", "INT_INTERFACE_WW2END3" ], [ "CLK_FEED_WW4A0", "INT_INTERFACE_WW4A0" ], [ "CLK_FEED_WW4A1", "INT_INTERFACE_WW4A1" ], [ "CLK_FEED_WW4A2", "INT_INTERFACE_WW4A2" ], [ "CLK_FEED_WW4A3", "INT_INTERFACE_WW4A3" ], [ "CLK_FEED_WW4B0", "INT_INTERFACE_WW4B0" ], [ "CLK_FEED_WW4B1", "INT_INTERFACE_WW4B1" ], [ "CLK_FEED_WW4B2", "INT_INTERFACE_WW4B2" ], [ "CLK_FEED_WW4B3", "INT_INTERFACE_WW4B3" ], [ "CLK_FEED_WW4C0", "INT_INTERFACE_WW4C0" ], [ "CLK_FEED_WW4C1", "INT_INTERFACE_WW4C1" ], [ "CLK_FEED_WW4C2", "INT_INTERFACE_WW4C2" ], [ "CLK_FEED_WW4C3", "INT_INTERFACE_WW4C3" ], [ "CLK_FEED_WW4END0", "INT_INTERFACE_WW4END0" ], [ "CLK_FEED_WW4END1", "INT_INTERFACE_WW4END1" ], [ "CLK_FEED_WW4END2", "INT_INTERFACE_WW4END2" ], [ "CLK_FEED_WW4END3", "INT_INTERFACE_WW4END3" ], [ "CLK_PMV_BYP0_0", "INT_INTERFACE_BYP0" ], [ "CLK_PMV_BYP1_0", "INT_INTERFACE_BYP1" ], [ "CLK_PMV_BYP2_0", "INT_INTERFACE_BYP2" ], [ "CLK_PMV_BYP3_0", "INT_INTERFACE_BYP3" ], [ "CLK_PMV_BYP4_0", "INT_INTERFACE_BYP4" ], [ "CLK_PMV_BYP5_0", "INT_INTERFACE_BYP5" ], [ "CLK_PMV_BYP6_0", "INT_INTERFACE_BYP6" ], [ "CLK_PMV_BYP7_0", "INT_INTERFACE_BYP7" ], [ "CLK_PMV_CLK0_0", "INT_INTERFACE_CLK0" ], [ "CLK_PMV_CLK1_0", "INT_INTERFACE_CLK1" ], [ "CLK_PMV_CTRL0_0", "INT_INTERFACE_CTRL0" ], [ "CLK_PMV_CTRL1_0", "INT_INTERFACE_CTRL1" ], [ "CLK_PMV_FAN0_0", "INT_INTERFACE_FAN0" ], [ "CLK_PMV_FAN1_0", "INT_INTERFACE_FAN1" ], [ "CLK_PMV_FAN2_0", "INT_INTERFACE_FAN2" ], [ "CLK_PMV_FAN3_0", "INT_INTERFACE_FAN3" ], [ "CLK_PMV_FAN4_0", "INT_INTERFACE_FAN4" ], [ "CLK_PMV_FAN5_0", "INT_INTERFACE_FAN5" ], [ "CLK_PMV_FAN6_0", "INT_INTERFACE_FAN6" ], [ "CLK_PMV_FAN7_0", "INT_INTERFACE_FAN7" ], [ "CLK_PMV_IMUX0_0", "INT_INTERFACE_IMUX0" ], [ "CLK_PMV_IMUX1_0", "INT_INTERFACE_IMUX1" ], [ "CLK_PMV_IMUX2_0", "INT_INTERFACE_IMUX2" ], [ "CLK_PMV_IMUX3_0", "INT_INTERFACE_IMUX3" ], [ "CLK_PMV_IMUX4_0", "INT_INTERFACE_IMUX4" ], [ "CLK_PMV_IMUX5_0", "INT_INTERFACE_IMUX5" ], [ "CLK_PMV_IMUX6_0", "INT_INTERFACE_IMUX6" ], [ "CLK_PMV_IMUX7_0", "INT_INTERFACE_IMUX7" ], [ "CLK_PMV_IMUX8_0", "INT_INTERFACE_IMUX8" ], [ "CLK_PMV_IMUX9_0", "INT_INTERFACE_IMUX9" ], [ "CLK_PMV_IMUX10_0", "INT_INTERFACE_IMUX10" ], [ "CLK_PMV_IMUX11_0", "INT_INTERFACE_IMUX11" ], [ "CLK_PMV_IMUX12_0", "INT_INTERFACE_IMUX12" ], [ "CLK_PMV_IMUX13_0", "INT_INTERFACE_IMUX13" ], [ "CLK_PMV_IMUX14_0", "INT_INTERFACE_IMUX14" ], [ "CLK_PMV_IMUX15_0", "INT_INTERFACE_IMUX15" ], [ "CLK_PMV_IMUX16_0", "INT_INTERFACE_IMUX16" ], [ "CLK_PMV_IMUX17_0", "INT_INTERFACE_IMUX17" ], [ "CLK_PMV_IMUX18_0", "INT_INTERFACE_IMUX18" ], [ "CLK_PMV_IMUX19_0", "INT_INTERFACE_IMUX19" ], [ "CLK_PMV_IMUX20_0", "INT_INTERFACE_IMUX20" ], [ "CLK_PMV_IMUX21_0", "INT_INTERFACE_IMUX21" ], [ "CLK_PMV_IMUX22_0", "INT_INTERFACE_IMUX22" ], [ "CLK_PMV_IMUX23_0", "INT_INTERFACE_IMUX23" ], [ "CLK_PMV_IMUX24_0", "INT_INTERFACE_IMUX24" ], [ "CLK_PMV_IMUX25_0", "INT_INTERFACE_IMUX25" ], [ "CLK_PMV_IMUX26_0", "INT_INTERFACE_IMUX26" ], [ "CLK_PMV_IMUX27_0", "INT_INTERFACE_IMUX27" ], [ "CLK_PMV_IMUX28_0", "INT_INTERFACE_IMUX28" ], [ "CLK_PMV_IMUX29_0", "INT_INTERFACE_IMUX29" ], [ "CLK_PMV_IMUX30_0", "INT_INTERFACE_IMUX30" ], [ "CLK_PMV_IMUX31_0", "INT_INTERFACE_IMUX31" ], [ "CLK_PMV_IMUX32_0", "INT_INTERFACE_IMUX32" ], [ "CLK_PMV_IMUX33_0", "INT_INTERFACE_IMUX33" ], [ "CLK_PMV_IMUX34_0", "INT_INTERFACE_IMUX34" ], [ "CLK_PMV_IMUX35_0", "INT_INTERFACE_IMUX35" ], [ "CLK_PMV_IMUX36_0", "INT_INTERFACE_IMUX36" ], [ "CLK_PMV_IMUX37_0", "INT_INTERFACE_IMUX37" ], [ "CLK_PMV_IMUX38_0", "INT_INTERFACE_IMUX38" ], [ "CLK_PMV_IMUX39_0", "INT_INTERFACE_IMUX39" ], [ "CLK_PMV_IMUX40_0", "INT_INTERFACE_IMUX40" ], [ "CLK_PMV_IMUX41_0", "INT_INTERFACE_IMUX41" ], [ "CLK_PMV_IMUX42_0", "INT_INTERFACE_IMUX42" ], [ "CLK_PMV_IMUX43_0", "INT_INTERFACE_IMUX43" ], [ "CLK_PMV_IMUX44_0", "INT_INTERFACE_IMUX44" ], [ "CLK_PMV_IMUX45_0", "INT_INTERFACE_IMUX45" ], [ "CLK_PMV_IMUX46_0", "INT_INTERFACE_IMUX46" ], [ "CLK_PMV_IMUX47_0", "INT_INTERFACE_IMUX47" ], [ "CLK_PMV_LOGIC_OUTS0_0", "INT_INTERFACE_LOGIC_OUTS_B0" ], [ "CLK_PMV_LOGIC_OUTS1_0", "INT_INTERFACE_LOGIC_OUTS_B1" ], [ "CLK_PMV_LOGIC_OUTS2_0", "INT_INTERFACE_LOGIC_OUTS_B2" ] ] }, { "grid_deltas": [ 1, 0 ], "tile_types": [ "CLK_PMVIOB", "VBRK" ], "wire_pairs": [ [ "CLK_FEED_EE2A0", "VBRK_EE2A0" ], [ "CLK_FEED_EE2A1", "VBRK_EE2A1" ], [ "CLK_FEED_EE2A2", "VBRK_EE2A2" ], [ "CLK_FEED_EE2A3", "VBRK_EE2A3" ], [ "CLK_FEED_EE2BEG0", "VBRK_EE2BEG0" ], [ "CLK_FEED_EE2BEG1", "VBRK_EE2BEG1" ], [ "CLK_FEED_EE2BEG2", "VBRK_EE2BEG2" ], [ "CLK_FEED_EE2BEG3", "VBRK_EE2BEG3" ], [ "CLK_FEED_EE4A0", "VBRK_EE4A0" ], [ "CLK_FEED_EE4A1", "VBRK_EE4A1" ], [ "CLK_FEED_EE4A2", "VBRK_EE4A2" ], [ "CLK_FEED_EE4A3", "VBRK_EE4A3" ], [ "CLK_FEED_EE4B0", "VBRK_EE4B0" ], [ "CLK_FEED_EE4B1", "VBRK_EE4B1" ], [ "CLK_FEED_EE4B2", "VBRK_EE4B2" ], [ "CLK_FEED_EE4B3", "VBRK_EE4B3" ], [ "CLK_FEED_EE4BEG0", "VBRK_EE4BEG0" ], [ "CLK_FEED_EE4BEG1", "VBRK_EE4BEG1" ], [ "CLK_FEED_EE4BEG2", "VBRK_EE4BEG2" ], [ "CLK_FEED_EE4BEG3", "VBRK_EE4BEG3" ], [ "CLK_FEED_EE4C0", "VBRK_EE4C0" ], [ "CLK_FEED_EE4C1", "VBRK_EE4C1" ], [ "CLK_FEED_EE4C2", "VBRK_EE4C2" ], [ "CLK_FEED_EE4C3", "VBRK_EE4C3" ], [ "CLK_FEED_EL1BEG0", "VBRK_EL1BEG0" ], [ "CLK_FEED_EL1BEG1", "VBRK_EL1BEG1" ], [ "CLK_FEED_EL1BEG2", "VBRK_EL1BEG2" ], [ "CLK_FEED_EL1BEG3", "VBRK_EL1BEG3" ], [ "CLK_FEED_ER1BEG0", "VBRK_ER1BEG0" ], [ "CLK_FEED_ER1BEG1", "VBRK_ER1BEG1" ], [ "CLK_FEED_ER1BEG2", "VBRK_ER1BEG2" ], [ "CLK_FEED_ER1BEG3", "VBRK_ER1BEG3" ], [ "CLK_FEED_LH1", "VBRK_LH1" ], [ "CLK_FEED_LH2", "VBRK_LH2" ], [ "CLK_FEED_LH3", "VBRK_LH3" ], [ "CLK_FEED_LH4", "VBRK_LH4" ], [ "CLK_FEED_LH5", "VBRK_LH5" ], [ "CLK_FEED_LH6", "VBRK_LH6" ], [ "CLK_FEED_LH7", "VBRK_LH7" ], [ "CLK_FEED_LH8", "VBRK_LH8" ], [ "CLK_FEED_LH9", "VBRK_LH9" ], [ "CLK_FEED_LH10", "VBRK_LH10" ], [ "CLK_FEED_LH11", "VBRK_LH11" ], [ "CLK_FEED_LH12", "VBRK_LH12" ], [ "CLK_FEED_MONITOR_N", "VBRK_MONITOR_N" ], [ "CLK_FEED_MONITOR_P", "VBRK_MONITOR_P" ], [ "CLK_FEED_NE2A0", "VBRK_NE2A0" ], [ "CLK_FEED_NE2A1", "VBRK_NE2A1" ], [ "CLK_FEED_NE2A2", "VBRK_NE2A2" ], [ "CLK_FEED_NE2A3", "VBRK_NE2A3" ], [ "CLK_FEED_NE4BEG0", "VBRK_NE4BEG0" ], [ "CLK_FEED_NE4BEG1", "VBRK_NE4BEG1" ], [ "CLK_FEED_NE4BEG2", "VBRK_NE4BEG2" ], [ "CLK_FEED_NE4BEG3", "VBRK_NE4BEG3" ], [ "CLK_FEED_NE4C0", "VBRK_NE4C0" ], [ "CLK_FEED_NE4C1", "VBRK_NE4C1" ], [ "CLK_FEED_NE4C2", "VBRK_NE4C2" ], [ "CLK_FEED_NE4C3", "VBRK_NE4C3" ], [ "CLK_FEED_NW2A0", "VBRK_NW2A0" ], [ "CLK_FEED_NW2A1", "VBRK_NW2A1" ], [ "CLK_FEED_NW2A2", "VBRK_NW2A2" ], [ "CLK_FEED_NW2A3", "VBRK_NW2A3" ], [ "CLK_FEED_NW4A0", "VBRK_NW4A0" ], [ "CLK_FEED_NW4A1", "VBRK_NW4A1" ], [ "CLK_FEED_NW4A2", "VBRK_NW4A2" ], [ "CLK_FEED_NW4A3", "VBRK_NW4A3" ], [ "CLK_FEED_NW4END0", "VBRK_NW4END0" ], [ "CLK_FEED_NW4END1", "VBRK_NW4END1" ], [ "CLK_FEED_NW4END2", "VBRK_NW4END2" ], [ "CLK_FEED_NW4END3", "VBRK_NW4END3" ], [ "CLK_FEED_SE2A0", "VBRK_SE2A0" ], [ "CLK_FEED_SE2A1", "VBRK_SE2A1" ], [ "CLK_FEED_SE2A2", "VBRK_SE2A2" ], [ "CLK_FEED_SE2A3", "VBRK_SE2A3" ], [ "CLK_FEED_SE4BEG0", "VBRK_SE4BEG0" ], [ "CLK_FEED_SE4BEG1", "VBRK_SE4BEG1" ], [ "CLK_FEED_SE4BEG2", "VBRK_SE4BEG2" ], [ "CLK_FEED_SE4BEG3", "VBRK_SE4BEG3" ], [ "CLK_FEED_SE4C0", "VBRK_SE4C0" ], [ "CLK_FEED_SE4C1", "VBRK_SE4C1" ], [ "CLK_FEED_SE4C2", "VBRK_SE4C2" ], [ "CLK_FEED_SE4C3", "VBRK_SE4C3" ], [ "CLK_FEED_SW2A0", "VBRK_SW2A0" ], [ "CLK_FEED_SW2A1", "VBRK_SW2A1" ], [ "CLK_FEED_SW2A2", "VBRK_SW2A2" ], [ "CLK_FEED_SW2A3", "VBRK_SW2A3" ], [ "CLK_FEED_SW4A0", "VBRK_SW4A0" ], [ "CLK_FEED_SW4A1", "VBRK_SW4A1" ], [ "CLK_FEED_SW4A2", "VBRK_SW4A2" ], [ "CLK_FEED_SW4A3", "VBRK_SW4A3" ], [ "CLK_FEED_SW4END0", "VBRK_SW4END0" ], [ "CLK_FEED_SW4END1", "VBRK_SW4END1" ], [ "CLK_FEED_SW4END2", "VBRK_SW4END2" ], [ "CLK_FEED_SW4END3", "VBRK_SW4END3" ], [ "CLK_FEED_WL1END0", "VBRK_WL1END0" ], [ "CLK_FEED_WL1END1", "VBRK_WL1END1" ], [ "CLK_FEED_WL1END2", "VBRK_WL1END2" ], [ "CLK_FEED_WL1END3", "VBRK_WL1END3" ], [ "CLK_FEED_WR1END0", "VBRK_WR1END0" ], [ "CLK_FEED_WR1END1", "VBRK_WR1END1" ], [ "CLK_FEED_WR1END2", "VBRK_WR1END2" ], [ "CLK_FEED_WR1END3", "VBRK_WR1END3" ], [ "CLK_FEED_WW2A0", "VBRK_WW2A0" ], [ "CLK_FEED_WW2A1", "VBRK_WW2A1" ], [ "CLK_FEED_WW2A2", "VBRK_WW2A2" ], [ "CLK_FEED_WW2A3", "VBRK_WW2A3" ], [ "CLK_FEED_WW2END0", "VBRK_WW2END0" ], [ "CLK_FEED_WW2END1", "VBRK_WW2END1" ], [ "CLK_FEED_WW2END2", "VBRK_WW2END2" ], [ "CLK_FEED_WW2END3", "VBRK_WW2END3" ], [ "CLK_FEED_WW4A0", "VBRK_WW4A0" ], [ "CLK_FEED_WW4A1", "VBRK_WW4A1" ], [ "CLK_FEED_WW4A2", "VBRK_WW4A2" ], [ "CLK_FEED_WW4A3", "VBRK_WW4A3" ], [ "CLK_FEED_WW4B0", "VBRK_WW4B0" ], [ "CLK_FEED_WW4B1", "VBRK_WW4B1" ], [ "CLK_FEED_WW4B2", "VBRK_WW4B2" ], [ "CLK_FEED_WW4B3", "VBRK_WW4B3" ], [ "CLK_FEED_WW4C0", "VBRK_WW4C0" ], [ "CLK_FEED_WW4C1", "VBRK_WW4C1" ], [ "CLK_FEED_WW4C2", "VBRK_WW4C2" ], [ "CLK_FEED_WW4C3", "VBRK_WW4C3" ], [ "CLK_FEED_WW4END0", "VBRK_WW4END0" ], [ "CLK_FEED_WW4END1", "VBRK_WW4END1" ], [ "CLK_FEED_WW4END2", "VBRK_WW4END2" ], [ "CLK_FEED_WW4END3", "VBRK_WW4END3" ] ] }, { "grid_deltas": [ -1, -1 ], "tile_types": [ "CMT_FIFO_L", "CMT_TOP_L_LOWER_B" ], "wire_pairs": [ [ "CMT_FIFO_EE2A0_0", "CMT_TOP_EE2A0_1" ], [ "CMT_FIFO_EE2A0_1", "CMT_TOP_EE2A0_2" ], [ "CMT_FIFO_EE2A0_2", "CMT_TOP_EE2A0_3" ], [ "CMT_FIFO_EE2A0_3", "CMT_TOP_EE2A0_4" ], [ "CMT_FIFO_EE2A0_4", "CMT_TOP_EE2A0_5" ], [ "CMT_FIFO_EE2A0_5", "CMT_TOP_EE2A0_6" ], [ "CMT_FIFO_EE2A0_6", "CMT_TOP_EE2A0_7" ], [ "CMT_FIFO_EE2A0_7", "CMT_TOP_EE2A0_8" ], [ "CMT_FIFO_EE2A0_8", "CMT_TOP_EE2A0_9" ], [ "CMT_FIFO_EE2A0_9", "CMT_TOP_EE2A0_10" ], [ "CMT_FIFO_EE2A0_10", "CMT_TOP_EE2A0_11" ], [ "CMT_FIFO_EE2A0_11", "CMT_TOP_EE2A0_12" ], [ "CMT_FIFO_EE2A1_0", "CMT_TOP_EE2A1_1" ], [ "CMT_FIFO_EE2A1_1", "CMT_TOP_EE2A1_2" ], [ "CMT_FIFO_EE2A1_2", "CMT_TOP_EE2A1_3" ], [ "CMT_FIFO_EE2A1_3", "CMT_TOP_EE2A1_4" ], [ "CMT_FIFO_EE2A1_4", "CMT_TOP_EE2A1_5" ], [ "CMT_FIFO_EE2A1_5", "CMT_TOP_EE2A1_6" ], [ "CMT_FIFO_EE2A1_6", "CMT_TOP_EE2A1_7" ], [ "CMT_FIFO_EE2A1_7", "CMT_TOP_EE2A1_8" ], [ "CMT_FIFO_EE2A1_8", "CMT_TOP_EE2A1_9" ], [ "CMT_FIFO_EE2A1_9", "CMT_TOP_EE2A1_10" ], [ "CMT_FIFO_EE2A1_10", "CMT_TOP_EE2A1_11" ], [ "CMT_FIFO_EE2A1_11", "CMT_TOP_EE2A1_12" ], [ "CMT_FIFO_EE2A2_0", "CMT_TOP_EE2A2_1" ], [ "CMT_FIFO_EE2A2_1", "CMT_TOP_EE2A2_2" ], [ "CMT_FIFO_EE2A2_2", "CMT_TOP_EE2A2_3" ], [ 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