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"src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B6_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B16_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_DQSFOUND" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B18_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B1_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_A_ICLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_A_ICLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_ICLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ICLKDIV->CMT_PHASER_IN_A_WRCLK_TOFIFO": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_ICLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_ISERDESRST" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.115", "0.188", "0.216" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CMT_PHASER_IN_CA_RCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.100", "0.115", "0.188", "0.216" ], "in_cap": null, "res": "0.0" }, "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_A_RCLK0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_A_RCLK0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_RCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_A_WREN_TOFIFO": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_A_WREN_TOFIFO", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_CA_WRENABLE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B2_7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B15_7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B3_7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B21_7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B16_6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_DQSFOUND" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B14_7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B3_6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_B_ICLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_B_ICLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_ICLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_B_WRCLK_TOFIFO": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_ICLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_ISERDESRST" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.115", "0.188", "0.216" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CMT_PHASER_IN_DB_RCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.100", "0.115", "0.188", "0.216" ], "in_cap": null, "res": "0.0" }, "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_B_RCLK1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_B_RCLK1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_RCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_B_WREN_TOFIFO": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_B_WREN_TOFIFO", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_IN_DB_WRENABLE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO->CMT_PHASER_OUT_A_OCLKDIV": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_A_OCLKDIV", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90->>CMT_PHASER_B_OCLK90_TOIOI": { "can_invert": "0", "dst_to_src": { "delay": [ "0.036", "0.041", "0.065", "0.073" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CMT_PHASER_B_OCLK90_TOIOI", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.036", "0.041", "0.065", "0.073" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CMT_PHASER_OUT_B_OCLK1X_90" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK->>CMT_PHASER_B_OCLK_TOIOI": { "can_invert": "0", "dst_to_src": { "delay": [ "0.038", "0.043", "0.071", "0.080" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CMT_PHASER_B_OCLK_TOIOI", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.038", "0.043", "0.071", "0.080" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CMT_PHASER_OUT_B_OCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV->>CMT_PHASER_B_OCLKDIV_TOIOI": { "can_invert": "0", "dst_to_src": { "delay": [ "0.040", "0.045", "0.072", "0.081" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.040", "0.045", "0.072", "0.081" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CMT_PHASER_OUT_B_OCLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO->CMT_PHASER_OUT_B_OCLKDIV": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_B_OCLKDIV", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B16_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B14_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B16_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS0->CMT_PHASERA_CTSBUS0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASERA_CTSBUS0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS1->CMT_PHASERA_CTSBUS1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASERA_CTSBUS1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS0->CMT_PHASERA_DQSBUS0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASERA_DQSBUS0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS1->CMT_PHASERA_DQSBUS1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASERA_DQSBUS1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS0->CMT_PHASERA_DTSBUS0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASERA_DTSBUS0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS1->CMT_PHASERA_DTSBUS1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASERA_DTSBUS1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B23_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_A_OCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_A_OCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_OCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_A_OCLK1X_90": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_A_OCLK1X_90", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_A_RDCLK_TOFIFO": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B14_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_A_RDEN_TOFIFO": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_A_RDEN_TOFIFO", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_CA_RDENABLE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B6_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B16_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B15_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B10_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_B_OCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_B_OCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_OCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_B_OCLK1X_90": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_B_OCLK1X_90", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_B_RDCLK_TOFIFO": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_B_RDEN_TOFIFO": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_B_RDEN_TOFIFO", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_PHASER_OUT_DB_RDENABLE" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_1->CMT_PHASER_OUT_CA_SYSCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_CLK0_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_2->CMT_PHASER_IN_CA_SYSCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_CLK0_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_CLK0_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_6->CMT_PHASER_IN_DB_SYSCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_CLK0_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_8->>CMT_BOT_HCLKMUX_CLKINT_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CMT_TOP_CLK0_8" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK1_8->>CMT_BOT_HCLKMUX_CLKINT_1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CMT_TOP_CLK1_8" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_DIVIDERST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX0_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX0_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_DIVIDERST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX0_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_7->CMT_PHASER_IN_DB_RSTDQSFIND": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX0_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX1_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX2_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX8_3->CMT_PHASER_IN_CA_RSTDQSFIND": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX8_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX9_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX11_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX11_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX12_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX12_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX12_4->CMT_PHASER_IN_CA_RST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_RST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX12_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX13_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_5->CMT_PHASER_OUT_DB_FINEINC": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX13_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_6->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX13_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX14_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_FINEINC": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_FINEINC", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX14_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX14_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_5->CMT_PHASER_OUT_DB_COARSEENABLE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX14_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX14_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX14_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX15_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX15_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX15_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX19_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX19_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_DIVIDERST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX19_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX20_4->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX20_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX21_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX21_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX23_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_4->CMT_PHASER_OUT_DB_COUNTERREADEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX23_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_6->CMT_PHASER_IN_DB_COUNTERREADEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX23_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX25_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX25_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX25_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX25_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_RST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX27_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX27_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_4->CMT_PHASER_IN_CA_RANKSEL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX27_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX28_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX28_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX29_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERREADEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX29_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX29_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_5->CMT_PHASER_OUT_DB_FINEENABLE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX29_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_6->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX29_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX30_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_FINEENABLE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX30_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX30_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_5->CMT_PHASER_OUT_DB_EDGEADV": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX30_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX30_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX31_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX31_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_7->CMT_PHASER_IN_DB_RANKSEL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX31_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX32_2->CMT_PHASER_OUT_CA_FINEINC": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX32_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_EDGEADV": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX34_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX39_4->CMT_PHASER_OUT_DB_COUNTERLOADEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX39_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX41_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX43_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX43_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX43_4->CMT_PHASER_IN_CA_RANKSEL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_TOP_IMUX43_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": 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