{ "pips": { "GTX_COMMON.GTXE2_CLK0_2->GTXE2_COMMON_GTGREFCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_GTGREFCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_CLK0_2" }, "GTX_COMMON.GTXE2_CLK1_1->GTXE2_COMMON_DRPCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_CLK1_1" }, "GTX_COMMON.GTXE2_CLK1_3->GTXE2_COMMON_QPLLLOCKDETCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLLOCKDETCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_CLK1_3" }, "GTX_COMMON.GTXE2_COMMON_DRPDO0->GTXE2_LOGIC_OUTS_B15_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO0" }, "GTX_COMMON.GTXE2_COMMON_DRPDO1->GTXE2_LOGIC_OUTS_B11_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO1" }, "GTX_COMMON.GTXE2_COMMON_DRPDO2->GTXE2_LOGIC_OUTS_B13_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO2" }, "GTX_COMMON.GTXE2_COMMON_DRPDO3->GTXE2_LOGIC_OUTS_B9_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO3" }, "GTX_COMMON.GTXE2_COMMON_DRPDO4->GTXE2_LOGIC_OUTS_B10_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO4" }, "GTX_COMMON.GTXE2_COMMON_DRPDO5->GTXE2_LOGIC_OUTS_B14_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO5" }, "GTX_COMMON.GTXE2_COMMON_DRPDO6->GTXE2_LOGIC_OUTS_B8_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO6" }, "GTX_COMMON.GTXE2_COMMON_DRPDO7->GTXE2_LOGIC_OUTS_B12_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO7" }, "GTX_COMMON.GTXE2_COMMON_DRPDO8->GTXE2_LOGIC_OUTS_B15_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO8" }, "GTX_COMMON.GTXE2_COMMON_DRPDO9->GTXE2_LOGIC_OUTS_B11_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO9" }, "GTX_COMMON.GTXE2_COMMON_DRPDO10->GTXE2_LOGIC_OUTS_B13_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO10" }, "GTX_COMMON.GTXE2_COMMON_DRPDO11->GTXE2_LOGIC_OUTS_B9_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO11" }, "GTX_COMMON.GTXE2_COMMON_DRPDO12->GTXE2_LOGIC_OUTS_B10_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO12" }, "GTX_COMMON.GTXE2_COMMON_DRPDO13->GTXE2_LOGIC_OUTS_B14_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO13" }, "GTX_COMMON.GTXE2_COMMON_DRPDO14->GTXE2_LOGIC_OUTS_B8_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO14" }, "GTX_COMMON.GTXE2_COMMON_DRPDO15->GTXE2_LOGIC_OUTS_B12_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPDO15" }, "GTX_COMMON.GTXE2_COMMON_DRPRDY->GTXE2_LOGIC_OUTS_B21_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_DRPRDY" }, "GTX_COMMON.GTXE2_COMMON_GTQPLLOUTCLK->GTXE2_COMMON_QPLLOUTCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLOUTCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_GTQPLLOUTCLK" }, "GTX_COMMON.GTXE2_COMMON_GTQPLLOUTREFCLK->GTXE2_COMMON_QPLLOUTREFCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLOUTREFCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_GTQPLLOUTREFCLK" }, "GTX_COMMON.GTXE2_COMMON_NORTHREFCLK0->>GTXE2_COMMON_GTNORTHREFCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_GTNORTHREFCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_NORTHREFCLK0" }, "GTX_COMMON.GTXE2_COMMON_NORTHREFCLK1->>GTXE2_COMMON_GTNORTHREFCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_GTNORTHREFCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_NORTHREFCLK1" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR0->GTXE2_LOGIC_OUTS_B19_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR0" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR1->GTXE2_LOGIC_OUTS_B23_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR1" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR2->GTXE2_LOGIC_OUTS_B17_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR2" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR3->GTXE2_LOGIC_OUTS_B21_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR3" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR4->GTXE2_LOGIC_OUTS_B22_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR4" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR5->GTXE2_LOGIC_OUTS_B18_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR5" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR6->GTXE2_LOGIC_OUTS_B20_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR6" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR7->GTXE2_LOGIC_OUTS_B16_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR7" }, "GTX_COMMON.GTXE2_COMMON_QPLLFBCLKLOST->GTXE2_LOGIC_OUTS_B19_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_QPLLFBCLKLOST" }, "GTX_COMMON.GTXE2_COMMON_QPLLLOCK->GTXE2_LOGIC_OUTS_B14_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_QPLLLOCK" }, "GTX_COMMON.GTXE2_COMMON_QPLLREFCLKLOST->GTXE2_LOGIC_OUTS_B10_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_QPLLREFCLKLOST" }, "GTX_COMMON.GTXE2_COMMON_REFCLK0->>GTXE2_COMMON_GTREFCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_GTREFCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_REFCLK0" }, "GTX_COMMON.GTXE2_COMMON_REFCLK1->>GTXE2_COMMON_GTREFCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_GTREFCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_REFCLK1" }, "GTX_COMMON.GTXE2_COMMON_REFCLKOUTMONITOR->GTXE2_LOGIC_OUTS_B2_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_COMMON_REFCLKOUTMONITOR" }, "GTX_COMMON.GTXE2_COMMON_RXOUTCLK_0->>GTXE2_COMMON_MGT_CLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_MGT_CLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_RXOUTCLK_0" }, "GTX_COMMON.GTXE2_COMMON_RXOUTCLK_1->>GTXE2_COMMON_MGT_CLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_MGT_CLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_RXOUTCLK_1" }, "GTX_COMMON.GTXE2_COMMON_RXOUTCLK_2->>GTXE2_COMMON_MGT_CLK6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_MGT_CLK6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_RXOUTCLK_2" }, "GTX_COMMON.GTXE2_COMMON_RXOUTCLK_3->>GTXE2_COMMON_MGT_CLK7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_MGT_CLK7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_RXOUTCLK_3" }, "GTX_COMMON.GTXE2_COMMON_SOUTHREFCLK0->>GTXE2_COMMON_GTSOUTHREFCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_GTSOUTHREFCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_SOUTHREFCLK0" }, "GTX_COMMON.GTXE2_COMMON_SOUTHREFCLK1->>GTXE2_COMMON_GTSOUTHREFCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_GTSOUTHREFCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_SOUTHREFCLK1" }, "GTX_COMMON.GTXE2_COMMON_TXOUTCLK_0->>GTXE2_COMMON_MGT_CLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_MGT_CLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_TXOUTCLK_0" }, "GTX_COMMON.GTXE2_COMMON_TXOUTCLK_1->>GTXE2_COMMON_MGT_CLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_MGT_CLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_TXOUTCLK_1" }, "GTX_COMMON.GTXE2_COMMON_TXOUTCLK_2->>GTXE2_COMMON_MGT_CLK8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_MGT_CLK8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_TXOUTCLK_2" }, "GTX_COMMON.GTXE2_COMMON_TXOUTCLK_3->>GTXE2_COMMON_MGT_CLK9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "GTXE2_COMMON_MGT_CLK9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "GTXE2_COMMON_TXOUTCLK_3" }, "GTX_COMMON.GTXE2_CTRL0_3->GTXE2_COMMON_QPLLRESET": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRESET", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_CTRL0_3" }, "GTX_COMMON.GTXE2_CTRL1_2->GTXE2_COMMON_QPLLOUTRESET": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLOUTRESET", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_CTRL1_2" }, "GTX_COMMON.GTXE2_IMUX16_0->GTXE2_COMMON_DRPDI7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX16_0" }, "GTX_COMMON.GTXE2_IMUX16_1->GTXE2_COMMON_DRPDI15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX16_1" }, "GTX_COMMON.GTXE2_IMUX16_2->GTXE2_COMMON_QPLLRSVD20": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD20", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX16_2" }, "GTX_COMMON.GTXE2_IMUX16_3->GTXE2_COMMON_QPLLRSVD21": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD21", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX16_3" }, "GTX_COMMON.GTXE2_IMUX16_4->GTXE2_COMMON_QPLLRSVD22": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD22", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX16_4" }, "GTX_COMMON.GTXE2_IMUX16_5->GTXE2_COMMON_QPLLRSVD23": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD23", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX16_5" }, "GTX_COMMON.GTXE2_IMUX17_0->GTXE2_COMMON_DRPDI6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX17_0" }, "GTX_COMMON.GTXE2_IMUX17_1->GTXE2_COMMON_DRPDI14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX17_1" }, "GTX_COMMON.GTXE2_IMUX17_5->GTXE2_COMMON_QPLLRSVD24": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD24", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX17_5" }, "GTX_COMMON.GTXE2_IMUX18_0->GTXE2_COMMON_DRPDI3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX18_0" }, "GTX_COMMON.GTXE2_IMUX18_1->GTXE2_COMMON_DRPDI11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX18_1" }, "GTX_COMMON.GTXE2_IMUX18_2->GTXE2_COMMON_QPLLRSVD13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX18_2" }, "GTX_COMMON.GTXE2_IMUX18_3->GTXE2_COMMON_QPLLRSVD17": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD17", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX18_3" }, "GTX_COMMON.GTXE2_IMUX18_4->GTXE2_COMMON_QPLLRSVD111": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD111", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX18_4" }, "GTX_COMMON.GTXE2_IMUX18_5->GTXE2_COMMON_QPLLRSVD115": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD115", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX18_5" }, "GTX_COMMON.GTXE2_IMUX19_0->GTXE2_COMMON_DRPDI2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX19_0" }, "GTX_COMMON.GTXE2_IMUX19_1->GTXE2_COMMON_DRPDI10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX19_1" }, "GTX_COMMON.GTXE2_IMUX19_2->GTXE2_COMMON_QPLLRSVD12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX19_2" }, "GTX_COMMON.GTXE2_IMUX19_3->GTXE2_COMMON_QPLLRSVD16": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD16", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX19_3" }, "GTX_COMMON.GTXE2_IMUX19_4->GTXE2_COMMON_QPLLRSVD110": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD110", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX19_4" }, "GTX_COMMON.GTXE2_IMUX19_5->GTXE2_COMMON_QPLLRSVD114": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD114", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX19_5" }, "GTX_COMMON.GTXE2_IMUX20_0->GTXE2_COMMON_DRPDI5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX20_0" }, "GTX_COMMON.GTXE2_IMUX20_1->GTXE2_COMMON_DRPDI13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX20_1" }, "GTX_COMMON.GTXE2_IMUX20_2->GTXE2_COMMON_PMARSVD4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_PMARSVD4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX20_2" }, "GTX_COMMON.GTXE2_IMUX20_3->GTXE2_COMMON_PMARSVD5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_PMARSVD5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX20_3" }, "GTX_COMMON.GTXE2_IMUX20_4->GTXE2_COMMON_PMARSVD6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_PMARSVD6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX20_4" }, "GTX_COMMON.GTXE2_IMUX20_5->GTXE2_COMMON_PMARSVD7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_PMARSVD7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX20_5" }, "GTX_COMMON.GTXE2_IMUX21_0->GTXE2_COMMON_DRPDI4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX21_0" }, "GTX_COMMON.GTXE2_IMUX21_1->GTXE2_COMMON_DRPDI12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX21_1" }, "GTX_COMMON.GTXE2_IMUX21_2->GTXE2_COMMON_PMARSVD0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_PMARSVD0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX21_2" }, "GTX_COMMON.GTXE2_IMUX21_3->GTXE2_COMMON_PMARSVD1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_PMARSVD1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX21_3" }, "GTX_COMMON.GTXE2_IMUX21_4->GTXE2_COMMON_PMARSVD2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_PMARSVD2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX21_4" }, "GTX_COMMON.GTXE2_IMUX21_5->GTXE2_COMMON_PMARSVD3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_PMARSVD3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX21_5" }, "GTX_COMMON.GTXE2_IMUX22_0->GTXE2_COMMON_DRPDI1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX22_0" }, "GTX_COMMON.GTXE2_IMUX22_1->GTXE2_COMMON_DRPDI9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX22_1" }, "GTX_COMMON.GTXE2_IMUX22_2->GTXE2_COMMON_QPLLRSVD11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX22_2" }, "GTX_COMMON.GTXE2_IMUX22_3->GTXE2_COMMON_QPLLRSVD15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX22_3" }, "GTX_COMMON.GTXE2_IMUX22_4->GTXE2_COMMON_QPLLRSVD19": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD19", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX22_4" }, "GTX_COMMON.GTXE2_IMUX22_5->GTXE2_COMMON_QPLLRSVD113": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD113", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX22_5" }, "GTX_COMMON.GTXE2_IMUX23_0->GTXE2_COMMON_DRPDI0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX23_0" }, "GTX_COMMON.GTXE2_IMUX23_1->GTXE2_COMMON_DRPDI8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPDI8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX23_1" }, "GTX_COMMON.GTXE2_IMUX23_2->GTXE2_COMMON_QPLLRSVD10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX23_2" }, "GTX_COMMON.GTXE2_IMUX23_3->GTXE2_COMMON_QPLLRSVD14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX23_3" }, "GTX_COMMON.GTXE2_IMUX23_4->GTXE2_COMMON_QPLLRSVD18": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD18", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX23_4" }, "GTX_COMMON.GTXE2_IMUX23_5->GTXE2_COMMON_QPLLRSVD112": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLRSVD112", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX23_5" }, "GTX_COMMON.GTXE2_IMUX24_2->GTXE2_COMMON_DRPADDR0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPADDR0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX24_2" }, "GTX_COMMON.GTXE2_IMUX24_3->GTXE2_COMMON_QPLLLOCKEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLLOCKEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX24_3" }, "GTX_COMMON.GTXE2_IMUX25_2->GTXE2_COMMON_DRPADDR1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPADDR1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX25_2" }, "GTX_COMMON.GTXE2_IMUX26_2->GTXE2_COMMON_DRPADDR4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPADDR4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX26_2" }, "GTX_COMMON.GTXE2_IMUX26_3->IBUFDS_GTE2_0_CEB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTE2_0_CEB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX26_3" }, "GTX_COMMON.GTXE2_IMUX26_4->GTXE2_COMMON_BGRCALOVRD3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_BGRCALOVRD3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX26_4" }, "GTX_COMMON.GTXE2_IMUX26_5->GTXE2_COMMON_BGPDB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_BGPDB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX26_5" }, "GTX_COMMON.GTXE2_IMUX27_2->GTXE2_COMMON_DRPADDR5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPADDR5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX27_2" }, "GTX_COMMON.GTXE2_IMUX27_3->GTXE2_COMMON_QPLLREFCLKSEL2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLREFCLKSEL2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX27_3" }, "GTX_COMMON.GTXE2_IMUX27_4->GTXE2_COMMON_BGRCALOVRD2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_BGRCALOVRD2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX27_4" }, "GTX_COMMON.GTXE2_IMUX27_5->GTXE2_COMMON_BGMONITORENB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_BGMONITORENB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX27_5" }, "GTX_COMMON.GTXE2_IMUX28_2->GTXE2_COMMON_DRPADDR2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPADDR2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX28_2" }, "GTX_COMMON.GTXE2_IMUX28_3->GTXE2_COMMON_QPLLPD": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLPD", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX28_3" }, "GTX_COMMON.GTXE2_IMUX28_4->GTXE2_COMMON_RCALENB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_RCALENB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX28_4" }, "GTX_COMMON.GTXE2_IMUX29_0->GTXE2_COMMON_DRPWE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPWE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX29_0" }, "GTX_COMMON.GTXE2_IMUX29_1->GTXE2_COMMON_DRPEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX29_1" }, "GTX_COMMON.GTXE2_IMUX29_2->GTXE2_COMMON_DRPADDR3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPADDR3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX29_2" }, "GTX_COMMON.GTXE2_IMUX29_3->IBUFDS_GTE2_1_CEB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTE2_1_CEB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX29_3" }, "GTX_COMMON.GTXE2_IMUX29_4->GTXE2_COMMON_BGRCALOVRD4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_BGRCALOVRD4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX29_4" }, "GTX_COMMON.GTXE2_IMUX30_2->GTXE2_COMMON_DRPADDR6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPADDR6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX30_2" }, "GTX_COMMON.GTXE2_IMUX30_3->GTXE2_COMMON_QPLLREFCLKSEL1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLREFCLKSEL1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX30_3" }, "GTX_COMMON.GTXE2_IMUX30_4->GTXE2_COMMON_BGRCALOVRD1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_BGRCALOVRD1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX30_4" }, "GTX_COMMON.GTXE2_IMUX30_5->GTXE2_COMMON_BGBYPASSB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_BGBYPASSB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX30_5" }, "GTX_COMMON.GTXE2_IMUX31_2->GTXE2_COMMON_DRPADDR7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_DRPADDR7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX31_2" }, "GTX_COMMON.GTXE2_IMUX31_3->GTXE2_COMMON_QPLLREFCLKSEL0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_QPLLREFCLKSEL0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX31_3" }, "GTX_COMMON.GTXE2_IMUX31_4->GTXE2_COMMON_BGRCALOVRD0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "GTXE2_COMMON_BGRCALOVRD0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "GTXE2_IMUX31_4" }, "GTX_COMMON.IBUFDS_GTE2_0_I->IBUFDS_GTE2_0_I_SEG": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTE2_0_I_SEG", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTE2_0_I" }, "GTX_COMMON.IBUFDS_GTE2_0_IB->IBUFDS_GTE2_0_IB_SEG": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IBUFDS_GTE2_0_IB_SEG", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IBUFDS_GTE2_0_IB" }, "GTX_COMMON.IBUFDS_GTE2_0_MGTCLKOUT->>GTXE2_COMMON_MGT_CLK4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": 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