{ "pips": { "HCLK_CMT_L.HCLK_CMT_BUFMRCE_O0->>HCLK_CMT_BUFMR_PHASEREF0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_PHASEREF0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_BUFMRCE_O0" }, "HCLK_CMT_L.HCLK_CMT_BUFMRCE_O1->>HCLK_CMT_BUFMR_PHASEREF1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_PHASEREF1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_BUFMRCE_O1" }, "HCLK_CMT_L.HCLK_CMT_BUFMR_CE0->HCLK_CMT_BUFMRCE_CEINP0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "HCLK_CMT_BUFMRCE_CEINP0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "HCLK_CMT_BUFMR_CE0" }, "HCLK_CMT_L.HCLK_CMT_BUFMR_CE1->HCLK_CMT_BUFMRCE_CEINP1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "HCLK_CMT_BUFMRCE_CEINP1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "HCLK_CMT_BUFMR_CE1" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.178", "0.205", "0.443", "0.511" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.178", "0.205", "0.443", "0.511" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.252", "0.269", "0.453", "0.485" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.252", "0.269", "0.453", "0.485" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.252", "0.269", "0.453", "0.485" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.252", "0.269", "0.453", "0.485" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO1" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.252", "0.269", "0.453", "0.485" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.252", "0.269", "0.453", "0.485" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO2" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.178", "0.205", "0.443", "0.511" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.178", "0.205", "0.443", "0.511" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.327", "0.353", "0.625", "0.676" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.495", "0.902", "0.985" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.252", "0.269", "0.453", "0.485" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.252", "0.269", "0.453", "0.485" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CCIO3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.453", "0.496", "0.917", "1.002" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CCIO3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.104", "0.117", "0.238", "0.266" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK1" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.199", "0.225", "0.443", "0.493" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.205", "0.232", "0.463", "0.516" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.201", "0.228", "0.391", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.201", "0.228", "0.391", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLKINT_0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.201", "0.228", "0.391", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.201", "0.228", "0.391", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLKINT_0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_MUX_OUT_FREQ_REF0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.163", "0.184", "0.406", "0.452" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.163", "0.184", "0.406", "0.452" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLKINT_0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.201", "0.228", "0.391", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.201", "0.228", "0.391", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLKINT_1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.201", "0.228", "0.391", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.201", "0.228", "0.391", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLKINT_1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.163", "0.184", "0.406", "0.452" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.163", "0.184", "0.406", "0.452" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLKINT_1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.163", "0.184", "0.406", "0.452" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.163", "0.184", "0.406", "0.452" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLKINT_2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.163", "0.184", "0.406", "0.452" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.163", "0.184", "0.406", "0.452" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLKINT_3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.172", "0.356", "0.397" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.099", "0.112", "0.230", "0.257" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.192", "0.217", "0.432", "0.482" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.203", "0.230", "0.460", "0.513" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM1->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM10->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.229", "0.259", "0.530", "0.591" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.247", "0.279", "0.528", "0.589" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.365", "0.412", "0.744", "0.830" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3" }, "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF0->>HCLK_CMT_FREQ_REF_NS0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_FREQ_REF_NS0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0" }, "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF1->>HCLK_CMT_FREQ_REF_NS1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_FREQ_REF_NS1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1" }, "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF2->>HCLK_CMT_FREQ_REF_NS2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_FREQ_REF_NS2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2" }, "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF3->>HCLK_CMT_FREQ_REF_NS3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_CMT_FREQ_REF_NS3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.180", "0.203", "0.383", "0.427" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" } }, "sites": [ { "name": "X0Y0", "prefix": "BUFMRCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_CMT_BUFMRCE_CEINP0" }, "I": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_CMT_BUFMR_INP0" }, "O": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "HCLK_CMT_BUFMRCE_O0" } }, "type": "BUFMRCE", "x_coord": 0, "y_coord": 0 }, { "name": "X0Y1", "prefix": "BUFMRCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_CMT_BUFMRCE_CEINP1" }, "I": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_CMT_BUFMR_INP1" }, "O": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "HCLK_CMT_BUFMRCE_O1" } }, "type": "BUFMRCE", "x_coord": 0, "y_coord": 1 } ], "tile_type": "HCLK_CMT_L", "wires": { "HCLK_CMT_BUFMRCE_CEINP0": null, "HCLK_CMT_BUFMRCE_CEINP1": null, "HCLK_CMT_BUFMRCE_O0": null, "HCLK_CMT_BUFMRCE_O1": null, "HCLK_CMT_BUFMR_CE0": null, "HCLK_CMT_BUFMR_CE1": null, "HCLK_CMT_BUFMR_INP0": null, "HCLK_CMT_BUFMR_INP1": null, "HCLK_CMT_BUFMR_PHASEREF0": null, "HCLK_CMT_BUFMR_PHASEREF1": null, "HCLK_CMT_CCIO0": null, "HCLK_CMT_CCIO1": null, "HCLK_CMT_CCIO2": null, "HCLK_CMT_CCIO3": null, "HCLK_CMT_CK_BUFHCLK0": null, "HCLK_CMT_CK_BUFHCLK1": null, "HCLK_CMT_CK_BUFHCLK2": null, "HCLK_CMT_CK_BUFHCLK3": null, "HCLK_CMT_CK_BUFHCLK4": null, "HCLK_CMT_CK_BUFHCLK5": null, "HCLK_CMT_CK_BUFHCLK6": null, "HCLK_CMT_CK_BUFHCLK7": null, "HCLK_CMT_CK_BUFHCLK8": null, "HCLK_CMT_CK_BUFHCLK9": null, "HCLK_CMT_CK_BUFHCLK10": null, "HCLK_CMT_CK_BUFHCLK11": null, "HCLK_CMT_CK_BUFRCLK0": null, "HCLK_CMT_CK_BUFRCLK1": null, "HCLK_CMT_CK_BUFRCLK2": null, "HCLK_CMT_CK_BUFRCLK3": null, "HCLK_CMT_CK_IN0": null, "HCLK_CMT_CK_IN1": null, "HCLK_CMT_CK_IN2": null, "HCLK_CMT_CK_IN3": null, "HCLK_CMT_CK_IN4": null, "HCLK_CMT_CK_IN5": null, "HCLK_CMT_CK_IN6": null, "HCLK_CMT_CK_IN7": null, "HCLK_CMT_CK_IN8": null, "HCLK_CMT_CK_IN9": null, "HCLK_CMT_CK_IN10": null, "HCLK_CMT_CK_IN11": null, "HCLK_CMT_CK_IN12": null, "HCLK_CMT_CK_IN13": null, "HCLK_CMT_ECALIB0": null, "HCLK_CMT_ECALIB1": null, "HCLK_CMT_FREQ_PHASER_REFMUX_0": null, "HCLK_CMT_FREQ_PHASER_REFMUX_1": null, "HCLK_CMT_FREQ_PHASER_REFMUX_2": null, "HCLK_CMT_FREQ_REF_NS0": null, "HCLK_CMT_FREQ_REF_NS1": null, "HCLK_CMT_FREQ_REF_NS2": null, "HCLK_CMT_FREQ_REF_NS3": null, "HCLK_CMT_IBURST0": null, "HCLK_CMT_IBURST1": null, "HCLK_CMT_IBURSTPENDING0": null, "HCLK_CMT_IBURSTPENDING1": null, "HCLK_CMT_MUX_CLKINT_0": null, "HCLK_CMT_MUX_CLKINT_1": null, "HCLK_CMT_MUX_CLKINT_2": null, "HCLK_CMT_MUX_CLKINT_3": null, "HCLK_CMT_MUX_CLK_0": null, "HCLK_CMT_MUX_CLK_1": null, "HCLK_CMT_MUX_CLK_2": null, "HCLK_CMT_MUX_CLK_3": null, "HCLK_CMT_MUX_CLK_4": null, "HCLK_CMT_MUX_CLK_5": null, "HCLK_CMT_MUX_CLK_6": null, "HCLK_CMT_MUX_CLK_7": null, "HCLK_CMT_MUX_CLK_8": null, "HCLK_CMT_MUX_CLK_9": null, "HCLK_CMT_MUX_CLK_10": null, "HCLK_CMT_MUX_CLK_11": null, "HCLK_CMT_MUX_CLK_12": null, "HCLK_CMT_MUX_CLK_13": null, "HCLK_CMT_MUX_CLK_LEAF_DN0": null, "HCLK_CMT_MUX_CLK_LEAF_DN1": null, "HCLK_CMT_MUX_CLK_LEAF_UP0": null, "HCLK_CMT_MUX_CLK_LEAF_UP1": null, "HCLK_CMT_MUX_CLK_MMCM0": null, "HCLK_CMT_MUX_CLK_MMCM1": null, "HCLK_CMT_MUX_CLK_MMCM2": null, "HCLK_CMT_MUX_CLK_MMCM3": null, "HCLK_CMT_MUX_CLK_MMCM4": null, "HCLK_CMT_MUX_CLK_MMCM5": null, "HCLK_CMT_MUX_CLK_MMCM6": null, "HCLK_CMT_MUX_CLK_MMCM7": null, "HCLK_CMT_MUX_CLK_MMCM8": null, "HCLK_CMT_MUX_CLK_MMCM9": null, "HCLK_CMT_MUX_CLK_MMCM10": null, "HCLK_CMT_MUX_CLK_MMCM11": null, "HCLK_CMT_MUX_CLK_MMCM12": null, "HCLK_CMT_MUX_CLK_MMCM13": null, "HCLK_CMT_MUX_CLK_PLL0": null, "HCLK_CMT_MUX_CLK_PLL1": null, "HCLK_CMT_MUX_CLK_PLL2": null, "HCLK_CMT_MUX_CLK_PLL3": null, "HCLK_CMT_MUX_CLK_PLL4": null, "HCLK_CMT_MUX_CLK_PLL5": null, "HCLK_CMT_MUX_CLK_PLL6": null, "HCLK_CMT_MUX_CLK_PLL7": null, "HCLK_CMT_MUX_MMCM_CLKFBIN": null, "HCLK_CMT_MUX_MMCM_CLKIN1": null, "HCLK_CMT_MUX_MMCM_CLKIN2": null, "HCLK_CMT_MUX_MMCM_MUXED0": null, "HCLK_CMT_MUX_MMCM_MUXED1": null, "HCLK_CMT_MUX_MMCM_MUXED2": null, "HCLK_CMT_MUX_MMCM_MUXED3": null, "HCLK_CMT_MUX_OUT_FREQ_REF0": null, "HCLK_CMT_MUX_OUT_FREQ_REF1": null, "HCLK_CMT_MUX_OUT_FREQ_REF2": null, "HCLK_CMT_MUX_OUT_FREQ_REF3": null, "HCLK_CMT_MUX_PHSR_PERFCLK0": null, "HCLK_CMT_MUX_PHSR_PERFCLK1": null, "HCLK_CMT_MUX_PHSR_PERFCLK2": null, "HCLK_CMT_MUX_PHSR_PERFCLK3": null, "HCLK_CMT_MUX_PLLE2_CLKFBIN": null, "HCLK_CMT_MUX_PLLE2_CLKIN1": null, "HCLK_CMT_MUX_PLLE2_CLKIN2": null, "HCLK_CMT_OBURSTPENDING0": null, "HCLK_CMT_OBURSTPENDING1": null, "HCLK_CMT_PHASEREF_ABOVE0": null, "HCLK_CMT_PHASEREF_ABOVE1": null, "HCLK_CMT_PHASEREF_BELOW0": null, "HCLK_CMT_PHASEREF_BELOW1": null, "HCLK_CMT_PHASERIN_RCLK0": null, "HCLK_CMT_PHASERIN_RCLK1": null, "HCLK_CMT_PHASERIN_RCLK2": null, "HCLK_CMT_PHASERIN_RCLK3": null, "HCLK_CMT_PHY_CONTROL_IRANKA0": null, "HCLK_CMT_PHY_CONTROL_IRANKA1": null, "HCLK_CMT_PHY_CONTROL_IRANKB0": null, "HCLK_CMT_PHY_CONTROL_IRANKB1": null, "HCLK_CMT_PHY_SYNC_BB": null, "HCLK_CMT_PREF_BOUNCE0": null, "HCLK_CMT_PREF_BOUNCE1": null, "HCLK_CMT_PREF_BOUNCE2": null, "HCLK_CMT_PREF_BOUNCE3": null, "HCLK_CMT_PREF_CLKOUT": null, "HCLK_CMT_PREF_TMUXOUT": null } }