{ "pips": { "HCLK_IOI.HCLK_IOI_BUFIO_O0->>HCLK_IOI_IOCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_IOCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_BUFIO_O0" }, "HCLK_IOI.HCLK_IOI_BUFIO_O1->>HCLK_IOI_IOCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_IOCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_BUFIO_O1" }, "HCLK_IOI.HCLK_IOI_BUFIO_O2->>HCLK_IOI_IOCLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_IOCLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_BUFIO_O2" }, "HCLK_IOI.HCLK_IOI_BUFIO_O3->>HCLK_IOI_IOCLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_IOCLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_BUFIO_O3" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK0->>HCLK_IOI_CK_IGCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_CK_IGCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_CK_BUFHCLK0" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK1->>HCLK_IOI_CK_IGCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_CK_IGCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_CK_BUFHCLK1" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK2->>HCLK_IOI_CK_IGCLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_CK_IGCLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_CK_BUFHCLK2" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK3->>HCLK_IOI_CK_IGCLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_CK_IGCLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_CK_BUFHCLK3" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK4->>HCLK_IOI_CK_IGCLK4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_CK_IGCLK4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_CK_BUFHCLK4" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK5->>HCLK_IOI_CK_IGCLK5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_CK_IGCLK5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_CK_BUFHCLK5" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK6->>HCLK_IOI_CK_IGCLK6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_CK_IGCLK6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_CK_BUFHCLK6" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK7->>HCLK_IOI_CK_IGCLK7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_CK_IGCLK7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_CK_BUFHCLK7" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK8->>HCLK_IOI_CK_IGCLK8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_CK_IGCLK8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_CK_BUFHCLK8" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK9->>HCLK_IOI_CK_IGCLK9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_CK_IGCLK9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_CK_BUFHCLK9" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK10->>HCLK_IOI_CK_IGCLK10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_CK_IGCLK10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_CK_BUFHCLK10" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK11->>HCLK_IOI_CK_IGCLK11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_CK_IGCLK11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.141", "0.151", "0.230", "0.258" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_CK_BUFHCLK11" }, "HCLK_IOI.HCLK_IOI_CK_BUFRCLK0->>HCLK_IOI_RCLK2IO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.161", "0.185", "0.294", "0.318" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_RCLK2IO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.161", "0.185", "0.294", "0.318" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_BUFRCLK0" }, "HCLK_IOI.HCLK_IOI_CK_BUFRCLK1->>HCLK_IOI_RCLK2IO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.161", "0.185", "0.294", "0.318" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_RCLK2IO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.161", "0.185", "0.294", "0.318" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_BUFRCLK1" }, "HCLK_IOI.HCLK_IOI_CK_BUFRCLK2->>HCLK_IOI_RCLK2IO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.161", "0.185", "0.294", "0.318" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_RCLK2IO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.161", "0.185", "0.294", "0.318" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_BUFRCLK2" }, "HCLK_IOI.HCLK_IOI_CK_BUFRCLK3->>HCLK_IOI_RCLK2IO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.161", "0.185", "0.294", "0.318" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_RCLK2IO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.161", "0.185", "0.294", "0.318" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_BUFRCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_I2IOCLK_BOT0->>HCLK_IOI_IO_PLL_CLK2_DMUX": { "can_invert": "0", "dst_to_src": { "delay": [ "0.103", "0.119", "0.155", "0.203" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.103", "0.119", "0.155", "0.203" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_I2IOCLK_BOT0" }, "HCLK_IOI.HCLK_IOI_I2IOCLK_BOT1->>HCLK_IOI_IO_PLL_CLK3_DMUX": { "can_invert": "0", "dst_to_src": { "delay": [ "0.103", "0.119", "0.155", "0.203" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.103", "0.119", "0.155", "0.203" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_I2IOCLK_BOT1" }, "HCLK_IOI.HCLK_IOI_I2IOCLK_TOP0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { "can_invert": "0", "dst_to_src": { "delay": [ "0.103", "0.119", "0.155", "0.203" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.103", "0.119", "0.155", "0.203" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_I2IOCLK_TOP0" }, "HCLK_IOI.HCLK_IOI_I2IOCLK_TOP1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { "can_invert": "0", "dst_to_src": { "delay": [ "0.103", "0.119", "0.155", "0.203" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.103", "0.119", "0.155", "0.203" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_I2IOCLK_TOP1" }, "HCLK_IOI.HCLK_IOI_IOCLK_PLL0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_IOCLK_PLL0" }, "HCLK_IOI.HCLK_IOI_IOCLK_PLL1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_IOCLK_PLL1" }, "HCLK_IOI.HCLK_IOI_IOCLK_PLL2->>HCLK_IOI_IO_PLL_CLK2_DMUX": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_IOCLK_PLL2" }, "HCLK_IOI.HCLK_IOI_IOCLK_PLL3->>HCLK_IOI_IO_PLL_CLK3_DMUX": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_IOCLK_PLL3" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_IO_PLL_CLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.034", "0.040", "0.047", "0.055" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_IO_PLL_CLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.034", "0.040", "0.047", "0.055" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_RCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.063", "0.073", "0.112", "0.129" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.063", "0.073", "0.112", "0.129" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_IO_PLL_CLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.034", "0.040", "0.047", "0.055" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_IO_PLL_CLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.034", "0.040", "0.047", "0.055" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_RCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.063", "0.073", "0.112", "0.129" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.063", "0.073", "0.112", "0.129" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_IO_PLL_CLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.034", "0.040", "0.047", "0.055" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_IO_PLL_CLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.034", "0.040", "0.047", "0.055" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_RCLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.063", "0.073", "0.112", "0.129" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.063", "0.073", "0.112", "0.129" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_IO_PLL_CLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.034", "0.040", "0.047", "0.055" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_IO_PLL_CLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.034", "0.040", "0.047", "0.055" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_RCLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.063", "0.073", "0.112", "0.129" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.063", "0.073", "0.112", "0.129" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT0->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT0" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT1->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT1" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT2->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT2" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT3->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT3" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT4->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT4" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT5->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT5" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP0->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP0" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP1->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP1" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP2->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP2" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP3->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP3" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP4->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP4" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP5->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP5" }, "HCLK_IOI.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK2" }, "HCLK_IOI.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK2" }, "HCLK_IOI.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK2" }, "HCLK_IOI.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK2" }, "HCLK_IOI.HCLK_IOI_RCLK2RCLK0->>HCLK_IOI_CK_BUFRCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_CK_BUFRCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_RCLK2RCLK0" }, "HCLK_IOI.HCLK_IOI_RCLK2RCLK1->>HCLK_IOI_CK_BUFRCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_CK_BUFRCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_RCLK2RCLK1" }, "HCLK_IOI.HCLK_IOI_RCLK2RCLK2->>HCLK_IOI_CK_BUFRCLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_CK_BUFRCLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_RCLK2RCLK2" }, "HCLK_IOI.HCLK_IOI_RCLK2RCLK3->>HCLK_IOI_CK_BUFRCLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_IOI_CK_BUFRCLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "HCLK_IOI_RCLK2RCLK3" }, "HCLK_IOI.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK3" }, "HCLK_IOI.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK3" }, "HCLK_IOI.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK3" }, "HCLK_IOI.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK3" }, "HCLK_IOI.HCLK_IOI_RCLK_BEFORE_DIV0->>HCLK_IOI_RCLK_OUT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.090", "0.093", "0.289", "0.314" ], "in_cap": null, "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_OUT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.090", "0.093", "0.289", "0.314" ], "in_cap": null, "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV0" }, "HCLK_IOI.HCLK_IOI_RCLK_BEFORE_DIV1->>HCLK_IOI_RCLK_OUT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.090", "0.093", "0.289", "0.314" ], "in_cap": null, "res": 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"can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK_IMUX0" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK_IMUX0" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": 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"0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI.HCLK_IOI_RCLK_OUT0->>HCLK_IOI_RCLK2RCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK2RCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK_OUT0" }, "HCLK_IOI.HCLK_IOI_RCLK_OUT1->>HCLK_IOI_RCLK2RCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK2RCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK_OUT1" }, "HCLK_IOI.HCLK_IOI_RCLK_OUT2->>HCLK_IOI_RCLK2RCLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK2RCLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK_OUT2" }, "HCLK_IOI.HCLK_IOI_RCLK_OUT3->>HCLK_IOI_RCLK2RCLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_IOI_RCLK2RCLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_IOI_RCLK_OUT3" }, "HCLK_IOI.HCLK_RCLK_DIV_CE0->HCLK_IOI_BUFR0_CE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "HCLK_IOI_BUFR0_CE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "HCLK_RCLK_DIV_CE0" }, "HCLK_IOI.HCLK_RCLK_DIV_CE1->HCLK_IOI_BUFR1_CE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "HCLK_IOI_BUFR1_CE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "HCLK_RCLK_DIV_CE1" }, "HCLK_IOI.HCLK_RCLK_DIV_CE2->HCLK_IOI_BUFR2_CE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "HCLK_IOI_BUFR2_CE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "HCLK_RCLK_DIV_CE2" }, "HCLK_IOI.HCLK_RCLK_DIV_CE3->HCLK_IOI_BUFR3_CE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "HCLK_IOI_BUFR3_CE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "HCLK_RCLK_DIV_CE3" }, "HCLK_IOI.HCLK_RCLK_DIV_CLR0->HCLK_IOI_BUFR0_CLR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "HCLK_IOI_BUFR0_CLR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "HCLK_RCLK_DIV_CLR0" }, "HCLK_IOI.HCLK_RCLK_DIV_CLR1->HCLK_IOI_BUFR1_CLR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "HCLK_IOI_BUFR1_CLR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "HCLK_RCLK_DIV_CLR1" }, "HCLK_IOI.HCLK_RCLK_DIV_CLR2->HCLK_IOI_BUFR2_CLR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "HCLK_IOI_BUFR2_CLR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "HCLK_RCLK_DIV_CLR2" }, "HCLK_IOI.HCLK_RCLK_DIV_CLR3->HCLK_IOI_BUFR3_CLR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "HCLK_IOI_BUFR3_CLR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "HCLK_RCLK_DIV_CLR3" } }, "sites": [ { "name": "X0Y0", "prefix": "BUFIO", "site_pins": { "I": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_IO_PLL_CLK2" }, "O": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "HCLK_IOI_BUFIO_O2" } }, "type": "BUFIO", "x_coord": 0, "y_coord": 0 }, { "name": "X0Y0", "prefix": "BUFR", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_BUFR2_CE" }, "CLR": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_BUFR2_CLR" }, "I": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_RCLK_BEFORE_DIV2" }, "O": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "687.5", "wire": "HCLK_IOI_RCLK_OUT2" } }, "type": "BUFR", "x_coord": 0, "y_coord": 0 }, { "name": "X0Y0", "prefix": "IDELAYCTRL", "site_pins": { "DNPULSEOUT": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "HCLK_IOI_IDELAYCTRL_DNPULSEOUT" }, "OUTN1": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "HCLK_IOI_IDELAYCTRL_OUTN1" }, "OUTN65": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "HCLK_IOI_IDELAYCTRL_OUTN65" }, "RDY": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "687.5", "wire": "HCLK_IOI_IDELAYCTRL_RDY" }, "REFCLK": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_IDELAYCTRL_REFCLK" }, "RST": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_IDELAYCTRL_RST" }, "UPPULSEOUT": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "HCLK_IOI_IDELAYCTRL_UPPULSEOUT" } }, "type": "IDELAYCTRL", "x_coord": 0, "y_coord": 0 }, { "name": "X0Y1", "prefix": "BUFIO", "site_pins": { "I": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_IO_PLL_CLK3" }, "O": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "HCLK_IOI_BUFIO_O3" } }, "type": "BUFIO", "x_coord": 0, "y_coord": 1 }, { "name": "X0Y1", "prefix": "BUFR", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_BUFR3_CE" }, "CLR": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_BUFR3_CLR" }, "I": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_RCLK_BEFORE_DIV3" }, "O": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "687.5", "wire": "HCLK_IOI_RCLK_OUT3" } }, "type": "BUFR", "x_coord": 0, "y_coord": 1 }, { "name": "X0Y2", "prefix": "BUFIO", "site_pins": { "I": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_IO_PLL_CLK0" }, "O": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "HCLK_IOI_BUFIO_O0" } }, "type": "BUFIO", "x_coord": 0, "y_coord": 2 }, { "name": "X0Y2", "prefix": "BUFR", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_BUFR0_CE" }, "CLR": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_BUFR0_CLR" }, "I": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_RCLK_BEFORE_DIV0" }, "O": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "687.5", "wire": "HCLK_IOI_RCLK_OUT0" } }, "type": "BUFR", "x_coord": 0, "y_coord": 2 }, { "name": "X0Y3", "prefix": "BUFIO", "site_pins": { "I": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_IO_PLL_CLK1" }, "O": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "HCLK_IOI_BUFIO_O1" } }, "type": "BUFIO", "x_coord": 0, "y_coord": 3 }, { "name": "X0Y3", "prefix": "BUFR", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_BUFR1_CE" }, "CLR": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_BUFR1_CLR" }, "I": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "HCLK_IOI_RCLK_BEFORE_DIV1" }, "O": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "687.5", "wire": "HCLK_IOI_RCLK_OUT1" } }, "type": "BUFR", "x_coord": 0, "y_coord": 3 } ], "tile_type": "HCLK_IOI", "wires": { "HCLK_DCI_DCIADDRESS0": null, "HCLK_DCI_DCIADDRESS1": null, "HCLK_DCI_DCIADDRESS2": null, "HCLK_DCI_DCIDATA": null, "HCLK_DCI_DCIIOUPDATE": null, "HCLK_DCI_DCIREFIOUPDATE": null, "HCLK_DCI_DCISCLK": null, "HCLK_IOI_BUFIO_O0": null, "HCLK_IOI_BUFIO_O1": null, "HCLK_IOI_BUFIO_O2": null, "HCLK_IOI_BUFIO_O3": null, "HCLK_IOI_BUFR0_CE": null, "HCLK_IOI_BUFR0_CLR": null, "HCLK_IOI_BUFR1_CE": null, "HCLK_IOI_BUFR1_CLR": null, "HCLK_IOI_BUFR2_CE": null, "HCLK_IOI_BUFR2_CLR": null, "HCLK_IOI_BUFR3_CE": null, "HCLK_IOI_BUFR3_CLR": null, "HCLK_IOI_CK_BUFHCLK0": null, "HCLK_IOI_CK_BUFHCLK1": null, "HCLK_IOI_CK_BUFHCLK2": null, "HCLK_IOI_CK_BUFHCLK3": null, "HCLK_IOI_CK_BUFHCLK4": null, "HCLK_IOI_CK_BUFHCLK5": null, "HCLK_IOI_CK_BUFHCLK6": null, "HCLK_IOI_CK_BUFHCLK7": null, "HCLK_IOI_CK_BUFHCLK8": null, "HCLK_IOI_CK_BUFHCLK9": null, "HCLK_IOI_CK_BUFHCLK10": null, "HCLK_IOI_CK_BUFHCLK11": null, "HCLK_IOI_CK_BUFRCLK0": null, "HCLK_IOI_CK_BUFRCLK1": null, "HCLK_IOI_CK_BUFRCLK2": null, "HCLK_IOI_CK_BUFRCLK3": null, "HCLK_IOI_CK_IGCLK0": null, "HCLK_IOI_CK_IGCLK1": null, "HCLK_IOI_CK_IGCLK2": null, "HCLK_IOI_CK_IGCLK3": null, "HCLK_IOI_CK_IGCLK4": null, "HCLK_IOI_CK_IGCLK5": null, "HCLK_IOI_CK_IGCLK6": null, "HCLK_IOI_CK_IGCLK7": null, "HCLK_IOI_CK_IGCLK8": null, "HCLK_IOI_CK_IGCLK9": null, "HCLK_IOI_CK_IGCLK10": null, "HCLK_IOI_CK_IGCLK11": null, "HCLK_IOI_CK_IN0": null, "HCLK_IOI_CK_IN1": null, "HCLK_IOI_CK_IN2": null, "HCLK_IOI_CK_IN3": null, "HCLK_IOI_CK_IN4": null, "HCLK_IOI_CK_IN5": null, "HCLK_IOI_CK_IN6": null, "HCLK_IOI_CK_IN7": null, "HCLK_IOI_CK_IN8": null, "HCLK_IOI_CK_IN9": null, "HCLK_IOI_CK_IN10": null, "HCLK_IOI_CK_IN11": null, "HCLK_IOI_CK_IN12": null, "HCLK_IOI_CK_IN13": null, "HCLK_IOI_DCI_DCIDONE": null, "HCLK_IOI_DCI_TSTCLK": null, "HCLK_IOI_DCI_TSTHLN": null, "HCLK_IOI_DCI_TSTHLP": null, "HCLK_IOI_DCI_TSTRST": null, "HCLK_IOI_I2IOCLK_BOT0": null, "HCLK_IOI_I2IOCLK_BOT1": null, "HCLK_IOI_I2IOCLK_TOP0": null, "HCLK_IOI_I2IOCLK_TOP1": null, "HCLK_IOI_IDELAYCTRL_DNPULSEOUT": null, "HCLK_IOI_IDELAYCTRL_OUTN1": null, "HCLK_IOI_IDELAYCTRL_OUTN65": null, "HCLK_IOI_IDELAYCTRL_RDY": null, "HCLK_IOI_IDELAYCTRL_REFCLK": null, "HCLK_IOI_IDELAYCTRL_RST": null, "HCLK_IOI_IDELAYCTRL_UPPULSEOUT": null, "HCLK_IOI_INT_DCI_EN": null, "HCLK_IOI_IOCLK0": null, "HCLK_IOI_IOCLK1": null, "HCLK_IOI_IOCLK2": null, "HCLK_IOI_IOCLK3": null, "HCLK_IOI_IOCLK_PLL0": null, "HCLK_IOI_IOCLK_PLL1": null, "HCLK_IOI_IOCLK_PLL2": null, "HCLK_IOI_IOCLK_PLL3": null, "HCLK_IOI_IO_PLL_CLK0": null, "HCLK_IOI_IO_PLL_CLK0_DMUX": null, "HCLK_IOI_IO_PLL_CLK1": null, "HCLK_IOI_IO_PLL_CLK1_DMUX": null, "HCLK_IOI_IO_PLL_CLK2": null, "HCLK_IOI_IO_PLL_CLK2_DMUX": null, "HCLK_IOI_IO_PLL_CLK3": null, "HCLK_IOI_IO_PLL_CLK3_DMUX": null, "HCLK_IOI_LEAF_GCLK_BOT0": null, "HCLK_IOI_LEAF_GCLK_BOT1": null, "HCLK_IOI_LEAF_GCLK_BOT2": null, "HCLK_IOI_LEAF_GCLK_BOT3": null, "HCLK_IOI_LEAF_GCLK_BOT4": null, "HCLK_IOI_LEAF_GCLK_BOT5": null, "HCLK_IOI_LEAF_GCLK_TOP0": null, "HCLK_IOI_LEAF_GCLK_TOP1": null, "HCLK_IOI_LEAF_GCLK_TOP2": null, "HCLK_IOI_LEAF_GCLK_TOP3": null, "HCLK_IOI_LEAF_GCLK_TOP4": null, "HCLK_IOI_LEAF_GCLK_TOP5": null, "HCLK_IOI_RCLK0": null, "HCLK_IOI_RCLK1": null, "HCLK_IOI_RCLK2": null, "HCLK_IOI_RCLK2IO0": null, "HCLK_IOI_RCLK2IO1": null, "HCLK_IOI_RCLK2IO2": null, "HCLK_IOI_RCLK2IO3": null, "HCLK_IOI_RCLK2RCLK0": null, "HCLK_IOI_RCLK2RCLK1": null, "HCLK_IOI_RCLK2RCLK2": null, "HCLK_IOI_RCLK2RCLK3": null, "HCLK_IOI_RCLK3": null, "HCLK_IOI_RCLK_BEFORE_DIV0": null, "HCLK_IOI_RCLK_BEFORE_DIV1": null, "HCLK_IOI_RCLK_BEFORE_DIV2": null, "HCLK_IOI_RCLK_BEFORE_DIV3": null, "HCLK_IOI_RCLK_IMUX0": null, "HCLK_IOI_RCLK_IMUX1": null, "HCLK_IOI_RCLK_IMUX2": null, "HCLK_IOI_RCLK_IMUX3": null, "HCLK_IOI_RCLK_OUT0": null, "HCLK_IOI_RCLK_OUT1": null, "HCLK_IOI_RCLK_OUT2": null, "HCLK_IOI_RCLK_OUT3": null, "HCLK_RCLK_DIV_CE0": null, "HCLK_RCLK_DIV_CE1": null, "HCLK_RCLK_DIV_CE2": null, "HCLK_RCLK_DIV_CE3": null, "HCLK_RCLK_DIV_CLR0": null, "HCLK_RCLK_DIV_CLR1": null, "HCLK_RCLK_DIV_CLR2": null, "HCLK_RCLK_DIV_CLR3": null } }