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"res": null }, "src_wire": "HCLK_CK_BUFHCLK5" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CK_BUFHCLK5" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CK_BUFHCLK5" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.082", "0.084", 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0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CK_BUFHCLK6" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_CK_INOUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "HCLK_CK_INOUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "HCLK_CK_BUFHCLK7" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CK_BUFHCLK7" }, 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"dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CK_BUFHCLK7" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CK_BUFHCLK7" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK7->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_LEAF_CLK_B_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CK_BUFHCLK7" }, "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CK_OUTIN_R0" }, "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_LEAF_CLK_B_TOP1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CK_OUTIN_R0" }, "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R0->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.082", "0.084", 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0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CK_OUTIN_R1" }, "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CK_OUTIN_R1" }, "HCLK_R_BOT_UTURN.HCLK_CK_OUTIN_R1->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "dst_wire": "HCLK_LEAF_CLK_B_TOP5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.082", "0.084", "0.153", "0.155" ], "in_cap": null, "res": null }, "src_wire": "HCLK_CK_OUTIN_R1" }, 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