{ "pips": { "LIOI3_SING.IOI_BYP6_0->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP6_0" }, "LIOI3_SING.IOI_BYP7_0->LIOI3_IDELAY0_IFDLY2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI3_IDELAY0_IFDLY2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_BYP7_0" }, "LIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CLK0_0" }, "LIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CLK0_0" }, "LIOI3_SING.IOI_CLK1_0->IOI_IDELAY0_C": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CLK1_0" }, "LIOI3_SING.IOI_CTRL0_0->IOI_OLOGIC0_SR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CTRL0_0" }, "LIOI3_SING.IOI_CTRL1_0->IOI_ILOGIC0_SR": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_CTRL1_0" }, "LIOI3_SING.IOI_FAN4_0->LIOI3_IDELAY0_IFDLY0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI3_IDELAY0_IFDLY0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_FAN4_0" }, "LIOI3_SING.IOI_FAN5_0->LIOI3_IDELAY0_IFDLY1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI3_IDELAY0_IFDLY1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_FAN5_0" }, "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "LIOI3_SING.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.033", "0.060", "0.039", "0.089" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.033", "0.060", "0.039", "0.089" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_ILOGIC0_O" }, "LIOI3_SING.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q1" }, "LIOI3_SING.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q2" }, "LIOI3_SING.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q3" }, "LIOI3_SING.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q4" }, "LIOI3_SING.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q5" }, "LIOI3_SING.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q6" }, "LIOI3_SING.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q7" }, "LIOI3_SING.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_ILOGIC0_Q8" }, "LIOI3_SING.IOI_IMUX0_0->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX0_0" }, "LIOI3_SING.IOI_IMUX1_0->IOI_OLOGIC0_TCE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX1_0" }, "LIOI3_SING.IOI_IMUX4_0->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX4_0" }, "LIOI3_SING.IOI_IMUX5_0->IOI_ILOGIC0_CE1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX5_0" }, "LIOI3_SING.IOI_IMUX6_0->LIOI_DCI_T_TERM0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI_DCI_T_TERM0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX6_0" }, "LIOI3_SING.IOI_IMUX7_0->IOI_OLOGIC0_T2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX7_0" }, "LIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_SING.IOI_IMUX8_0->IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_SING.IOI_IMUX8_0->LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_SING.IOI_IMUX9_0->LIOI_IBUF_DISABLE0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "LIOI_IBUF_DISABLE0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX9_0" }, "LIOI3_SING.IOI_IMUX10_0->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX10_0" }, "LIOI3_SING.IOI_IMUX12_0->IOI_IDELAY0_REGRST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX12_0" }, "LIOI3_SING.IOI_IMUX13_0->IOI_OLOGIC0_T3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX13_0" }, "LIOI3_SING.IOI_IMUX14_0->IOI_ILOGIC0_CE2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX14_0" }, "LIOI3_SING.IOI_IMUX15_0->IOI_OLOGIC0_T1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX15_0" }, "LIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX20_0" }, "LIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX20_0" }, "LIOI3_SING.IOI_IMUX21_0->IOI_OLOGIC0_T4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX21_0" }, "LIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX22_0" }, "LIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX22_0" }, "LIOI3_SING.IOI_IMUX25_0->IOI_IDELAY0_DATAIN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX25_0" }, "LIOI3_SING.IOI_IMUX26_0->IOI_IDELAY0_INC": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX26_0" }, "LIOI3_SING.IOI_IMUX29_0->IOI_OLOGIC0_OCE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX29_0" }, "LIOI3_SING.IOI_IMUX30_0->IOI_IDELAY0_LD": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX30_0" }, "LIOI3_SING.IOI_IMUX31_0->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX31_0" }, "LIOI3_SING.IOI_IMUX31_0->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.134", "0.154", "0.247", "0.284" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_IMUX31_0" }, "LIOI3_SING.IOI_IMUX32_0->IOI_IDELAY0_CE": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX32_0" }, "LIOI3_SING.IOI_IMUX33_0->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX33_0" }, "LIOI3_SING.IOI_IMUX34_0->IOI_OLOGIC0_D1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX34_0" }, "LIOI3_SING.IOI_IMUX35_0->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX35_0" }, "LIOI3_SING.IOI_IMUX36_0->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX36_0" }, "LIOI3_SING.IOI_IMUX37_0->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX37_0" }, "LIOI3_SING.IOI_IMUX38_0->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX38_0" }, "LIOI3_SING.IOI_IMUX39_0->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX39_0" }, "LIOI3_SING.IOI_IMUX40_0->IOI_OLOGIC0_D2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX40_0" }, "LIOI3_SING.IOI_IMUX41_0->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX41_0" }, "LIOI3_SING.IOI_IMUX42_0->IOI_OLOGIC0_D4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX42_0" }, "LIOI3_SING.IOI_IMUX43_0->IOI_OLOGIC0_D5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX43_0" }, "LIOI3_SING.IOI_IMUX44_0->IOI_OLOGIC0_D3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX44_0" }, "LIOI3_SING.IOI_IMUX45_0->IOI_OLOGIC0_D6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX45_0" }, "LIOI3_SING.IOI_IMUX46_0->IOI_OLOGIC0_D7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX46_0" }, "LIOI3_SING.IOI_IMUX47_0->IOI_OLOGIC0_D8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_IMUX47_0" }, "LIOI3_SING.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLKM_0" }, "LIOI3_SING.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLKM_0" }, "LIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLK_0" }, "LIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLK_0" }, "LIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLK_0" }, "LIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OCLK_0" }, "LIOI3_SING.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.128", "0.277", "0.731", "0.801" ], "in_cap": null, "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_OFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.128", "0.277", "0.731", "0.801" ], "in_cap": null, "res": "0.0" }, "src_wire": "IOI_OLOGIC0_D1" }, "LIOI3_SING.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { "can_invert": "0", "dst_to_src": { "delay": [ "0.128", "0.277", "0.731", "0.801" ], "in_cap": null, "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_OQ", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.128", "0.277", "0.731", "0.801" ], "in_cap": null, "res": "0.0" }, "src_wire": "IOI_OLOGIC0_D1" }, "LIOI3_SING.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "IOI_LOGIC_OUTS5_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" }, "LIOI3_SING.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.381", "0.438", "0.699", "0.804" ], "in_cap": null, "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_TFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.381", "0.438", "0.699", "0.804" ], "in_cap": null, "res": "0.0" }, "src_wire": "IOI_OLOGIC0_T1" }, "LIOI3_SING.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { "can_invert": "0", "dst_to_src": { "delay": [ "0.381", "0.438", "0.699", "0.804" ], "in_cap": null, "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_TQ", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.381", "0.438", "0.699", "0.804" ], "in_cap": null, "res": "0.0" }, "src_wire": "IOI_OLOGIC0_T1" }, "LIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "LIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "LIOI3_SING.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", "dst_to_src": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.031", "0.035", "0.058", "0.066" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, 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"dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_IOCLK0" }, "LIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_IOCLK0" }, "LIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_IOCLK0" }, "LIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_IOCLK1" }, "LIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_IOCLK1" }, "LIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": 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}, "LIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_IOCLK2" }, "LIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_IOCLK2" }, "LIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_IOCLK2" }, "LIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_IOCLK3" }, "LIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_IOCLK3" }, "LIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_IOCLK3" }, "LIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_IOCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLKM_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLK_0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": 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"is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": 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}, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", "dst_to_src": { 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"LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "LIOI3_SING.IOI_SING_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", "dst_to_src": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.021", "0.022", "0.130", "0.162" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "LIOI3_SING.IOI_SING_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", 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