{ "pips": { "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED1->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED1" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED2->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED2" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED3->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED3" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED4->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED4" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED5->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED5" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED6->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED6" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED7->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED7" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED8->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED8" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED9->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED9" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED10->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED10" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED11->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED11" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED12->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED12" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED13->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED13" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED14->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED14" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED15->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED15" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED16->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED16" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED17->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED17" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED18->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED18" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED19->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED19" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED20->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED20" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED21->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED21" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED22->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED22" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED23->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED23" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED24->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED24" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED25->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED25" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED26->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED26" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED27->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED27" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED28->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED28" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED29->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED29" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED30->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED30" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED31->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.068", "0.075", "0.182", "0.191" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED31" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0->>CLK_BUFG_BUFGCTRL0_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL0_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL0_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_CK_GCLK0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL0_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_R_FBG_OUT0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL0_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0->>CLK_BUFG_BUFGCTRL1_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL1_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL1_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_CK_GCLK1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL1_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_R_FBG_OUT1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL1_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0->>CLK_BUFG_BUFGCTRL2_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL2_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL2_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_CK_GCLK2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL2_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_R_FBG_OUT2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL2_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0->>CLK_BUFG_BUFGCTRL3_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL3_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL3_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_CK_GCLK3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL3_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_R_FBG_OUT3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL3_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0->>CLK_BUFG_BUFGCTRL4_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL4_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL4_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_CK_GCLK4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL4_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_R_FBG_OUT4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL4_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0->>CLK_BUFG_BUFGCTRL5_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL5_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL5_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_CK_GCLK5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL5_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_R_FBG_OUT5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL5_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0->>CLK_BUFG_BUFGCTRL6_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL6_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL6_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_CK_GCLK6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL6_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_R_FBG_OUT6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL6_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0->>CLK_BUFG_BUFGCTRL7_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL7_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL7_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_CK_GCLK7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL7_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_R_FBG_OUT7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL7_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0->>CLK_BUFG_BUFGCTRL8_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL8_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL8_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_CK_GCLK8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL8_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_R_FBG_OUT8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL8_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0->>CLK_BUFG_BUFGCTRL9_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL9_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL9_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_CK_GCLK9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL9_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_R_FBG_OUT9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL9_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0->>CLK_BUFG_BUFGCTRL10_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL10_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL10_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_CK_GCLK10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL10_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_R_FBG_OUT10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL10_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0->>CLK_BUFG_BUFGCTRL11_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL11_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL11_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_CK_GCLK11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL11_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_R_FBG_OUT11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL11_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0->>CLK_BUFG_BUFGCTRL12_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL12_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL12_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_CK_GCLK12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL12_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_R_FBG_OUT12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL12_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0->>CLK_BUFG_BUFGCTRL13_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL13_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL13_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_CK_GCLK13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL13_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_R_FBG_OUT13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL13_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0->>CLK_BUFG_BUFGCTRL14_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL14_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL14_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_CK_GCLK14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL14_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_R_FBG_OUT14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL14_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0->>CLK_BUFG_BUFGCTRL15_O": { "can_invert": "0", "dst_to_src": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL15_O", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.026", "0.029", "0.091", "0.096" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL15_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_CK_GCLK15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_BUFG_CK_GCLK15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_BUFG_BUFGCTRL15_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_R_FBG_OUT15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_FBG_OUT15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_BUFGCTRL15_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_0->>CLK_BUFG_R_BUFGCTRL0_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX0_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_1->>CLK_BUFG_R_BUFGCTRL4_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX0_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_2->>CLK_BUFG_R_BUFGCTRL8_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX0_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_3->>CLK_BUFG_R_BUFGCTRL12_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX0_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_0->>CLK_BUFG_R_BUFGCTRL1_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX1_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_1->>CLK_BUFG_R_BUFGCTRL5_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX1_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_2->>CLK_BUFG_R_BUFGCTRL9_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX1_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_3->>CLK_BUFG_R_BUFGCTRL13_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX1_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_0->>CLK_BUFG_R_BUFGCTRL2_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX2_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_1->>CLK_BUFG_R_BUFGCTRL6_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX2_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_2->>CLK_BUFG_R_BUFGCTRL10_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX2_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_3->>CLK_BUFG_R_BUFGCTRL14_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX2_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_0->>CLK_BUFG_R_BUFGCTRL3_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX3_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_1->>CLK_BUFG_R_BUFGCTRL7_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX3_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_2->>CLK_BUFG_R_BUFGCTRL11_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX3_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_3->>CLK_BUFG_R_BUFGCTRL15_S1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX3_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_0->>CLK_BUFG_R_BUFGCTRL0_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX4_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_1->>CLK_BUFG_R_BUFGCTRL4_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX4_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_2->>CLK_BUFG_R_BUFGCTRL8_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX4_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_3->>CLK_BUFG_R_BUFGCTRL12_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX4_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_0->>CLK_BUFG_R_BUFGCTRL1_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX5_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_1->>CLK_BUFG_R_BUFGCTRL5_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX5_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_2->>CLK_BUFG_R_BUFGCTRL9_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX5_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_3->>CLK_BUFG_R_BUFGCTRL13_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX5_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_0->>CLK_BUFG_R_BUFGCTRL2_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX6_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_1->>CLK_BUFG_R_BUFGCTRL6_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX6_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_2->>CLK_BUFG_R_BUFGCTRL10_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX6_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_3->>CLK_BUFG_R_BUFGCTRL14_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX6_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_0->>CLK_BUFG_R_BUFGCTRL3_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX7_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_1->>CLK_BUFG_R_BUFGCTRL7_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX7_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_2->>CLK_BUFG_R_BUFGCTRL11_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX7_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_3->>CLK_BUFG_R_BUFGCTRL15_S0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX7_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX8_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX8_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX8_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX8_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX9_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX9_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX9_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX9_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX10_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX10_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX10_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX10_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX11_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX11_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX11_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX11_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX12_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX12_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX12_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX12_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX13_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX13_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX13_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX13_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX14_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX14_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX14_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX14_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX15_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX15_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX15_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX15_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_0->>CLK_BUFG_R_BUFGCTRL0_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX16_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_1->>CLK_BUFG_R_BUFGCTRL4_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX16_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_2->>CLK_BUFG_R_BUFGCTRL8_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX16_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_3->>CLK_BUFG_R_BUFGCTRL12_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX16_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_0->>CLK_BUFG_R_BUFGCTRL1_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX17_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_1->>CLK_BUFG_R_BUFGCTRL5_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX17_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_2->>CLK_BUFG_R_BUFGCTRL9_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX17_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_3->>CLK_BUFG_R_BUFGCTRL13_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX17_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_0->>CLK_BUFG_R_BUFGCTRL2_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX18_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_1->>CLK_BUFG_R_BUFGCTRL6_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX18_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_2->>CLK_BUFG_R_BUFGCTRL10_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX18_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_3->>CLK_BUFG_R_BUFGCTRL14_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX18_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_0->>CLK_BUFG_R_BUFGCTRL3_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX19_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_1->>CLK_BUFG_R_BUFGCTRL7_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX19_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_2->>CLK_BUFG_R_BUFGCTRL11_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX19_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_3->>CLK_BUFG_R_BUFGCTRL15_CE1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX19_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_0->>CLK_BUFG_R_BUFGCTRL0_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX20_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_1->>CLK_BUFG_R_BUFGCTRL4_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX20_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_2->>CLK_BUFG_R_BUFGCTRL8_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX20_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_3->>CLK_BUFG_R_BUFGCTRL12_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX20_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_0->>CLK_BUFG_R_BUFGCTRL1_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX21_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_1->>CLK_BUFG_R_BUFGCTRL5_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX21_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_2->>CLK_BUFG_R_BUFGCTRL9_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX21_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_3->>CLK_BUFG_R_BUFGCTRL13_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX21_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_0->>CLK_BUFG_R_BUFGCTRL2_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX22_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_1->>CLK_BUFG_R_BUFGCTRL6_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX22_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_2->>CLK_BUFG_R_BUFGCTRL10_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX22_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_3->>CLK_BUFG_R_BUFGCTRL14_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX22_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_0->>CLK_BUFG_R_BUFGCTRL3_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX23_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_1->>CLK_BUFG_R_BUFGCTRL7_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX23_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_2->>CLK_BUFG_R_BUFGCTRL11_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX23_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_3->>CLK_BUFG_R_BUFGCTRL15_CE0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.020", "0.022", "0.069", "0.072" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX23_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX24_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX24_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX24_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX24_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX24_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX24_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX24_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX24_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX25_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX25_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX25_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX25_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX25_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX25_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX25_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX25_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX26_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX26_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX26_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX26_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX26_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX26_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX26_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX26_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX27_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX27_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX27_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX27_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX27_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX27_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX27_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX27_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX28_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX28_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX28_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX28_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX28_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX28_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX28_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX28_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX29_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX29_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX29_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX29_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX29_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX29_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX29_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX29_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX30_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX30_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX30_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX30_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX30_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX30_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX30_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX30_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX31_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX31_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX31_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX31_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX31_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX31_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX31_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.064", "0.071", "0.217", "0.228" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_IMUX31_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.040", "0.044", "0.145", "0.152" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.040", "0.044", "0.145", "0.152" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.040", "0.044", "0.145", "0.152" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.040", "0.044", "0.145", "0.152" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.040", "0.044", "0.145", "0.152" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.040", "0.044", "0.145", "0.152" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.040", "0.044", "0.145", "0.152" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.040", "0.044", "0.145", "0.152" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.028", "0.031", "0.131", "0.138" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_BUFG_R_FBG_OUT15" } }, "sites": [ { "name": "X0Y0", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL0_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL0_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL0_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL0_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL0_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL0_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL0_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 0 }, { "name": "X0Y1", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL1_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL1_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL1_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL1_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL1_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL1_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL1_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 1 }, { "name": "X0Y2", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL2_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL2_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL2_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL2_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL2_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL2_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL2_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 2 }, { "name": "X0Y3", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL3_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL3_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL3_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL3_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL3_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL3_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL3_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 3 }, { "name": "X0Y4", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL4_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL4_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL4_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL4_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL4_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL4_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL4_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 4 }, { "name": "X0Y5", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL5_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL5_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL5_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL5_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL5_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL5_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL5_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 5 }, { "name": "X0Y6", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL6_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL6_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL6_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL6_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL6_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL6_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL6_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 6 }, { "name": "X0Y7", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL7_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL7_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL7_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL7_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL7_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL7_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL7_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 7 }, { "name": "X0Y8", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL8_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL8_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL8_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL8_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL8_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL8_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL8_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 8 }, { "name": "X0Y9", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL9_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL9_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL9_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL9_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL9_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL9_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL9_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 9 }, { "name": "X0Y10", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL10_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL10_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL10_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL10_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL10_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL10_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL10_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 10 }, { "name": "X0Y11", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL11_CE0" }, "CE1": { "cap": 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{ "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL12_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL12_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL12_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL12_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL12_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL12_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL12_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 12 }, { "name": "X0Y13", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL13_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL13_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL13_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL13_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL13_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL13_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL13_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 13 }, { "name": "X0Y14", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL14_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL14_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL14_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL14_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL14_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL14_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL14_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 14 }, { "name": "X0Y15", "prefix": "BUFGCTRL", "site_pins": { "CE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL15_CE0" }, "CE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL15_CE1" }, "I0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL15_I0" }, "I1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_BUFGCTRL15_I1" }, "IGNORE0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0" }, "IGNORE1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_BUFG_BUFGCTRL15_O" }, "S0": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL15_S0" }, "S1": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_BUFG_R_BUFGCTRL15_S1" } }, "type": "BUFGCTRL", "x_coord": 0, "y_coord": 15 } ], "tile_type": "CLK_BUFG_BOT_R", "wires": { "CLK_BUFG_BOT_R_CK_MUXED0": null, "CLK_BUFG_BOT_R_CK_MUXED1": null, "CLK_BUFG_BOT_R_CK_MUXED2": null, "CLK_BUFG_BOT_R_CK_MUXED3": null, "CLK_BUFG_BOT_R_CK_MUXED4": null, "CLK_BUFG_BOT_R_CK_MUXED5": null, "CLK_BUFG_BOT_R_CK_MUXED6": null, "CLK_BUFG_BOT_R_CK_MUXED7": null, "CLK_BUFG_BOT_R_CK_MUXED8": null, "CLK_BUFG_BOT_R_CK_MUXED9": null, "CLK_BUFG_BOT_R_CK_MUXED10": null, "CLK_BUFG_BOT_R_CK_MUXED11": null, "CLK_BUFG_BOT_R_CK_MUXED12": null, "CLK_BUFG_BOT_R_CK_MUXED13": null, "CLK_BUFG_BOT_R_CK_MUXED14": null, "CLK_BUFG_BOT_R_CK_MUXED15": null, "CLK_BUFG_BOT_R_CK_MUXED16": null, "CLK_BUFG_BOT_R_CK_MUXED17": null, "CLK_BUFG_BOT_R_CK_MUXED18": null, "CLK_BUFG_BOT_R_CK_MUXED19": null, "CLK_BUFG_BOT_R_CK_MUXED20": null, "CLK_BUFG_BOT_R_CK_MUXED21": null, "CLK_BUFG_BOT_R_CK_MUXED22": null, "CLK_BUFG_BOT_R_CK_MUXED23": null, "CLK_BUFG_BOT_R_CK_MUXED24": null, "CLK_BUFG_BOT_R_CK_MUXED25": null, "CLK_BUFG_BOT_R_CK_MUXED26": null, "CLK_BUFG_BOT_R_CK_MUXED27": null, "CLK_BUFG_BOT_R_CK_MUXED28": null, "CLK_BUFG_BOT_R_CK_MUXED29": null, "CLK_BUFG_BOT_R_CK_MUXED30": null, "CLK_BUFG_BOT_R_CK_MUXED31": null, "CLK_BUFG_BUFGCTRL0_I0": null, "CLK_BUFG_BUFGCTRL0_I1": null, "CLK_BUFG_BUFGCTRL0_O": null, "CLK_BUFG_BUFGCTRL1_I0": null, "CLK_BUFG_BUFGCTRL1_I1": null, "CLK_BUFG_BUFGCTRL1_O": null, "CLK_BUFG_BUFGCTRL2_I0": null, "CLK_BUFG_BUFGCTRL2_I1": null, "CLK_BUFG_BUFGCTRL2_O": null, "CLK_BUFG_BUFGCTRL3_I0": null, "CLK_BUFG_BUFGCTRL3_I1": null, "CLK_BUFG_BUFGCTRL3_O": null, "CLK_BUFG_BUFGCTRL4_I0": null, "CLK_BUFG_BUFGCTRL4_I1": null, "CLK_BUFG_BUFGCTRL4_O": null, "CLK_BUFG_BUFGCTRL5_I0": null, "CLK_BUFG_BUFGCTRL5_I1": null, "CLK_BUFG_BUFGCTRL5_O": null, "CLK_BUFG_BUFGCTRL6_I0": null, "CLK_BUFG_BUFGCTRL6_I1": null, "CLK_BUFG_BUFGCTRL6_O": null, "CLK_BUFG_BUFGCTRL7_I0": null, "CLK_BUFG_BUFGCTRL7_I1": null, "CLK_BUFG_BUFGCTRL7_O": null, "CLK_BUFG_BUFGCTRL8_I0": null, "CLK_BUFG_BUFGCTRL8_I1": null, "CLK_BUFG_BUFGCTRL8_O": null, "CLK_BUFG_BUFGCTRL9_I0": null, "CLK_BUFG_BUFGCTRL9_I1": null, "CLK_BUFG_BUFGCTRL9_O": null, "CLK_BUFG_BUFGCTRL10_I0": null, "CLK_BUFG_BUFGCTRL10_I1": null, "CLK_BUFG_BUFGCTRL10_O": null, "CLK_BUFG_BUFGCTRL11_I0": null, "CLK_BUFG_BUFGCTRL11_I1": null, "CLK_BUFG_BUFGCTRL11_O": null, "CLK_BUFG_BUFGCTRL12_I0": null, "CLK_BUFG_BUFGCTRL12_I1": null, "CLK_BUFG_BUFGCTRL12_O": null, "CLK_BUFG_BUFGCTRL13_I0": null, "CLK_BUFG_BUFGCTRL13_I1": null, "CLK_BUFG_BUFGCTRL13_O": null, "CLK_BUFG_BUFGCTRL14_I0": null, "CLK_BUFG_BUFGCTRL14_I1": null, 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"CLK_HROW_SW4A3_1": null, "CLK_HROW_SW4A3_2": null, "CLK_HROW_SW4A3_3": null, "CLK_HROW_SW4END0_0": null, "CLK_HROW_SW4END0_1": null, "CLK_HROW_SW4END0_2": null, "CLK_HROW_SW4END0_3": null, "CLK_HROW_SW4END1_0": null, "CLK_HROW_SW4END1_1": null, "CLK_HROW_SW4END1_2": null, "CLK_HROW_SW4END1_3": null, "CLK_HROW_SW4END2_0": null, "CLK_HROW_SW4END2_1": null, "CLK_HROW_SW4END2_2": null, "CLK_HROW_SW4END2_3": null, "CLK_HROW_SW4END3_0": null, "CLK_HROW_SW4END3_1": null, "CLK_HROW_SW4END3_2": null, "CLK_HROW_SW4END3_3": null, "CLK_HROW_WL1END0_0": null, "CLK_HROW_WL1END0_1": null, "CLK_HROW_WL1END0_2": null, "CLK_HROW_WL1END0_3": null, "CLK_HROW_WL1END1_0": null, "CLK_HROW_WL1END1_1": null, "CLK_HROW_WL1END1_2": null, "CLK_HROW_WL1END1_3": null, "CLK_HROW_WL1END2_0": null, "CLK_HROW_WL1END2_1": null, "CLK_HROW_WL1END2_2": null, "CLK_HROW_WL1END2_3": null, "CLK_HROW_WL1END3_0": null, "CLK_HROW_WL1END3_1": null, "CLK_HROW_WL1END3_2": null, "CLK_HROW_WL1END3_3": null, "CLK_HROW_WR1END0_0": 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"CLK_HROW_WW2END1_1": null, "CLK_HROW_WW2END1_2": null, "CLK_HROW_WW2END1_3": null, "CLK_HROW_WW2END2_0": null, "CLK_HROW_WW2END2_1": null, "CLK_HROW_WW2END2_2": null, "CLK_HROW_WW2END2_3": null, "CLK_HROW_WW2END3_0": null, "CLK_HROW_WW2END3_1": null, "CLK_HROW_WW2END3_2": null, "CLK_HROW_WW2END3_3": null, "CLK_HROW_WW4A0_0": null, "CLK_HROW_WW4A0_1": null, "CLK_HROW_WW4A0_2": null, "CLK_HROW_WW4A0_3": null, "CLK_HROW_WW4A1_0": null, "CLK_HROW_WW4A1_1": null, "CLK_HROW_WW4A1_2": null, "CLK_HROW_WW4A1_3": null, "CLK_HROW_WW4A2_0": null, "CLK_HROW_WW4A2_1": null, "CLK_HROW_WW4A2_2": null, "CLK_HROW_WW4A2_3": null, "CLK_HROW_WW4A3_0": null, "CLK_HROW_WW4A3_1": null, "CLK_HROW_WW4A3_2": null, "CLK_HROW_WW4A3_3": null, "CLK_HROW_WW4B0_0": null, "CLK_HROW_WW4B0_1": null, "CLK_HROW_WW4B0_2": null, "CLK_HROW_WW4B0_3": null, "CLK_HROW_WW4B1_0": null, "CLK_HROW_WW4B1_1": null, "CLK_HROW_WW4B1_2": null, "CLK_HROW_WW4B1_3": null, "CLK_HROW_WW4B2_0": null, "CLK_HROW_WW4B2_1": null, "CLK_HROW_WW4B2_2": null, "CLK_HROW_WW4B2_3": null, "CLK_HROW_WW4B3_0": null, "CLK_HROW_WW4B3_1": null, "CLK_HROW_WW4B3_2": null, "CLK_HROW_WW4B3_3": null, "CLK_HROW_WW4C0_0": null, "CLK_HROW_WW4C0_1": null, "CLK_HROW_WW4C0_2": null, "CLK_HROW_WW4C0_3": null, "CLK_HROW_WW4C1_0": null, "CLK_HROW_WW4C1_1": null, "CLK_HROW_WW4C1_2": null, "CLK_HROW_WW4C1_3": null, "CLK_HROW_WW4C2_0": null, "CLK_HROW_WW4C2_1": null, "CLK_HROW_WW4C2_2": null, "CLK_HROW_WW4C2_3": null, "CLK_HROW_WW4C3_0": null, "CLK_HROW_WW4C3_1": null, "CLK_HROW_WW4C3_2": null, "CLK_HROW_WW4C3_3": null, "CLK_HROW_WW4END0_0": null, "CLK_HROW_WW4END0_1": null, "CLK_HROW_WW4END0_2": null, "CLK_HROW_WW4END0_3": null, "CLK_HROW_WW4END1_0": null, "CLK_HROW_WW4END1_1": null, "CLK_HROW_WW4END1_2": null, "CLK_HROW_WW4END1_3": null, "CLK_HROW_WW4END2_0": null, "CLK_HROW_WW4END2_1": null, "CLK_HROW_WW4END2_2": null, "CLK_HROW_WW4END2_3": null, "CLK_HROW_WW4END3_0": null, "CLK_HROW_WW4END3_1": null, "CLK_HROW_WW4END3_2": null, "CLK_HROW_WW4END3_3": null } }