{ "pips": { "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT0->>CLK_HROW_BUFHCE_CE_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_BOT0" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT1->>CLK_HROW_BUFHCE_CE_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_BOT1" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT2->>CLK_HROW_BUFHCE_CE_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_BOT2" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT3->>CLK_HROW_BUFHCE_CE_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_BOT3" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT4->>CLK_HROW_BUFHCE_CE_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_BOT4" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT5->>CLK_HROW_BUFHCE_CE_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_BOT5" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT6->>CLK_HROW_BUFHCE_CE_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_BOT6" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT7->>CLK_HROW_BUFHCE_CE_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_BOT7" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT8->>CLK_HROW_BUFHCE_CE_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_BOT8" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT9->>CLK_HROW_BUFHCE_CE_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_BOT9" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT10->>CLK_HROW_BUFHCE_CE_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_BOT10" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT11->>CLK_HROW_BUFHCE_CE_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_BOT11" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP0->>CLK_HROW_BUFHCE_CE_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_TOP0" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP1->>CLK_HROW_BUFHCE_CE_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_TOP1" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP2->>CLK_HROW_BUFHCE_CE_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_TOP2" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP3->>CLK_HROW_BUFHCE_CE_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_TOP3" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP4->>CLK_HROW_BUFHCE_CE_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_TOP4" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP5->>CLK_HROW_BUFHCE_CE_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_TOP5" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP6->>CLK_HROW_BUFHCE_CE_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_TOP6" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP7->>CLK_HROW_BUFHCE_CE_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_TOP7" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP8->>CLK_HROW_BUFHCE_CE_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_TOP8" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP9->>CLK_HROW_BUFHCE_CE_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_TOP9" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP10->>CLK_HROW_BUFHCE_CE_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_TOP10" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP11->>CLK_HROW_BUFHCE_CE_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_BUFHCE_CE_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.016", "0.018", "0.050", "0.052" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CE_INT_TOP11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.119", "0.132", "0.378", "0.398" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST0->CLK_HROW_CK_GCLK_TEST_IN0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST1->CLK_HROW_CK_GCLK_TEST_IN1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST2->CLK_HROW_CK_GCLK_TEST_IN2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST3->CLK_HROW_CK_GCLK_TEST_IN3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST4->CLK_HROW_CK_GCLK_TEST_IN4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST5->CLK_HROW_CK_GCLK_TEST_IN5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST6->CLK_HROW_CK_GCLK_TEST_IN6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST7->CLK_HROW_CK_GCLK_TEST_IN7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST8->CLK_HROW_CK_GCLK_TEST_IN8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST9->CLK_HROW_CK_GCLK_TEST_IN9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST10->CLK_HROW_CK_GCLK_TEST_IN10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST11->CLK_HROW_CK_GCLK_TEST_IN11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST12->CLK_HROW_CK_GCLK_TEST_IN12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST13->CLK_HROW_CK_GCLK_TEST_IN13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST14->CLK_HROW_CK_GCLK_TEST_IN14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST14" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST15->CLK_HROW_CK_GCLK_TEST_IN15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST15" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST16->CLK_HROW_CK_GCLK_TEST_IN16": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN16", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST16" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST17->CLK_HROW_CK_GCLK_TEST_IN17": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN17", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST17" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST18->CLK_HROW_CK_GCLK_TEST_IN18": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN18", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST18" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST19->CLK_HROW_CK_GCLK_TEST_IN19": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN19", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST19" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST20->CLK_HROW_CK_GCLK_TEST_IN20": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN20", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST20" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST21->CLK_HROW_CK_GCLK_TEST_IN21": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN21", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST21" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST22->CLK_HROW_CK_GCLK_TEST_IN22": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN22", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST22" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST23->CLK_HROW_CK_GCLK_TEST_IN23": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN23", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST23" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST24->CLK_HROW_CK_GCLK_TEST_IN24": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN24", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST24" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST25->CLK_HROW_CK_GCLK_TEST_IN25": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN25", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST25" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST26->CLK_HROW_CK_GCLK_TEST_IN26": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN26", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST26" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST27->CLK_HROW_CK_GCLK_TEST_IN27": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN27", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST27" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST28->CLK_HROW_CK_GCLK_TEST_IN28": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN28", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST28" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST29->CLK_HROW_CK_GCLK_TEST_IN29": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN29", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST29" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST30->CLK_HROW_CK_GCLK_TEST_IN30": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN30", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST30" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST31->CLK_HROW_CK_GCLK_TEST_IN31": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN31", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST31" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT0->CLK_HROW_CK_GCLK_OUT_TEST0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT1->CLK_HROW_CK_GCLK_OUT_TEST1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT2->CLK_HROW_CK_GCLK_OUT_TEST2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT3->CLK_HROW_CK_GCLK_OUT_TEST3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT4->CLK_HROW_CK_GCLK_OUT_TEST4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT5->CLK_HROW_CK_GCLK_OUT_TEST5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT6->CLK_HROW_CK_GCLK_OUT_TEST6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT7->CLK_HROW_CK_GCLK_OUT_TEST7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT8->CLK_HROW_CK_GCLK_OUT_TEST8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT9->CLK_HROW_CK_GCLK_OUT_TEST9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT10->CLK_HROW_CK_GCLK_OUT_TEST10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT11->CLK_HROW_CK_GCLK_OUT_TEST11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT12->CLK_HROW_CK_GCLK_OUT_TEST12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT13->CLK_HROW_CK_GCLK_OUT_TEST13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT14->CLK_HROW_CK_GCLK_OUT_TEST14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT14" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT15->CLK_HROW_CK_GCLK_OUT_TEST15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT15" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT16->CLK_HROW_CK_GCLK_OUT_TEST16": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST16", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT16" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT17->CLK_HROW_CK_GCLK_OUT_TEST17": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST17", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT17" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT18->CLK_HROW_CK_GCLK_OUT_TEST18": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST18", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT18" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT19->CLK_HROW_CK_GCLK_OUT_TEST19": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST19", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT19" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT20->CLK_HROW_CK_GCLK_OUT_TEST20": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST20", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT20" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT21->CLK_HROW_CK_GCLK_OUT_TEST21": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST21", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT21" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT22->CLK_HROW_CK_GCLK_OUT_TEST22": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST22", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT22" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT23->CLK_HROW_CK_GCLK_OUT_TEST23": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST23", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT23" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT24->CLK_HROW_CK_GCLK_OUT_TEST24": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST24", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT24" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT25->CLK_HROW_CK_GCLK_OUT_TEST25": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST25", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT25" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT26->CLK_HROW_CK_GCLK_OUT_TEST26": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST26", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT26" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT27->CLK_HROW_CK_GCLK_OUT_TEST27": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST27", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT27" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT28->CLK_HROW_CK_GCLK_OUT_TEST28": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST28", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT28" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT29->CLK_HROW_CK_GCLK_OUT_TEST29": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST29", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT29" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT30->CLK_HROW_CK_GCLK_OUT_TEST30": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST30", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT30" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT31->CLK_HROW_CK_GCLK_OUT_TEST31": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST31", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT31" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L0->>CLK_HROW_CK_BUFHCLK_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L1->>CLK_HROW_CK_BUFHCLK_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L2->>CLK_HROW_CK_BUFHCLK_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L3->>CLK_HROW_CK_BUFHCLK_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L4->>CLK_HROW_CK_BUFHCLK_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L5->>CLK_HROW_CK_BUFHCLK_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L6->>CLK_HROW_CK_BUFHCLK_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L7->>CLK_HROW_CK_BUFHCLK_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L8->>CLK_HROW_CK_BUFHCLK_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L9->>CLK_HROW_CK_BUFHCLK_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L10->>CLK_HROW_CK_BUFHCLK_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L11->>CLK_HROW_CK_BUFHCLK_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R0->>CLK_HROW_CK_BUFHCLK_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R1->>CLK_HROW_CK_BUFHCLK_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R2->>CLK_HROW_CK_BUFHCLK_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R3->>CLK_HROW_CK_BUFHCLK_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R4->>CLK_HROW_CK_BUFHCLK_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R5->>CLK_HROW_CK_BUFHCLK_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R6->>CLK_HROW_CK_BUFHCLK_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R7->>CLK_HROW_CK_BUFHCLK_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R8->>CLK_HROW_CK_BUFHCLK_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R9->>CLK_HROW_CK_BUFHCLK_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R10->>CLK_HROW_CK_BUFHCLK_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R11->>CLK_HROW_CK_BUFHCLK_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.000", "0.190", "0.000", "0.000" ], "in_cap": null, "res": null }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.127", "0.140", "0.418", "0.440" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_OUT_TEST->CLK_HROW_CK_IN_L_TEST_OUT": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_IN_L_TEST_OUT", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_IN_L_OUT_TEST" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_TEST_IN->CLK_HROW_CK_IN_L_IN_TEST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_IN_L_IN_TEST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_IN_L_TEST_IN" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.112", "0.386", "0.424" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.152", "0.160", "0.633", "0.665" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_OUT_TEST->CLK_HROW_CK_IN_R_TEST_OUT": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_IN_R_TEST_OUT", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_IN_R_OUT_TEST" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_TEST_IN->CLK_HROW_CK_IN_R_IN_TEST": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_IN_R_IN_TEST", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CK_IN_R_TEST_IN" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L0->>CLK_HROW_CK_HCLK_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L1->>CLK_HROW_CK_HCLK_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L2->>CLK_HROW_CK_HCLK_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L3->>CLK_HROW_CK_HCLK_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L4->>CLK_HROW_CK_HCLK_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L5->>CLK_HROW_CK_HCLK_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L6->>CLK_HROW_CK_HCLK_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L7->>CLK_HROW_CK_HCLK_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L8->>CLK_HROW_CK_HCLK_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L9->>CLK_HROW_CK_HCLK_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L10->>CLK_HROW_CK_HCLK_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L11->>CLK_HROW_CK_HCLK_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R0->>CLK_HROW_CK_HCLK_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R1->>CLK_HROW_CK_HCLK_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R2->>CLK_HROW_CK_HCLK_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R3->>CLK_HROW_CK_HCLK_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R4->>CLK_HROW_CK_HCLK_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R5->>CLK_HROW_CK_HCLK_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R6->>CLK_HROW_CK_HCLK_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R7->>CLK_HROW_CK_HCLK_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R8->>CLK_HROW_CK_HCLK_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R9->>CLK_HROW_CK_HCLK_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R10->>CLK_HROW_CK_HCLK_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R11->>CLK_HROW_CK_HCLK_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "1", "src_to_dst": { "delay": [ "0.020", "0.043", "0.081", "0.127" ], "in_cap": null, "res": "0.0" }, "src_wire": "CLK_HROW_CK_MUX_OUT_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CLK0_3->CLK_HROW_CK_INT_0_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_INT_0_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CLK0_3" }, "CLK_HROW_TOP_R.CLK_HROW_CLK0_4->CLK_HROW_CK_INT_1_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_INT_1_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CLK0_4" }, "CLK_HROW_TOP_R.CLK_HROW_CLK1_3->CLK_HROW_CK_INT_0_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_INT_0_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CLK1_3" }, "CLK_HROW_TOP_R.CLK_HROW_CLK1_4->CLK_HROW_CK_INT_1_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CK_INT_1_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_CLK1_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX0_3->CLK_HROW_CE_INT_BOT0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_BOT0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX0_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX0_4->CLK_HROW_CE_INT_TOP0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_TOP0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX0_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX1_3->CLK_HROW_CE_INT_BOT1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_BOT1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX1_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX1_4->CLK_HROW_CE_INT_TOP1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_TOP1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX1_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX2_3->CLK_HROW_CE_INT_BOT2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_BOT2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX2_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX2_4->CLK_HROW_CE_INT_TOP2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_TOP2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX2_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX3_3->CLK_HROW_CE_INT_BOT3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_BOT3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX3_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX3_4->CLK_HROW_CE_INT_TOP3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_TOP3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX3_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX4_3->CLK_HROW_CE_INT_BOT4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_BOT4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX4_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX4_4->CLK_HROW_CE_INT_TOP4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_TOP4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX4_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX5_3->CLK_HROW_CE_INT_BOT5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_BOT5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX5_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX5_4->CLK_HROW_CE_INT_TOP5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_TOP5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX5_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX6_3->CLK_HROW_CE_INT_BOT6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_BOT6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX6_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX6_4->CLK_HROW_CE_INT_TOP6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_TOP6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX6_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX7_3->CLK_HROW_CE_INT_BOT7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_BOT7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX7_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX7_4->CLK_HROW_CE_INT_TOP7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_TOP7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX7_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX8_3->CLK_HROW_CE_INT_BOT8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_BOT8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX8_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX8_4->CLK_HROW_CE_INT_TOP8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_TOP8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX8_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX9_3->CLK_HROW_CE_INT_BOT9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_BOT9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX9_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX9_4->CLK_HROW_CE_INT_TOP9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_TOP9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX9_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX10_3->CLK_HROW_CE_INT_BOT10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_BOT10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX10_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX10_4->CLK_HROW_CE_INT_TOP10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_TOP10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX10_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX11_3->CLK_HROW_CE_INT_BOT11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_BOT11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX11_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX11_4->CLK_HROW_CE_INT_TOP11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CLK_HROW_CE_INT_TOP11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CLK_HROW_IMUX11_4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.100", "0.110", "0.324", "0.341" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN0" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN1" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN2" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN3" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN4" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN5" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN6" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN7" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN8" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN9" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN10" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN11" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN12" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN13" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN14->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN14" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN15->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN15" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN16->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN16" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN17->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN17" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN18->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN18" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN19->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN19" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN20->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN20" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN21->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN21" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN22->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN22" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN23->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN23" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN24->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN24" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN25->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN25" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN26->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN26" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN27->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN27" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN28->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN28" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN29->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN29" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN30->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN30" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN31->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", "dst_to_src": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", "is_pass_transistor": 0, "is_pseudo": "0", "src_to_dst": { "delay": [ "0.168", "0.176", "0.287", "0.302" ], "in_cap": "0.000", "res": "0.0" }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN31" } }, "sites": [ { "name": "X0Y0", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_L0" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_L0" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_L0" } }, "type": "BUFHCE", "x_coord": 0, "y_coord": 0 }, { "name": "X0Y1", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_L1" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_L1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_L1" } }, "type": "BUFHCE", "x_coord": 0, "y_coord": 1 }, { "name": "X0Y2", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_L2" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_L2" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_L2" } }, "type": "BUFHCE", "x_coord": 0, "y_coord": 2 }, { "name": "X0Y3", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_L3" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_L3" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_L3" } }, "type": "BUFHCE", "x_coord": 0, "y_coord": 3 }, { "name": "X0Y4", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_L4" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_L4" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_L4" } }, "type": "BUFHCE", "x_coord": 0, "y_coord": 4 }, { "name": "X0Y5", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_L5" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_L5" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_L5" } }, "type": "BUFHCE", "x_coord": 0, "y_coord": 5 }, { "name": "X0Y6", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_L6" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_L6" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_L6" } }, "type": "BUFHCE", "x_coord": 0, "y_coord": 6 }, { "name": "X0Y7", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_L7" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_L7" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_L7" } }, "type": "BUFHCE", "x_coord": 0, "y_coord": 7 }, { "name": "X0Y8", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_L8" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_L8" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_L8" } }, "type": "BUFHCE", "x_coord": 0, "y_coord": 8 }, { "name": "X0Y9", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_L9" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_L9" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_L9" } }, "type": "BUFHCE", "x_coord": 0, "y_coord": 9 }, { "name": "X0Y10", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_L10" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_L10" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_L10" } }, "type": "BUFHCE", "x_coord": 0, "y_coord": 10 }, { "name": "X0Y11", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_L11" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_L11" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_L11" } }, "type": "BUFHCE", "x_coord": 0, "y_coord": 11 }, { "name": "X1Y0", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_R0" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_R0" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_R0" } }, "type": "BUFHCE", "x_coord": 1, "y_coord": 0 }, { "name": "X1Y1", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_R1" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_R1" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_R1" } }, "type": "BUFHCE", "x_coord": 1, "y_coord": 1 }, { "name": "X1Y2", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_R2" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_R2" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_R2" } }, "type": "BUFHCE", "x_coord": 1, "y_coord": 2 }, { "name": "X1Y3", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_R3" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_R3" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_R3" } }, "type": "BUFHCE", "x_coord": 1, "y_coord": 3 }, { "name": "X1Y4", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_R4" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_R4" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_R4" } }, "type": "BUFHCE", "x_coord": 1, "y_coord": 4 }, { "name": "X1Y5", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_R5" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_R5" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_R5" } }, "type": "BUFHCE", "x_coord": 1, "y_coord": 5 }, { "name": "X1Y6", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_R6" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_R6" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_R6" } }, "type": "BUFHCE", "x_coord": 1, "y_coord": 6 }, { "name": "X1Y7", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_R7" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_R7" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_R7" } }, "type": "BUFHCE", "x_coord": 1, "y_coord": 7 }, { "name": "X1Y8", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_R8" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_R8" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_R8" } }, "type": "BUFHCE", "x_coord": 1, "y_coord": 8 }, { "name": "X1Y9", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_R9" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_R9" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_R9" } }, "type": "BUFHCE", "x_coord": 1, "y_coord": 9 }, { "name": "X1Y10", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_R10" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_R10" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_R10" } }, "type": "BUFHCE", "x_coord": 1, "y_coord": 10 }, { "name": "X1Y11", "prefix": "BUFHCE", "site_pins": { "CE": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_BUFHCE_CE_R11" }, "I": { "cap": "0.000", "delay": [ "0.001", "0.001", "0.001", "0.001" ], "wire": "CLK_HROW_CK_MUX_OUT_R11" }, "O": { "delay": [ "0.001", "0.001", "0.001", "0.001" ], "res": "0.0", "wire": "CLK_HROW_CK_HCLK_OUT_R11" } }, "type": "BUFHCE", "x_coord": 1, "y_coord": 11 } ], "tile_type": "CLK_HROW_TOP_R", "wires": { "CLK_HROW_BLOCK_OUTS_B0_0": null, "CLK_HROW_BLOCK_OUTS_B0_1": null, "CLK_HROW_BLOCK_OUTS_B0_2": null, "CLK_HROW_BLOCK_OUTS_B0_3": null, "CLK_HROW_BLOCK_OUTS_B0_4": null, "CLK_HROW_BLOCK_OUTS_B0_5": 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"CLK_HROW_WW4C1_5": null, "CLK_HROW_WW4C1_6": null, "CLK_HROW_WW4C1_7": null, "CLK_HROW_WW4C2_0": null, "CLK_HROW_WW4C2_1": null, "CLK_HROW_WW4C2_2": null, "CLK_HROW_WW4C2_3": null, "CLK_HROW_WW4C2_4": null, "CLK_HROW_WW4C2_5": null, "CLK_HROW_WW4C2_6": null, "CLK_HROW_WW4C2_7": null, "CLK_HROW_WW4C3_0": null, "CLK_HROW_WW4C3_1": null, "CLK_HROW_WW4C3_2": null, "CLK_HROW_WW4C3_3": null, "CLK_HROW_WW4C3_4": null, "CLK_HROW_WW4C3_5": null, "CLK_HROW_WW4C3_6": null, "CLK_HROW_WW4C3_7": null, "CLK_HROW_WW4END0_0": null, "CLK_HROW_WW4END0_1": null, "CLK_HROW_WW4END0_2": null, "CLK_HROW_WW4END0_3": null, "CLK_HROW_WW4END0_4": null, "CLK_HROW_WW4END0_5": null, "CLK_HROW_WW4END0_6": null, "CLK_HROW_WW4END0_7": null, "CLK_HROW_WW4END1_0": null, "CLK_HROW_WW4END1_1": null, "CLK_HROW_WW4END1_2": null, "CLK_HROW_WW4END1_3": null, "CLK_HROW_WW4END1_4": null, "CLK_HROW_WW4END1_5": null, "CLK_HROW_WW4END1_6": null, "CLK_HROW_WW4END1_7": null, "CLK_HROW_WW4END2_0": null, "CLK_HROW_WW4END2_1": null, "CLK_HROW_WW4END2_2": null, "CLK_HROW_WW4END2_3": null, "CLK_HROW_WW4END2_4": null, "CLK_HROW_WW4END2_5": null, "CLK_HROW_WW4END2_6": null, "CLK_HROW_WW4END2_7": null, "CLK_HROW_WW4END3_0": null, "CLK_HROW_WW4END3_1": null, "CLK_HROW_WW4END3_2": null, "CLK_HROW_WW4END3_3": null, "CLK_HROW_WW4END3_4": null, "CLK_HROW_WW4END3_5": null, "CLK_HROW_WW4END3_6": null, "CLK_HROW_WW4END3_7": null } }