{
    "pips": {
        "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_BB_PREF_IN0"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_BB_PREF_IN0"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_BB_PREF_IN0"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_BB_PREF_IN1"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_BB_PREF_IN1"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN1->>CMT_FREQ_PHASER_REFMUX_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_BB_PREF_IN1"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_BB_PREF_IN2"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_BB_PREF_IN2"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN2->>CMT_FREQ_PHASER_REFMUX_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_BB_PREF_IN2"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_BB_PREF_IN3"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_BB_PREF_IN3"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN3->>CMT_FREQ_PHASER_REFMUX_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.063",
                    "0.070",
                    "0.204",
                    "0.215"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_BB_PREF_IN3"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.078",
                    "0.086",
                    "0.229",
                    "0.241"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.078",
                    "0.086",
                    "0.229",
                    "0.241"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_0"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.072",
                    "0.080",
                    "0.219",
                    "0.231"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.072",
                    "0.080",
                    "0.219",
                    "0.231"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_0"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.078",
                    "0.087",
                    "0.235",
                    "0.248"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.078",
                    "0.087",
                    "0.235",
                    "0.248"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_0"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.071",
                    "0.078",
                    "0.225",
                    "0.237"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.071",
                    "0.078",
                    "0.225",
                    "0.237"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_0"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_0->>CMT_PHASER_REF_CLKIN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.092",
                    "0.101",
                    "0.267",
                    "0.281"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_REF_CLKIN",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.092",
                    "0.101",
                    "0.267",
                    "0.281"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_0"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.078",
                    "0.086",
                    "0.229",
                    "0.241"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.078",
                    "0.086",
                    "0.229",
                    "0.241"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.072",
                    "0.080",
                    "0.219",
                    "0.231"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.072",
                    "0.080",
                    "0.219",
                    "0.231"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.078",
                    "0.087",
                    "0.235",
                    "0.248"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.078",
                    "0.087",
                    "0.235",
                    "0.248"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.071",
                    "0.078",
                    "0.225",
                    "0.237"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_MEMREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.071",
                    "0.078",
                    "0.225",
                    "0.237"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_1->>CMT_PHY_CONTROL_MEMREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.076",
                    "0.084",
                    "0.242",
                    "0.255"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHY_CONTROL_MEMREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.076",
                    "0.084",
                    "0.242",
                    "0.255"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_CA_SYNCIN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.071",
                    "0.078",
                    "0.225",
                    "0.237"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_IN_CA_SYNCIN",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.071",
                    "0.078",
                    "0.225",
                    "0.237"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_IN_DB_SYNCIN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.071",
                    "0.078",
                    "0.225",
                    "0.237"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_IN_DB_SYNCIN",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.071",
                    "0.078",
                    "0.225",
                    "0.237"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_CA_SYNCIN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.071",
                    "0.078",
                    "0.225",
                    "0.237"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_SYNCIN",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.071",
                    "0.078",
                    "0.225",
                    "0.237"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHASER_OUT_DB_SYNCIN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.071",
                    "0.078",
                    "0.225",
                    "0.237"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_SYNCIN",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.071",
                    "0.078",
                    "0.225",
                    "0.237"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_FREQ_PHASER_REFMUX_2->>CMT_PHY_CONTROL_SYNCIN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.076",
                    "0.084",
                    "0.242",
                    "0.255"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHY_CONTROL_SYNCIN",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.076",
                    "0.084",
                    "0.242",
                    "0.255"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_FREQ_PHASER_REFMUX_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASERIN_C->CMT_PHASER_IN_CA_PHASEREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASERREF_PHASERIN_C"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASERIN_D->CMT_PHASER_IN_DB_PHASEREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASERREF_PHASERIN_D"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASEROUT_C->CMT_PHASER_OUT_CA_PHASEREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASERREF_PHASEROUT_C"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASERREF_PHASEROUT_D->CMT_PHASER_OUT_DB_PHASEREFCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASERREF_PHASEROUT_D"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLEMPTY->>CMT_PHASER_TOP_SYNC_BB": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": null,
                "res": null
            },
            "dst_wire": "CMT_PHASER_TOP_SYNC_BB",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": null,
                "res": null
            },
            "src_wire": "CMT_PHASERTOP_PHYCTLEMPTY"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASERTOP_PHYCTLMSTREMPTY->CMT_PHY_CONTROL_PHYCTLMSTREMPTY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.221",
                    "0.255"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLKDIV_0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.221",
                    "0.255"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.221",
                    "0.255"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLKDIV_1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.221",
                    "0.255"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.091",
                    "0.105",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLKDIV_2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.091",
                    "0.105",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.091",
                    "0.105",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLKDIV_3",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.091",
                    "0.105",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.091",
                    "0.105",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLKDIV_4",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.091",
                    "0.105",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLKDIV_5",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.222",
                    "0.256"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLKDIV_6",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.222",
                    "0.256"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.094",
                    "0.108",
                    "0.222",
                    "0.256"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLKDIV_7",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.094",
                    "0.108",
                    "0.222",
                    "0.256"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.094",
                    "0.108",
                    "0.223",
                    "0.257"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLKDIV_8",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.094",
                    "0.108",
                    "0.223",
                    "0.257"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.095",
                    "0.109",
                    "0.225",
                    "0.259"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLKDIV_9",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.095",
                    "0.109",
                    "0.225",
                    "0.259"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.096",
                    "0.110",
                    "0.226",
                    "0.260"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLKDIV_10",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.096",
                    "0.110",
                    "0.226",
                    "0.260"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.096",
                    "0.110",
                    "0.226",
                    "0.260"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLKDIV_11",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.096",
                    "0.110",
                    "0.226",
                    "0.260"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.096",
                    "0.110",
                    "0.228",
                    "0.262"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLK_0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.096",
                    "0.110",
                    "0.228",
                    "0.262"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.097",
                    "0.111",
                    "0.228",
                    "0.262"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLK_1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.097",
                    "0.111",
                    "0.228",
                    "0.262"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.097",
                    "0.111",
                    "0.227",
                    "0.261"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLK_2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.097",
                    "0.111",
                    "0.227",
                    "0.261"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.097",
                    "0.111",
                    "0.227",
                    "0.261"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLK_3",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.097",
                    "0.111",
                    "0.227",
                    "0.261"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.096",
                    "0.110",
                    "0.227",
                    "0.261"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLK_4",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.096",
                    "0.110",
                    "0.227",
                    "0.261"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.096",
                    "0.110",
                    "0.227",
                    "0.261"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLK_5",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.096",
                    "0.110",
                    "0.227",
                    "0.261"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.097",
                    "0.111",
                    "0.228",
                    "0.262"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLK_6",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.097",
                    "0.111",
                    "0.228",
                    "0.262"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.097",
                    "0.111",
                    "0.228",
                    "0.262"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLK_7",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.097",
                    "0.111",
                    "0.228",
                    "0.262"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.098",
                    "0.112",
                    "0.229",
                    "0.263"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLK_8",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.098",
                    "0.112",
                    "0.229",
                    "0.263"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.099",
                    "0.113",
                    "0.231",
                    "0.265"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLK_9",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.099",
                    "0.113",
                    "0.231",
                    "0.265"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.099",
                    "0.113",
                    "0.231",
                    "0.265"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLK_10",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.099",
                    "0.113",
                    "0.231",
                    "0.265"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_ICLK_TOIOI->>CMT_TOP_ICLK_11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.099",
                    "0.113",
                    "0.231",
                    "0.265"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_ICLK_11",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.099",
                    "0.113",
                    "0.231",
                    "0.265"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_ICLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK90_TOIOI->>CMT_TOP_OCLK1X_90_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.094",
                    "0.108",
                    "0.219",
                    "0.252"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK1X_90_7",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.094",
                    "0.108",
                    "0.219",
                    "0.252"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK90_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLKDIV_0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLKDIV_1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLKDIV_2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLKDIV_3",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.220",
                    "0.253"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.218",
                    "0.251"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLKDIV_4",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.218",
                    "0.251"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.218",
                    "0.251"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLKDIV_5",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.218",
                    "0.251"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.216",
                    "0.249"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLKDIV_6",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.216",
                    "0.249"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.216",
                    "0.249"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLKDIV_7",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.216",
                    "0.249"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.216",
                    "0.249"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLKDIV_8",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.216",
                    "0.249"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.219",
                    "0.252"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLKDIV_9",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.093",
                    "0.107",
                    "0.219",
                    "0.252"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.094",
                    "0.108",
                    "0.219",
                    "0.252"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLKDIV_10",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.094",
                    "0.108",
                    "0.219",
                    "0.252"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLKDIV_TOIOI->>CMT_TOP_OCLKDIV_11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.094",
                    "0.108",
                    "0.219",
                    "0.252"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLKDIV_11",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.094",
                    "0.108",
                    "0.219",
                    "0.252"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLKDIV_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.090",
                    "0.104",
                    "0.215",
                    "0.248"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK_0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.090",
                    "0.104",
                    "0.215",
                    "0.248"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.090",
                    "0.104",
                    "0.215",
                    "0.248"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK_1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.090",
                    "0.104",
                    "0.215",
                    "0.248"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.090",
                    "0.104",
                    "0.214",
                    "0.246"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK_2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.090",
                    "0.104",
                    "0.214",
                    "0.246"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.090",
                    "0.104",
                    "0.214",
                    "0.246"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK_3",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.090",
                    "0.104",
                    "0.214",
                    "0.246"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.089",
                    "0.103",
                    "0.213",
                    "0.245"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK_4",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.089",
                    "0.103",
                    "0.213",
                    "0.245"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.089",
                    "0.103",
                    "0.213",
                    "0.245"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK_5",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.089",
                    "0.103",
                    "0.213",
                    "0.245"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.089",
                    "0.103",
                    "0.212",
                    "0.244"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK_6",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.089",
                    "0.103",
                    "0.212",
                    "0.244"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.090",
                    "0.104",
                    "0.214",
                    "0.246"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK_7",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.090",
                    "0.104",
                    "0.214",
                    "0.246"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.091",
                    "0.105",
                    "0.215",
                    "0.248"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK_8",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.091",
                    "0.105",
                    "0.215",
                    "0.248"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.216",
                    "0.249"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK_9",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.216",
                    "0.249"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.216",
                    "0.249"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK_10",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.216",
                    "0.249"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_C_OCLK_TOIOI->>CMT_TOP_OCLK_11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.218",
                    "0.251"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_TOP_OCLK_11",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.092",
                    "0.106",
                    "0.218",
                    "0.251"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_C_OCLK_TOIOI"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B3_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B21_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B3_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B21_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B6_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_DQSFOUND"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B15_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_C_ICLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_C_ICLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_ICLK"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ICLKDIV->CMT_R_PHASER_IN_C_WRCLK_FIFO": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_R_PHASER_IN_C_WRCLK_FIFO",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_ICLKDIV"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_ISERDESRST"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.100",
                    "0.115",
                    "0.228",
                    "0.263"
                ],
                "in_cap": null,
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_IN_CA_RCLK",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "1",
            "src_to_dst": {
                "delay": [
                    "0.100",
                    "0.115",
                    "0.228",
                    "0.263"
                ],
                "in_cap": null,
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_C_RCLK2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_C_RCLK2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_RCLK"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_C_WRENABLE_FIFO": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_C_WRENABLE_FIFO",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_CA_WRENABLE"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK->>CMT_PHASER_C_ICLK_TOIOI": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.031",
                    "0.035",
                    "0.096",
                    "0.101"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_C_ICLK_TOIOI",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.031",
                    "0.035",
                    "0.096",
                    "0.101"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_IN_C_ICLK"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV->>CMT_PHASER_C_ICLKDIV_TOIOI": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.034",
                    "0.037",
                    "0.098",
                    "0.103"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_C_ICLKDIV_TOIOI",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.034",
                    "0.037",
                    "0.098",
                    "0.103"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_IN_C_ICLKDIV"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B18_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B1_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B9_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_DQSFOUND"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B9_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B6_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_D_ICLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_D_ICLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_ICLK"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ICLKDIV->CMT_R_PHASER_IN_D_WRCLK_TOFIFO": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_R_PHASER_IN_D_WRCLK_TOFIFO",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_ICLKDIV"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_ISERDESRST"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.100",
                    "0.115",
                    "0.228",
                    "0.263"
                ],
                "in_cap": null,
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_IN_DB_RCLK",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "1",
            "src_to_dst": {
                "delay": [
                    "0.100",
                    "0.115",
                    "0.228",
                    "0.263"
                ],
                "in_cap": null,
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_D_RCLK3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_D_RCLK3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_RCLK"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_D_WRENABLE_FIFO": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_D_WRENABLE_FIFO",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_IN_DB_WRENABLE"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B15_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B15_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B3_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B21_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B7_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B23_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_C_OCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_C_OCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_OCLK"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_C_OCLK1X_90": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_C_OCLK1X_90",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLKDIV->CMT_R_PHASER_OUT_C_RDCLK_FIFO": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_R_PHASER_OUT_C_RDCLK_FIFO",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RDENABLE->CMT_R_PHASER_OUT_C_RDENABLE_FIFO": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_R_PHASER_OUT_C_RDENABLE_FIFO",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_CA_RDENABLE"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90->>CMT_PHASER_C_OCLK90_TOIOI": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.033",
                    "0.036",
                    "0.096",
                    "0.101"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_C_OCLK90_TOIOI",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.033",
                    "0.036",
                    "0.096",
                    "0.101"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_OUT_C_OCLK1X_90"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK->>CMT_PHASER_C_OCLK_TOIOI": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.031",
                    "0.035",
                    "0.090",
                    "0.095"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_C_OCLK_TOIOI",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.031",
                    "0.035",
                    "0.090",
                    "0.095"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_OUT_C_OCLK"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV->>CMT_PHASER_C_OCLKDIV_TOIOI": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.034",
                    "0.038",
                    "0.102",
                    "0.107"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASER_C_OCLKDIV_TOIOI",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.034",
                    "0.038",
                    "0.102",
                    "0.107"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_OUT_C_OCLKDIV"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B6_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS0->CMT_PHASERD_CTSBUS0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASERD_CTSBUS0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS1->CMT_PHASERD_CTSBUS1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASERD_CTSBUS1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS0->CMT_PHASERD_DQSBUS0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASERD_DQSBUS0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS1->CMT_PHASERD_DQSBUS1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASERD_DQSBUS1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS0->CMT_PHASERD_DTSBUS0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASERD_DTSBUS0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS1->CMT_PHASERD_DTSBUS1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASERD_DTSBUS1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_D_OCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_D_OCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_OCLK"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_D_OCLK1X_90": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_D_OCLK1X_90",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLKDIV->CMT_R_PHASER_OUT_D_RDCLK_TOFIFO": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B16_5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RDENABLE->CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_OUT_DB_RDENABLE"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKOUT->CMT_PHASER_REF_CLKOUT_TOHCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_REF_CLKOUT_TOHCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_REF_CLKOUT"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_LOCKED->CMT_TOP_LOGIC_OUTS_L_B14_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_REF_LOCKED"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_TMUXOUT->CMT_PHASER_REF_TMUXOUT_TOHCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_REF_TMUXOUT_TOHCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHASER_REF_TMUXOUT"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_TOP_SYNC_BB->>CMT_PHASERTOP_PHYCTLMSTREMPTY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERTOP_PHYCTLMSTREMPTY",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_TOP_SYNC_BB"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_C->>CMT_PHASERREF_PHASERIN_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.086",
                    "0.095",
                    "0.261",
                    "0.275"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.086",
                    "0.095",
                    "0.261",
                    "0.275"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_C"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_DQS_TO_PHASER_D->>CMT_PHASERREF_PHASERIN_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.095",
                    "0.105",
                    "0.291",
                    "0.306"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.095",
                    "0.105",
                    "0.291",
                    "0.306"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_DQS_TO_PHASER_D"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.149",
                    "0.165",
                    "0.445",
                    "0.468"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.149",
                    "0.165",
                    "0.445",
                    "0.468"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASERIN_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.152",
                    "0.168",
                    "0.452",
                    "0.475"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.152",
                    "0.168",
                    "0.452",
                    "0.475"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.146",
                    "0.161",
                    "0.439",
                    "0.462"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASEROUT_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.146",
                    "0.161",
                    "0.439",
                    "0.462"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF0->>CMT_PHASERREF_PHASEROUT_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.149",
                    "0.165",
                    "0.447",
                    "0.470"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASEROUT_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.149",
                    "0.165",
                    "0.447",
                    "0.470"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.149",
                    "0.165",
                    "0.445",
                    "0.468"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.149",
                    "0.165",
                    "0.445",
                    "0.468"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASERIN_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.152",
                    "0.168",
                    "0.452",
                    "0.475"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.152",
                    "0.168",
                    "0.452",
                    "0.475"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.146",
                    "0.161",
                    "0.439",
                    "0.462"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASEROUT_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.146",
                    "0.161",
                    "0.439",
                    "0.462"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF1->>CMT_PHASERREF_PHASEROUT_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.149",
                    "0.165",
                    "0.447",
                    "0.470"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASEROUT_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.149",
                    "0.165",
                    "0.447",
                    "0.470"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.155",
                    "0.171",
                    "0.453",
                    "0.476"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.155",
                    "0.171",
                    "0.453",
                    "0.476"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASERIN_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.152",
                    "0.168",
                    "0.448",
                    "0.472"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.152",
                    "0.168",
                    "0.448",
                    "0.472"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.151",
                    "0.166",
                    "0.447",
                    "0.470"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASEROUT_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.151",
                    "0.166",
                    "0.447",
                    "0.470"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE0->>CMT_PHASERREF_PHASEROUT_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.149",
                    "0.165",
                    "0.445",
                    "0.468"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASEROUT_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.149",
                    "0.165",
                    "0.445",
                    "0.468"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.155",
                    "0.171",
                    "0.453",
                    "0.476"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.155",
                    "0.171",
                    "0.453",
                    "0.476"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASERIN_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.152",
                    "0.168",
                    "0.448",
                    "0.472"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.152",
                    "0.168",
                    "0.448",
                    "0.472"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.151",
                    "0.166",
                    "0.447",
                    "0.470"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASEROUT_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.151",
                    "0.166",
                    "0.447",
                    "0.470"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_ABOVE1->>CMT_PHASERREF_PHASEROUT_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.149",
                    "0.165",
                    "0.445",
                    "0.468"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASEROUT_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.149",
                    "0.165",
                    "0.445",
                    "0.468"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_ABOVE1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.180",
                    "0.199",
                    "0.497",
                    "0.523"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.180",
                    "0.199",
                    "0.497",
                    "0.523"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASERIN_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.181",
                    "0.199",
                    "0.497",
                    "0.523"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.181",
                    "0.199",
                    "0.497",
                    "0.523"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.176",
                    "0.194",
                    "0.489",
                    "0.514"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASEROUT_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.176",
                    "0.194",
                    "0.489",
                    "0.514"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW0->>CMT_PHASERREF_PHASEROUT_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.177",
                    "0.195",
                    "0.491",
                    "0.517"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASEROUT_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.177",
                    "0.195",
                    "0.491",
                    "0.517"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.180",
                    "0.199",
                    "0.497",
                    "0.523"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.180",
                    "0.199",
                    "0.497",
                    "0.523"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASERIN_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.181",
                    "0.199",
                    "0.497",
                    "0.523"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASERIN_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.181",
                    "0.199",
                    "0.497",
                    "0.523"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_C": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.176",
                    "0.194",
                    "0.489",
                    "0.514"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASEROUT_C",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.176",
                    "0.194",
                    "0.489",
                    "0.514"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHASER_UP_PHASERREF_BELOW1->>CMT_PHASERREF_PHASEROUT_D": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.177",
                    "0.195",
                    "0.491",
                    "0.517"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_PHASERREF_PHASEROUT_D",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.177",
                    "0.195",
                    "0.491",
                    "0.517"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_PHASER_UP_PHASERREF_BELOW1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT0->CMT_TOP_LOGIC_OUTS_L_B3_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT1->CMT_TOP_LOGIC_OUTS_L_B21_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT2->CMT_TOP_LOGIC_OUTS_L_B17_10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT2"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_AUXOUTPUT3->CMT_TOP_LOGIC_OUTS_L_B17_11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_11",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_AUXOUTPUT3"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_ECALIB0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_ECALIB0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_ECALIB0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_ECALIB0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_ECALIB1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_ECALIB1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_ECALIB1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_ECALIB1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2->CMT_PHASER_IN_CA_BURSTPENDINGPHY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING2"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3->CMT_PHASER_IN_DB_BURSTPENDINGPHY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING3"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING0->CMT_PHY_CONTROL_IBURSTPENDING0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING1->CMT_PHY_CONTROL_IBURSTPENDING1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING2->CMT_PHY_CONTROL_IBURSTPENDING2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING2"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING3->CMT_PHY_CONTROL_IBURSTPENDING3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING3"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKA0->CMT_PHY_CONTROL_IRANKA0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_IRANKA0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_INRANKA0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKA1->CMT_PHY_CONTROL_IRANKA1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_IRANKA1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_INRANKA1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKB0->CMT_PHY_CONTROL_IRANKB0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_IRANKB0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_INRANKB0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKB1->CMT_PHY_CONTROL_IRANKB1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_IRANKB1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_INRANKB1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKC0->CMT_PHY_CONTROL_IRANKC0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_IRANKC0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_INRANKC0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKC1->CMT_PHY_CONTROL_IRANKC1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_IRANKC1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_INRANKC1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKD0->CMT_PHY_CONTROL_IRANKD0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_IRANKD0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_INRANKD0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKD1->CMT_PHY_CONTROL_IRANKD1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_IRANKD1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_INRANKD1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC0->CMT_PHASER_IN_CA_RANKSELPHY0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_IRANKC0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC1->CMT_PHASER_IN_CA_RANKSELPHY1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_IRANKC1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD0->CMT_PHASER_IN_DB_RANKSELPHY0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_IRANKD0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD1->CMT_PHASER_IN_DB_RANKSELPHY1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_IRANKD1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING2"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING3"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING0->CMT_PHY_CONTROL_OBURSTPENDING0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING1->CMT_PHY_CONTROL_OBURSTPENDING1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING2->CMT_PHY_CONTROL_OBURSTPENDING2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING3->CMT_PHY_CONTROL_OBURSTPENDING3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB0->CMT_PHY_CONTROL_ECALIB0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_ECALIB0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB0"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB1->CMT_PHY_CONTROL_ECALIB1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_ECALIB1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB1"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLALMOSTFULL->CMT_TOP_LOGIC_OUTS_L_B7_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLEMPTY->CMT_PHASERTOP_PHYCTLEMPTY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASERTOP_PHYCTLEMPTY",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_PHYCTLEMPTY"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLFULL->CMT_TOP_LOGIC_OUTS_L_B17_9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_PHYCTLFULL"
        },
        "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLREADY->CMT_TOP_LOGIC_OUTS_L_B17_8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_PHY_CONTROL_PHYCTLREADY"
        },
        "CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_C_WRCLK_FIFO->CMT_PHASER_IN_C_ICLKDIV": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_C_ICLKDIV",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_R_PHASER_IN_C_WRCLK_FIFO"
        },
        "CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_D_WRCLK_TOFIFO->CMT_PHASER_IN_D_ICLKDIV": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_D_ICLKDIV",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_R_PHASER_IN_D_WRCLK_TOFIFO"
        },
        "CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDCLK_FIFO->CMT_PHASER_OUT_C_OCLKDIV": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_C_OCLKDIV",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_R_PHASER_OUT_C_RDCLK_FIFO"
        },
        "CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO->CMT_PHASER_OUT_D_OCLKDIV": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_D_OCLKDIV",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_0->>CMT_L_TOP_UPPER_B_CLKINT_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_L_TOP_UPPER_B_CLKINT_2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_TOP_CLK0_0"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_2->CMT_PHASER_OUT_CA_SYSCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_CLK0_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_4->CMT_PHASER_IN_CA_SYSCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_SYSCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_CLK0_4"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_CLK0_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_8->CMT_PHASER_IN_DB_SYSCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_SYSCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_CLK0_8"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_10->CMT_PHY_CONTROL_PHYCLK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCLK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_CLK0_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_CLK1_0->>CMT_L_TOP_UPPER_B_CLKINT_3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_L_TOP_UPPER_B_CLKINT_3",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "CMT_TOP_CLK1_0"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_0->CMT_PHASER_UP_BUFMRCE_CE0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX0_0"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX0_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_DIVIDERST": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX0_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_3->CMT_PHASER_IN_CA_RSTDQSFIND": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX0_3"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX0_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX1_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX1_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX1_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX2_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX2_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX2_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX3_4->CMT_PHASER_IN_CA_RANKSEL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX3_4"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX3_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX3_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_9->CMT_PHY_CONTROL_PHYCTLWD0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX4_9"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_10->CMT_PHY_CONTROL_REFDLLLOCK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_REFDLLLOCK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX4_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_11->CMT_PHY_CONTROL_PHYCTLWD22": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD22",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX4_11"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX8_6->CMT_PHASER_OUT_DB_FINEENABLE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX8_6"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX8_7->CMT_PHASER_IN_DB_RSTDQSFIND": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX8_7"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX9_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX9_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_6->CMT_PHASER_OUT_DB_EDGEADV": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX9_6"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_4->CMT_PHASER_IN_CA_RST": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_RST",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX11_4"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_5->CMT_PHASER_OUT_DB_COUNTERREADEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX11_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_11->CMT_PHY_CONTROL_RESET": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_RESET",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX11_11"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX12_7->CMT_PHASER_IN_DB_COUNTERLOADVAL3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX12_7"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX13_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX13_3"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_9->CMT_PHY_CONTROL_PHYCTLWD3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX13_9"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_10->CMT_PHY_CONTROL_PHYCTLWD13": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD13",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX13_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_11->CMT_PHY_CONTROL_PHYCTLWD25": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD25",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX13_11"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX14_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX14_3"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX14_6"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_EDGEADV",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX14_7"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_9->CMT_PHY_CONTROL_PHYCTLWD5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX14_9"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_10->CMT_PHY_CONTROL_PHYCTLWD15": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD15",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX14_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_11->CMT_PHY_CONTROL_PHYCTLWD27": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD27",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX14_11"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_0->CMT_PHASER_REF_RST": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_REF_RST",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX15_0"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERREADEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX15_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX15_7"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_9->CMT_PHY_CONTROL_PHYCTLWD8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX15_9"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_10->CMT_PHY_CONTROL_PHYCTLWD18": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD18",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX15_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_11->CMT_PHY_CONTROL_PHYCTLWD30": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD30",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX15_11"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX16_0->CMT_PHASER_UP_BUFMRCE_CE1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX16_0"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX16_6->CMT_PHASER_OUT_DB_COARSEINC": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX16_6"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_2->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX17_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX17_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_6->CMT_PHASER_OUT_DB_ENCALIB0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_ENCALIB0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX17_6"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX18_2->CMT_PHASER_OUT_CA_ENCALIB0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_ENCALIB0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX18_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX18_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX18_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX19_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_4->CMT_PHASER_OUT_DB_DIVIDERST": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX19_4"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_6->CMT_PHASER_IN_DB_DIVIDERST": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX19_6"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_COUNTERLOADVAL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX19_7"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX20_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_9->CMT_PHY_CONTROL_PHYCTLWD1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX20_9"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_10->CMT_PHY_CONTROL_PHYCTLWD11": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD11",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX20_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_11->CMT_PHY_CONTROL_PHYCTLWD23": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD23",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX20_11"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX22_10->CMT_PHY_CONTROL_WRITECALIBENABLE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_WRITECALIBENABLE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX22_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX23_3->CMT_PHASER_IN_CA_COUNTERREADEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX23_3"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX23_7->CMT_PHASER_IN_DB_RANKSEL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX23_7"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_RST",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX27_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_5->CMT_PHASER_OUT_DB_COUNTERLOADEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX27_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_7->CMT_PHASER_IN_DB_COUNTERLOADVAL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX27_7"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX28_7->CMT_PHASER_IN_DB_COUNTERLOADVAL4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX28_7"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX29_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX29_3"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_10->CMT_PHY_CONTROL_READCALIBENABLE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_READCALIBENABLE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX29_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX30_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX30_3"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_FINEINC": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_FINEINC",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX30_6"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_9->CMT_PHY_CONTROL_PHYCTLWD6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX30_9"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_10->CMT_PHY_CONTROL_PHYCTLWD16": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD16",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX30_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_11->CMT_PHY_CONTROL_PHYCTLWD28": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD28",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX30_11"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX31_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_3->CMT_PHASER_IN_CA_COUNTERLOADEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX31_3"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_9->CMT_PHY_CONTROL_PHYCTLWD9": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD9",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX31_9"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_10->CMT_PHY_CONTROL_PHYCTLWD19": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD19",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX31_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_11->CMT_PHY_CONTROL_PHYCTLWD31": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD31",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX31_11"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX32_4->CMT_PHASER_IN_CA_FINEENABLE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX32_4"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX32_6->CMT_PHASER_OUT_DB_COARSEENABLE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX32_6"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_RANKSEL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX34_4"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX34_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_6->CMT_PHASER_OUT_DB_RST": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_RST",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX34_6"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX37_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX37_4"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX39_7->CMT_PHASER_IN_DB_RST": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_RST",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX39_7"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX41_2"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_4->CMT_PHASER_IN_CA_EDGEADV": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_EDGEADV",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX41_4"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX41_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_5->CMT_PHASER_OUT_DB_FINEINC": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_DB_FINEINC",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX43_5"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_7->CMT_PHASER_IN_DB_COUNTERLOADVAL2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX43_7"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_9->CMT_PHY_CONTROL_PLLLOCK": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PLLLOCK",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX43_9"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_11->CMT_PHY_CONTROL_PHYCTLWD21": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD21",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX43_11"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX44_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX44_3"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_COUNTERLOADVAL5": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX44_7"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_9->CMT_PHY_CONTROL_PHYCTLWD2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD2",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX44_9"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_10->CMT_PHY_CONTROL_PHYCTLWD12": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD12",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX44_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_11->CMT_PHY_CONTROL_PHYCTLWD24": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD24",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX44_11"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_0->CMT_PHASER_REF_PWRDWN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_REF_PWRDWN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX45_0"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX45_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX45_3"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERREADEN": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX45_6"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_9->CMT_PHY_CONTROL_PHYCTLWD4": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD4",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX45_9"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_10->CMT_PHY_CONTROL_PHYCTLWD14": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD14",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX45_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_11->CMT_PHY_CONTROL_PHYCTLWD26": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD26",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX45_11"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX46_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_6->CMT_PHASER_IN_DB_FINEENABLE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX46_6"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_9->CMT_PHY_CONTROL_PHYCTLWD7": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD7",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX46_9"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_10->CMT_PHY_CONTROL_PHYCTLWD17": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD17",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX46_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_11->CMT_PHY_CONTROL_PHYCTLWD29": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD29",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX46_11"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_FINEINC": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_OUT_CA_FINEINC",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX47_1"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_3->CMT_PHASER_IN_CA_FINEINC": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHASER_IN_CA_FINEINC",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX47_3"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_9->CMT_PHY_CONTROL_PHYCTLWD10": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD10",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX47_9"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_10->CMT_PHY_CONTROL_PHYCTLWD20": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD20",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX47_10"
        },
        "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_11->CMT_PHY_CONTROL_PHYCTLWRENABLE": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "dst_wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE",
            "is_directional": "1",
            "is_pass_transistor": 1,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": null,
                "in_cap": null,
                "res": "0.000"
            },
            "src_wire": "CMT_TOP_IMUX47_11"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>CMT_FREQ_PHASER_REFMUX_0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.114",
                    "0.126",
                    "0.334",
                    "0.352"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.114",
                    "0.126",
                    "0.334",
                    "0.352"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>CMT_FREQ_PHASER_REFMUX_1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.114",
                    "0.126",
                    "0.334",
                    "0.352"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.114",
                    "0.126",
                    "0.334",
                    "0.352"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>CMT_FREQ_PHASER_REFMUX_2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.114",
                    "0.126",
                    "0.334",
                    "0.352"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_PHASER_REFMUX_2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.114",
                    "0.126",
                    "0.334",
                    "0.352"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.157",
                    "0.173",
                    "0.454",
                    "0.478"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT0->>PLL_CLK_FREQBB_REBUFOUT0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": null,
                "res": null
            },
            "dst_wire": "PLL_CLK_FREQBB_REBUFOUT0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": null,
                "res": null
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT1->>PLL_CLK_FREQBB_REBUFOUT1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": null,
                "res": null
            },
            "dst_wire": "PLL_CLK_FREQBB_REBUFOUT1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": null,
                "res": null
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT2->>PLL_CLK_FREQBB_REBUFOUT2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": null,
                "res": null
            },
            "dst_wire": "PLL_CLK_FREQBB_REBUFOUT2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": null,
                "res": null
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2"
        },
        "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT3->>PLL_CLK_FREQBB_REBUFOUT3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": null,
                "res": null
            },
            "dst_wire": "PLL_CLK_FREQBB_REBUFOUT3",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": null,
                "res": null
            },
            "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3"
        },
        "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT0->>CMT_FREQ_BB_PREF_IN0": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_BB_PREF_IN0",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLL_CLK_FREQBB_REBUFOUT0"
        },
        "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT1->>CMT_FREQ_BB_PREF_IN1": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_BB_PREF_IN1",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLL_CLK_FREQBB_REBUFOUT1"
        },
        "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT2->>CMT_FREQ_BB_PREF_IN2": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_BB_PREF_IN2",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLL_CLK_FREQBB_REBUFOUT2"
        },
        "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT3->>CMT_FREQ_BB_PREF_IN3": {
            "can_invert": "0",
            "dst_to_src": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "dst_wire": "CMT_FREQ_BB_PREF_IN3",
            "is_directional": "1",
            "is_pass_transistor": 0,
            "is_pseudo": "0",
            "src_to_dst": {
                "delay": [
                    "0.000",
                    "0.000",
                    "0.000",
                    "0.000"
                ],
                "in_cap": "0.000",
                "res": "0.0"
            },
            "src_wire": "PLL_CLK_FREQBB_REBUFOUT3"
        }
    },
    "sites": [
        {
            "name": "X0Y0",
            "prefix": "PHASER_IN_PHY",
            "site_pins": {
                "BURSTPENDING": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_BURSTPENDING"
                },
                "BURSTPENDINGPHY": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY"
                },
                "COUNTERLOADEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_COUNTERLOADEN"
                },
                "COUNTERLOADVAL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0"
                },
                "COUNTERLOADVAL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1"
                },
                "COUNTERLOADVAL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2"
                },
                "COUNTERLOADVAL3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3"
                },
                "COUNTERLOADVAL4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4"
                },
                "COUNTERLOADVAL5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5"
                },
                "COUNTERREADEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_COUNTERREADEN"
                },
                "COUNTERREADVAL0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_COUNTERREADVAL0"
                },
                "COUNTERREADVAL1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_COUNTERREADVAL1"
                },
                "COUNTERREADVAL2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2"
                },
                "COUNTERREADVAL3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3"
                },
                "COUNTERREADVAL4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4"
                },
                "COUNTERREADVAL5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5"
                },
                "DIVIDERST": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_DIVIDERST"
                },
                "DQSFOUND": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_DQSFOUND"
                },
                "DQSOUTOFRANGE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE"
                },
                "EDGEADV": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_EDGEADV"
                },
                "ENCALIB0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_ENCALIB0"
                },
                "ENCALIB1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_ENCALIB1"
                },
                "ENCALIBPHY0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_ENCALIBPHY0"
                },
                "ENCALIBPHY1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_ENCALIBPHY1"
                },
                "ENSTG1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_ENSTG1"
                },
                "ENSTG1ADJUSTB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB"
                },
                "FINEENABLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_FINEENABLE"
                },
                "FINEINC": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_FINEINC"
                },
                "FINEOVERFLOW": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_FINEOVERFLOW"
                },
                "FREQREFCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_FREQREFCLK"
                },
                "ICLK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_ICLK"
                },
                "ICLKDIV": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_ICLKDIV"
                },
                "ISERDESRST": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_ISERDESRST"
                },
                "MEMREFCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_MEMREFCLK"
                },
                "PHASELOCKED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_PHASELOCKED"
                },
                "PHASEREFCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_PHASEREFCLK"
                },
                "RANKSEL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_RANKSEL0"
                },
                "RANKSEL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_RANKSEL1"
                },
                "RANKSELPHY0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_RANKSELPHY0"
                },
                "RANKSELPHY1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_RANKSELPHY1"
                },
                "RCLK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_RCLK"
                },
                "RST": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_RST"
                },
                "RSTDQSFIND": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_RSTDQSFIND"
                },
                "SCANCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_SCANCLK"
                },
                "SCANENB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_SCANENB"
                },
                "SCANIN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_SCANIN"
                },
                "SCANMODEB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_SCANMODEB"
                },
                "SCANOUT": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_SCANOUT"
                },
                "SELCALORSTG1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_SELCALORSTG1"
                },
                "STG1INCDEC": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_STG1INCDEC"
                },
                "STG1LOAD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_STG1LOAD"
                },
                "STG1OVERFLOW": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_STG1OVERFLOW"
                },
                "STG1READ": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_STG1READ"
                },
                "STG1REGL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_STG1REGL0"
                },
                "STG1REGL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_STG1REGL1"
                },
                "STG1REGL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_STG1REGL2"
                },
                "STG1REGL3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_STG1REGL3"
                },
                "STG1REGL4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_STG1REGL4"
                },
                "STG1REGL5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_STG1REGL5"
                },
                "STG1REGL6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_STG1REGL6"
                },
                "STG1REGL7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_STG1REGL7"
                },
                "STG1REGL8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_STG1REGL8"
                },
                "STG1REGR0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_STG1REGR0"
                },
                "STG1REGR1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_STG1REGR1"
                },
                "STG1REGR2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_STG1REGR2"
                },
                "STG1REGR3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_STG1REGR3"
                },
                "STG1REGR4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_STG1REGR4"
                },
                "STG1REGR5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_STG1REGR5"
                },
                "STG1REGR6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_STG1REGR6"
                },
                "STG1REGR7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_STG1REGR7"
                },
                "STG1REGR8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_STG1REGR8"
                },
                "SYNCIN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_SYNCIN"
                },
                "SYSCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_SYSCLK"
                },
                "TESTIN0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN0"
                },
                "TESTIN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN1"
                },
                "TESTIN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN2"
                },
                "TESTIN3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN3"
                },
                "TESTIN4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN4"
                },
                "TESTIN5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN5"
                },
                "TESTIN6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN6"
                },
                "TESTIN7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN7"
                },
                "TESTIN8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN8"
                },
                "TESTIN9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN9"
                },
                "TESTIN10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN10"
                },
                "TESTIN11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN11"
                },
                "TESTIN12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN12"
                },
                "TESTIN13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_CA_TESTIN13"
                },
                "TESTOUT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_TESTOUT0"
                },
                "TESTOUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_TESTOUT1"
                },
                "TESTOUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_TESTOUT2"
                },
                "TESTOUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_TESTOUT3"
                },
                "WRENABLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_CA_WRENABLE"
                }
            },
            "type": "PHASER_IN_PHY",
            "x_coord": 0,
            "y_coord": 0
        },
        {
            "name": "X0Y0",
            "prefix": "PHASER_OUT_PHY",
            "site_pins": {
                "BURSTPENDING": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_BURSTPENDING"
                },
                "BURSTPENDINGPHY": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY"
                },
                "COARSEENABLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_COARSEENABLE"
                },
                "COARSEINC": {
                    "cap": "0.000",
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_COARSEINC"
                },
                "COARSEOVERFLOW": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW"
                },
                "COUNTERLOADEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN"
                },
                "COUNTERLOADVAL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0"
                },
                "COUNTERLOADVAL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1"
                },
                "COUNTERLOADVAL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2"
                },
                "COUNTERLOADVAL3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3"
                },
                "COUNTERLOADVAL4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4"
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                "COUNTERLOADVAL5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5"
                },
                "COUNTERLOADVAL6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6"
                },
                "COUNTERLOADVAL7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7"
                },
                "COUNTERLOADVAL8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8"
                },
                "COUNTERREADEN": {
                    "cap": "0.000",
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_COUNTERREADEN"
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                "COUNTERREADVAL0": {
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0"
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                "COUNTERREADVAL1": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1"
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                "COUNTERREADVAL2": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2"
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                "COUNTERREADVAL3": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3"
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                "COUNTERREADVAL4": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4"
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                "COUNTERREADVAL5": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5"
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                "COUNTERREADVAL6": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6"
                },
                "COUNTERREADVAL7": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7"
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                "COUNTERREADVAL8": {
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                        "0.000",
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                        "0.000"
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                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8"
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                "CTSBUS0": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_CTSBUS0"
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                "CTSBUS1": {
                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_CTSBUS1"
                },
                "DIVIDERST": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_DIVIDERST"
                },
                "DQSBUS0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
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                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_DQSBUS0"
                },
                "DQSBUS1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_DQSBUS1"
                },
                "DTSBUS0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_DTSBUS0"
                },
                "DTSBUS1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_DTSBUS1"
                },
                "EDGEADV": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_EDGEADV"
                },
                "ENCALIB0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_ENCALIB0"
                },
                "ENCALIB1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_ENCALIB1"
                },
                "ENCALIBPHY0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0"
                },
                "ENCALIBPHY1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1"
                },
                "FINEENABLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_FINEENABLE"
                },
                "FINEINC": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_FINEINC"
                },
                "FINEOVERFLOW": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW"
                },
                "FREQREFCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_FREQREFCLK"
                },
                "MEMREFCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_MEMREFCLK"
                },
                "OCLK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_OCLK"
                },
                "OCLKDELAYED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_OCLKDELAYED"
                },
                "OCLKDIV": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_OCLKDIV"
                },
                "OSERDESRST": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_OSERDESRST"
                },
                "PHASEREFCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_PHASEREFCLK"
                },
                "RDENABLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_RDENABLE"
                },
                "RST": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_RST"
                },
                "SCANCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_SCANCLK"
                },
                "SCANENB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_SCANENB"
                },
                "SCANIN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_SCANIN"
                },
                "SCANMODEB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_SCANMODEB"
                },
                "SCANOUT": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_SCANOUT"
                },
                "SELFINEOCLKDELAY": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY"
                },
                "SYNCIN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_SYNCIN"
                },
                "SYSCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_SYSCLK"
                },
                "TESTIN0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN0"
                },
                "TESTIN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN1"
                },
                "TESTIN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN2"
                },
                "TESTIN3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN3"
                },
                "TESTIN4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN4"
                },
                "TESTIN5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN5"
                },
                "TESTIN6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN6"
                },
                "TESTIN7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN7"
                },
                "TESTIN8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN8"
                },
                "TESTIN9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN9"
                },
                "TESTIN10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN10"
                },
                "TESTIN11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN11"
                },
                "TESTIN12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN12"
                },
                "TESTIN13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN13"
                },
                "TESTIN14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN14"
                },
                "TESTIN15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_CA_TESTIN15"
                },
                "TESTOUT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_TESTOUT0"
                },
                "TESTOUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_TESTOUT1"
                },
                "TESTOUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_TESTOUT2"
                },
                "TESTOUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_CA_TESTOUT3"
                }
            },
            "type": "PHASER_OUT_PHY",
            "x_coord": 0,
            "y_coord": 0
        },
        {
            "name": "X0Y0",
            "prefix": "PHASER_REF",
            "site_pins": {
                "CLKIN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_REF_CLKIN"
                },
                "CLKOUT": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_REF_CLKOUT"
                },
                "LOCKED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_REF_LOCKED"
                },
                "PWRDWN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_REF_PWRDWN"
                },
                "RST": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_REF_RST"
                },
                "TESTIN0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_REF_TESTIN0"
                },
                "TESTIN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_REF_TESTIN1"
                },
                "TESTIN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_REF_TESTIN2"
                },
                "TESTIN3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_REF_TESTIN3"
                },
                "TESTIN4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_REF_TESTIN4"
                },
                "TESTIN5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_REF_TESTIN5"
                },
                "TESTIN6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_REF_TESTIN6"
                },
                "TESTIN7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_REF_TESTIN7"
                },
                "TESTOUT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_REF_TESTOUT0"
                },
                "TESTOUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_REF_TESTOUT1"
                },
                "TESTOUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_REF_TESTOUT2"
                },
                "TESTOUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_REF_TESTOUT3"
                },
                "TESTOUT4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_REF_TESTOUT4"
                },
                "TESTOUT5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_REF_TESTOUT5"
                },
                "TESTOUT6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_REF_TESTOUT6"
                },
                "TESTOUT7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_REF_TESTOUT7"
                },
                "TMUXOUT": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_REF_TMUXOUT"
                }
            },
            "type": "PHASER_REF",
            "x_coord": 0,
            "y_coord": 0
        },
        {
            "name": "X0Y0",
            "prefix": "PHY_CONTROL",
            "site_pins": {
                "AUXOUTPUT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_AUXOUTPUT0"
                },
                "AUXOUTPUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_AUXOUTPUT1"
                },
                "AUXOUTPUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_AUXOUTPUT2"
                },
                "AUXOUTPUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_AUXOUTPUT3"
                },
                "INBURSTPENDING0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_INBURSTPENDING0"
                },
                "INBURSTPENDING1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_INBURSTPENDING1"
                },
                "INBURSTPENDING2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_INBURSTPENDING2"
                },
                "INBURSTPENDING3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_INBURSTPENDING3"
                },
                "INRANKA0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_INRANKA0"
                },
                "INRANKA1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_INRANKA1"
                },
                "INRANKB0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_INRANKB0"
                },
                "INRANKB1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_INRANKB1"
                },
                "INRANKC0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_INRANKC0"
                },
                "INRANKC1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_INRANKC1"
                },
                "INRANKD0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_INRANKD0"
                },
                "INRANKD1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_INRANKD1"
                },
                "MEMREFCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_MEMREFCLK"
                },
                "OUTBURSTPENDING0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0"
                },
                "OUTBURSTPENDING1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1"
                },
                "OUTBURSTPENDING2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2"
                },
                "OUTBURSTPENDING3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3"
                },
                "PCENABLECALIB0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_PCENABLECALIB0"
                },
                "PCENABLECALIB1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_PCENABLECALIB1"
                },
                "PHYCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCLK"
                },
                "PHYCTLALMOSTFULL": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL"
                },
                "PHYCTLEMPTY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_PHYCTLEMPTY"
                },
                "PHYCTLFULL": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_PHYCTLFULL"
                },
                "PHYCTLMSTREMPTY": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY"
                },
                "PHYCTLREADY": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_PHYCTLREADY"
                },
                "PHYCTLWD0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD0"
                },
                "PHYCTLWD1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD1"
                },
                "PHYCTLWD2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD2"
                },
                "PHYCTLWD3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD3"
                },
                "PHYCTLWD4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD4"
                },
                "PHYCTLWD5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD5"
                },
                "PHYCTLWD6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD6"
                },
                "PHYCTLWD7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD7"
                },
                "PHYCTLWD8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD8"
                },
                "PHYCTLWD9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD9"
                },
                "PHYCTLWD10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD10"
                },
                "PHYCTLWD11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD11"
                },
                "PHYCTLWD12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD12"
                },
                "PHYCTLWD13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD13"
                },
                "PHYCTLWD14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD14"
                },
                "PHYCTLWD15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD15"
                },
                "PHYCTLWD16": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD16"
                },
                "PHYCTLWD17": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD17"
                },
                "PHYCTLWD18": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD18"
                },
                "PHYCTLWD19": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD19"
                },
                "PHYCTLWD20": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD20"
                },
                "PHYCTLWD21": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD21"
                },
                "PHYCTLWD22": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD22"
                },
                "PHYCTLWD23": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD23"
                },
                "PHYCTLWD24": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD24"
                },
                "PHYCTLWD25": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD25"
                },
                "PHYCTLWD26": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD26"
                },
                "PHYCTLWD27": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD27"
                },
                "PHYCTLWD28": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD28"
                },
                "PHYCTLWD29": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD29"
                },
                "PHYCTLWD30": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD30"
                },
                "PHYCTLWD31": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWD31"
                },
                "PHYCTLWRENABLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE"
                },
                "PLLLOCK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_PLLLOCK"
                },
                "READCALIBENABLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_READCALIBENABLE"
                },
                "REFDLLLOCK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_REFDLLLOCK"
                },
                "RESET": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_RESET"
                },
                "SCANENABLEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_SCANENABLEN"
                },
                "SYNCIN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_SYNCIN"
                },
                "TESTINPUT0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT0"
                },
                "TESTINPUT1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT1"
                },
                "TESTINPUT2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT2"
                },
                "TESTINPUT3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT3"
                },
                "TESTINPUT4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT4"
                },
                "TESTINPUT5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT5"
                },
                "TESTINPUT6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT6"
                },
                "TESTINPUT7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT7"
                },
                "TESTINPUT8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT8"
                },
                "TESTINPUT9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT9"
                },
                "TESTINPUT10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT10"
                },
                "TESTINPUT11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT11"
                },
                "TESTINPUT12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT12"
                },
                "TESTINPUT13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT13"
                },
                "TESTINPUT14": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT14"
                },
                "TESTINPUT15": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTINPUT15"
                },
                "TESTOUTPUT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT0"
                },
                "TESTOUTPUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT1"
                },
                "TESTOUTPUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT2"
                },
                "TESTOUTPUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT3"
                },
                "TESTOUTPUT4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT4"
                },
                "TESTOUTPUT5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT5"
                },
                "TESTOUTPUT6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT6"
                },
                "TESTOUTPUT7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT7"
                },
                "TESTOUTPUT8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT8"
                },
                "TESTOUTPUT9": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT9"
                },
                "TESTOUTPUT10": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT10"
                },
                "TESTOUTPUT11": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT11"
                },
                "TESTOUTPUT12": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT12"
                },
                "TESTOUTPUT13": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT13"
                },
                "TESTOUTPUT14": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT14"
                },
                "TESTOUTPUT15": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHY_CONTROL_TESTOUTPUT15"
                },
                "TESTSELECT0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTSELECT0"
                },
                "TESTSELECT1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTSELECT1"
                },
                "TESTSELECT2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_TESTSELECT2"
                },
                "WRITECALIBENABLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHY_CONTROL_WRITECALIBENABLE"
                }
            },
            "type": "PHY_CONTROL",
            "x_coord": 0,
            "y_coord": 0
        },
        {
            "name": "X0Y1",
            "prefix": "PHASER_IN_PHY",
            "site_pins": {
                "BURSTPENDING": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_BURSTPENDING"
                },
                "BURSTPENDINGPHY": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY"
                },
                "COUNTERLOADEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_COUNTERLOADEN"
                },
                "COUNTERLOADVAL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0"
                },
                "COUNTERLOADVAL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1"
                },
                "COUNTERLOADVAL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2"
                },
                "COUNTERLOADVAL3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3"
                },
                "COUNTERLOADVAL4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4"
                },
                "COUNTERLOADVAL5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5"
                },
                "COUNTERREADEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_COUNTERREADEN"
                },
                "COUNTERREADVAL0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0"
                },
                "COUNTERREADVAL1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1"
                },
                "COUNTERREADVAL2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2"
                },
                "COUNTERREADVAL3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3"
                },
                "COUNTERREADVAL4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4"
                },
                "COUNTERREADVAL5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5"
                },
                "DIVIDERST": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_DIVIDERST"
                },
                "DQSFOUND": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_DQSFOUND"
                },
                "DQSOUTOFRANGE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE"
                },
                "EDGEADV": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_EDGEADV"
                },
                "ENCALIB0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_ENCALIB0"
                },
                "ENCALIB1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_ENCALIB1"
                },
                "ENCALIBPHY0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_ENCALIBPHY0"
                },
                "ENCALIBPHY1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_ENCALIBPHY1"
                },
                "ENSTG1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_ENSTG1"
                },
                "ENSTG1ADJUSTB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB"
                },
                "FINEENABLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_FINEENABLE"
                },
                "FINEINC": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_FINEINC"
                },
                "FINEOVERFLOW": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_FINEOVERFLOW"
                },
                "FREQREFCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_FREQREFCLK"
                },
                "ICLK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_ICLK"
                },
                "ICLKDIV": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_ICLKDIV"
                },
                "ISERDESRST": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_ISERDESRST"
                },
                "MEMREFCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_MEMREFCLK"
                },
                "PHASELOCKED": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_PHASELOCKED"
                },
                "PHASEREFCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_PHASEREFCLK"
                },
                "RANKSEL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_RANKSEL0"
                },
                "RANKSEL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_RANKSEL1"
                },
                "RANKSELPHY0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_RANKSELPHY0"
                },
                "RANKSELPHY1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_RANKSELPHY1"
                },
                "RCLK": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_RCLK"
                },
                "RST": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_RST"
                },
                "RSTDQSFIND": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_RSTDQSFIND"
                },
                "SCANCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_SCANCLK"
                },
                "SCANENB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_SCANENB"
                },
                "SCANIN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_SCANIN"
                },
                "SCANMODEB": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_SCANMODEB"
                },
                "SCANOUT": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_SCANOUT"
                },
                "SELCALORSTG1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_SELCALORSTG1"
                },
                "STG1INCDEC": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_STG1INCDEC"
                },
                "STG1LOAD": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_STG1LOAD"
                },
                "STG1OVERFLOW": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_STG1OVERFLOW"
                },
                "STG1READ": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_STG1READ"
                },
                "STG1REGL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_STG1REGL0"
                },
                "STG1REGL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_STG1REGL1"
                },
                "STG1REGL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_STG1REGL2"
                },
                "STG1REGL3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_STG1REGL3"
                },
                "STG1REGL4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_STG1REGL4"
                },
                "STG1REGL5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_STG1REGL5"
                },
                "STG1REGL6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_STG1REGL6"
                },
                "STG1REGL7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_STG1REGL7"
                },
                "STG1REGL8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_STG1REGL8"
                },
                "STG1REGR0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_STG1REGR0"
                },
                "STG1REGR1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_STG1REGR1"
                },
                "STG1REGR2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_STG1REGR2"
                },
                "STG1REGR3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_STG1REGR3"
                },
                "STG1REGR4": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_STG1REGR4"
                },
                "STG1REGR5": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_STG1REGR5"
                },
                "STG1REGR6": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_STG1REGR6"
                },
                "STG1REGR7": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_STG1REGR7"
                },
                "STG1REGR8": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_STG1REGR8"
                },
                "SYNCIN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_SYNCIN"
                },
                "SYSCLK": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_SYSCLK"
                },
                "TESTIN0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN0"
                },
                "TESTIN1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN1"
                },
                "TESTIN2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN2"
                },
                "TESTIN3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN3"
                },
                "TESTIN4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN4"
                },
                "TESTIN5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN5"
                },
                "TESTIN6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN6"
                },
                "TESTIN7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN7"
                },
                "TESTIN8": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN8"
                },
                "TESTIN9": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN9"
                },
                "TESTIN10": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN10"
                },
                "TESTIN11": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN11"
                },
                "TESTIN12": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN12"
                },
                "TESTIN13": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_IN_DB_TESTIN13"
                },
                "TESTOUT0": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_TESTOUT0"
                },
                "TESTOUT1": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_TESTOUT1"
                },
                "TESTOUT2": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_TESTOUT2"
                },
                "TESTOUT3": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_TESTOUT3"
                },
                "WRENABLE": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_IN_DB_WRENABLE"
                }
            },
            "type": "PHASER_IN_PHY",
            "x_coord": 0,
            "y_coord": 1
        },
        {
            "name": "X0Y1",
            "prefix": "PHASER_OUT_PHY",
            "site_pins": {
                "BURSTPENDING": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_BURSTPENDING"
                },
                "BURSTPENDINGPHY": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY"
                },
                "COARSEENABLE": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_COARSEENABLE"
                },
                "COARSEINC": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_COARSEINC"
                },
                "COARSEOVERFLOW": {
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "res": "0.0",
                    "wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW"
                },
                "COUNTERLOADEN": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN"
                },
                "COUNTERLOADVAL0": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0"
                },
                "COUNTERLOADVAL1": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1"
                },
                "COUNTERLOADVAL2": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2"
                },
                "COUNTERLOADVAL3": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3"
                },
                "COUNTERLOADVAL4": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4"
                },
                "COUNTERLOADVAL5": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5"
                },
                "COUNTERLOADVAL6": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6"
                },
                "COUNTERLOADVAL7": {
                    "cap": "0.000",
                    "delay": [
                        "0.000",
                        "0.000",
                        "0.000",
                        "0.000"
                    ],
                    "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7"
                },
                "COUNTERLOADVAL8": {
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                    "delay": [
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                        "0.000",
                        "0.000",
                        "0.000"
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                    "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8"
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                    "delay": [
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                        "0.000",
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                    "wire": "CMT_PHASER_OUT_DB_COUNTERREADEN"
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                "COUNTERREADVAL0": {
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                        "0.000",
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                    "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0"
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                "COUNTERREADVAL1": {
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                    "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1"
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                "COUNTERREADVAL2": {
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                "COUNTERREADVAL3": {
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                    "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3"
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                "COUNTERREADVAL4": {
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                "COUNTERREADVAL5": {
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                    "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5"
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                "COUNTERREADVAL6": {
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                    "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6"
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                "COUNTERREADVAL7": {
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                "COUNTERREADVAL8": {
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                "CTSBUS1": {
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                "DQSBUS1": {
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                "DTSBUS1": {
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                        "0.000"
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            },
            "type": "PHASER_OUT_PHY",
            "x_coord": 0,
            "y_coord": 1
        }
    ],
    "tile_type": "CMT_TOP_L_UPPER_B",
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        "CMT_PHASER_C_ICLKDIV_TOIOI": null,
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        "CMT_PHASER_C_OCLK90_TOIOI": null,
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        "CMT_PHASER_IN_CA_BURSTPENDINGPHY": null,
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        "CMT_PHASER_IN_CA_COUNTERLOADVAL4": null,
        "CMT_PHASER_IN_CA_COUNTERLOADVAL5": null,
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        "CMT_PHASER_IN_CA_DQSOUTOFRANGE": null,
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        "CMT_PHASER_IN_CA_ENCALIBPHY1": null,
        "CMT_PHASER_IN_CA_ENSTG1": null,
        "CMT_PHASER_IN_CA_ENSTG1ADJUSTB": null,
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        "CMT_PHASER_IN_CA_FINEINC": null,
        "CMT_PHASER_IN_CA_FINEOVERFLOW": null,
        "CMT_PHASER_IN_CA_FREQREFCLK": null,
        "CMT_PHASER_IN_CA_ICLK": null,
        "CMT_PHASER_IN_CA_ICLKDIV": null,
        "CMT_PHASER_IN_CA_ISERDESRST": null,
        "CMT_PHASER_IN_CA_MEMREFCLK": null,
        "CMT_PHASER_IN_CA_PHASELOCKED": null,
        "CMT_PHASER_IN_CA_PHASEREFCLK": null,
        "CMT_PHASER_IN_CA_RANKSEL0": null,
        "CMT_PHASER_IN_CA_RANKSEL1": null,
        "CMT_PHASER_IN_CA_RANKSELPHY0": null,
        "CMT_PHASER_IN_CA_RANKSELPHY1": null,
        "CMT_PHASER_IN_CA_RCLK": null,
        "CMT_PHASER_IN_CA_RST": null,
        "CMT_PHASER_IN_CA_RSTDQSFIND": null,
        "CMT_PHASER_IN_CA_SCANCLK": null,
        "CMT_PHASER_IN_CA_SCANENB": null,
        "CMT_PHASER_IN_CA_SCANIN": null,
        "CMT_PHASER_IN_CA_SCANMODEB": null,
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        "CMT_PHASER_IN_CA_SELCALORSTG1": null,
        "CMT_PHASER_IN_CA_STG1INCDEC": null,
        "CMT_PHASER_IN_CA_STG1LOAD": null,
        "CMT_PHASER_IN_CA_STG1OVERFLOW": null,
        "CMT_PHASER_IN_CA_STG1READ": null,
        "CMT_PHASER_IN_CA_STG1REGL0": null,
        "CMT_PHASER_IN_CA_STG1REGL1": null,
        "CMT_PHASER_IN_CA_STG1REGL2": null,
        "CMT_PHASER_IN_CA_STG1REGL3": null,
        "CMT_PHASER_IN_CA_STG1REGL4": null,
        "CMT_PHASER_IN_CA_STG1REGL5": null,
        "CMT_PHASER_IN_CA_STG1REGL6": null,
        "CMT_PHASER_IN_CA_STG1REGL7": null,
        "CMT_PHASER_IN_CA_STG1REGL8": null,
        "CMT_PHASER_IN_CA_STG1REGR0": null,
        "CMT_PHASER_IN_CA_STG1REGR1": null,
        "CMT_PHASER_IN_CA_STG1REGR2": null,
        "CMT_PHASER_IN_CA_STG1REGR3": null,
        "CMT_PHASER_IN_CA_STG1REGR4": null,
        "CMT_PHASER_IN_CA_STG1REGR5": null,
        "CMT_PHASER_IN_CA_STG1REGR6": null,
        "CMT_PHASER_IN_CA_STG1REGR7": null,
        "CMT_PHASER_IN_CA_STG1REGR8": null,
        "CMT_PHASER_IN_CA_SYNCIN": null,
        "CMT_PHASER_IN_CA_SYSCLK": null,
        "CMT_PHASER_IN_CA_TESTIN0": null,
        "CMT_PHASER_IN_CA_TESTIN1": null,
        "CMT_PHASER_IN_CA_TESTIN2": null,
        "CMT_PHASER_IN_CA_TESTIN3": null,
        "CMT_PHASER_IN_CA_TESTIN4": null,
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        "CMT_PHASER_OUT_DB_COUNTERREADVAL6": null,
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        "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": null,
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        "CMT_PHASER_OUT_DB_TESTIN6": null,
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        "CMT_PHASER_OUT_DB_TESTIN14": null,
        "CMT_PHASER_OUT_DB_TESTIN15": null,
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        "CMT_PHASER_OUT_D_OCLK1X_90": null,
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        "CMT_PHASER_REF_LOCKED": null,
        "CMT_PHASER_REF_PWRDWN": null,
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        "CMT_PHASER_REF_TESTIN0": null,
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        "CMT_PHASER_REF_TESTIN3": null,
        "CMT_PHASER_REF_TESTIN4": null,
        "CMT_PHASER_REF_TESTIN5": null,
        "CMT_PHASER_REF_TESTIN6": null,
        "CMT_PHASER_REF_TESTIN7": null,
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        "CMT_PHASER_REF_TESTOUT1": null,
        "CMT_PHASER_REF_TESTOUT2": null,
        "CMT_PHASER_REF_TESTOUT3": null,
        "CMT_PHASER_REF_TESTOUT4": null,
        "CMT_PHASER_REF_TESTOUT5": null,
        "CMT_PHASER_REF_TESTOUT6": null,
        "CMT_PHASER_REF_TESTOUT7": null,
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        "CMT_PHASER_UP_BUFMRCE_CE0": null,
        "CMT_PHASER_UP_BUFMRCE_CE1": null,
        "CMT_PHASER_UP_DQS_TO_PHASER_C": null,
        "CMT_PHASER_UP_DQS_TO_PHASER_D": null,
        "CMT_PHASER_UP_PHASERREF0": null,
        "CMT_PHASER_UP_PHASERREF1": null,
        "CMT_PHASER_UP_PHASERREF_ABOVE0": null,
        "CMT_PHASER_UP_PHASERREF_ABOVE1": null,
        "CMT_PHASER_UP_PHASERREF_BELOW0": null,
        "CMT_PHASER_UP_PHASERREF_BELOW1": null,
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            "cap": "0.208",
            "res": "0.000"
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        "CMT_PHY_CONTROL_AUXOUTPUT1": {
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            "res": "0.000"
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        "CMT_PHY_CONTROL_AUXOUTPUT2": {
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        "CMT_PHY_CONTROL_AUXOUTPUT3": {
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            "res": "0.000"
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        "CMT_PHY_CONTROL_IBURSTPENDING0": null,
        "CMT_PHY_CONTROL_IBURSTPENDING1": null,
        "CMT_PHY_CONTROL_IBURSTPENDING2": null,
        "CMT_PHY_CONTROL_IBURSTPENDING3": null,
        "CMT_PHY_CONTROL_INBURSTPENDING0": {
            "cap": "0.623",
            "res": "0.039"
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        "CMT_PHY_CONTROL_INBURSTPENDING1": {
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            "res": "0.039"
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        "CMT_PHY_CONTROL_INBURSTPENDING2": {
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        "CMT_PHY_CONTROL_INBURSTPENDING3": {
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            "res": "0.039"
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        "CMT_PHY_CONTROL_INRANKA0": {
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            "res": "0.036"
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        "CMT_PHY_CONTROL_INRANKA1": {
            "cap": "1.039",
            "res": "0.036"
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        "CMT_PHY_CONTROL_INRANKB0": {
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            "res": "0.036"
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        "CMT_PHY_CONTROL_INRANKB1": {
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            "res": "0.036"
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        "CMT_PHY_CONTROL_INRANKC0": {
            "cap": "1.039",
            "res": "0.036"
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        "CMT_PHY_CONTROL_INRANKC1": {
            "cap": "1.039",
            "res": "0.036"
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        "CMT_PHY_CONTROL_INRANKD0": {
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            "res": "0.036"
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        "CMT_PHY_CONTROL_INRANKD1": {
            "cap": "1.039",
            "res": "0.036"
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        "CMT_PHY_CONTROL_IRANKA0": null,
        "CMT_PHY_CONTROL_IRANKA1": null,
        "CMT_PHY_CONTROL_IRANKB0": null,
        "CMT_PHY_CONTROL_IRANKB1": null,
        "CMT_PHY_CONTROL_IRANKC0": null,
        "CMT_PHY_CONTROL_IRANKC1": null,
        "CMT_PHY_CONTROL_IRANKD0": null,
        "CMT_PHY_CONTROL_IRANKD1": null,
        "CMT_PHY_CONTROL_MEMREFCLK": {
            "cap": "5.507",
            "res": "0.000"
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        "CMT_PHY_CONTROL_OBURSTPENDING0": null,
        "CMT_PHY_CONTROL_OBURSTPENDING1": null,
        "CMT_PHY_CONTROL_OBURSTPENDING2": null,
        "CMT_PHY_CONTROL_OBURSTPENDING3": null,
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            "res": "0.039"
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        "CMT_PHY_CONTROL_OUTBURSTPENDING1": {
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        "CMT_PHY_CONTROL_OUTBURSTPENDING2": {
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            "res": "0.039"
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        "CMT_PHY_CONTROL_OUTBURSTPENDING3": {
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            "res": "0.036"
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