{ "pips": { "PCIE_TOP.PCIE_IMUX0_L_0->PCIE_TOP_TRNTDLLPDATA19": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA19", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX0_L_0" }, "PCIE_TOP.PCIE_IMUX0_L_1->PCIE_TOP_TRNTDLLPDATA23": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA23", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX0_L_1" }, "PCIE_TOP.PCIE_IMUX0_L_2->PCIE_TOP_TRNTDLLPDATA27": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA27", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, 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null, "res": "0.000" }, "src_wire": "PCIE_IMUX4_L_3" }, "PCIE_TOP.PCIE_IMUX4_L_4->PCIE_TOP_CFGERRTLPCPLHEADER42": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER42", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX4_L_4" }, "PCIE_TOP.PCIE_IMUX4_R_0->PCIE_TOP_MIMRXRDATA52": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_MIMRXRDATA52", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX4_R_0" }, "PCIE_TOP.PCIE_IMUX4_R_1->PCIE_TOP_MIMRXRDATA48": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_MIMRXRDATA48", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { 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"delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX4_R_4" }, "PCIE_TOP.PCIE_IMUX5_L_0->PCIE_TOP_CFGERRTLPCPLHEADER27": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER27", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX5_L_0" }, "PCIE_TOP.PCIE_IMUX5_L_1->PCIE_TOP_CFGERRTLPCPLHEADER31": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER31", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX5_L_1" }, "PCIE_TOP.PCIE_IMUX5_L_2->PCIE_TOP_CFGERRTLPCPLHEADER35": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER35", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX5_L_2" }, "PCIE_TOP.PCIE_IMUX5_L_3->PCIE_TOP_CFGERRTLPCPLHEADER39": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER39", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX5_L_3" }, "PCIE_TOP.PCIE_IMUX5_L_4->PCIE_TOP_CFGERRTLPCPLHEADER43": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER43", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX5_L_4" }, "PCIE_TOP.PCIE_IMUX5_R_0->PCIE_TOP_MIMRXRDATA53": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": 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"dst_wire": "PCIE_TOP_MIMRXRDATA41", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX5_R_3" }, "PCIE_TOP.PCIE_IMUX5_R_4->PCIE_TOP_TRNTD25": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD25", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX5_R_4" }, "PCIE_TOP.PCIE_IMUX6_L_0->PCIE_TOP_CFGERRTLPCPLHEADER28": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER28", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX6_L_0" }, "PCIE_TOP.PCIE_IMUX6_L_1->PCIE_TOP_CFGERRTLPCPLHEADER32": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER32", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX6_L_1" }, "PCIE_TOP.PCIE_IMUX6_L_2->PCIE_TOP_CFGERRTLPCPLHEADER36": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER36", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX6_L_2" }, "PCIE_TOP.PCIE_IMUX6_L_3->PCIE_TOP_CFGERRTLPCPLHEADER40": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER40", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX6_L_3" }, "PCIE_TOP.PCIE_IMUX6_L_4->PCIE_TOP_CFGERRTLPCPLHEADER44": { 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"PCIE_TOP.PCIE_IMUX6_R_2->PCIE_TOP_MIMRXRDATA46": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_MIMRXRDATA46", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX6_R_2" }, "PCIE_TOP.PCIE_IMUX6_R_3->PCIE_TOP_MIMRXRDATA42": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_MIMRXRDATA42", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX6_R_3" }, "PCIE_TOP.PCIE_IMUX6_R_4->PCIE_TOP_TRNTD26": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD26", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX6_R_4" }, "PCIE_TOP.PCIE_IMUX7_L_0->PCIE_TOP_CFGERRTLPCPLHEADER29": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER29", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX7_L_0" }, "PCIE_TOP.PCIE_IMUX7_L_1->PCIE_TOP_CFGERRTLPCPLHEADER33": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER33", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX7_L_1" }, "PCIE_TOP.PCIE_IMUX7_L_2->PCIE_TOP_CFGERRTLPCPLHEADER37": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER37", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX7_L_2" }, "PCIE_TOP.PCIE_IMUX7_L_3->PCIE_TOP_CFGERRTLPCPLHEADER41": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER41", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX7_L_3" }, "PCIE_TOP.PCIE_IMUX7_L_4->PCIE_TOP_CFGERRTLPCPLHEADER45": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER45", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX7_L_4" }, "PCIE_TOP.PCIE_IMUX7_R_0->PCIE_TOP_MIMRXRDATA55": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_MIMRXRDATA55", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX7_R_0" }, "PCIE_TOP.PCIE_IMUX7_R_1->PCIE_TOP_MIMRXRDATA51": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_MIMRXRDATA51", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX7_R_1" }, "PCIE_TOP.PCIE_IMUX7_R_2->PCIE_TOP_MIMRXRDATA47": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_MIMRXRDATA47", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX7_R_2" }, "PCIE_TOP.PCIE_IMUX7_R_3->PCIE_TOP_MIMRXRDATA43": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_MIMRXRDATA43", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX7_R_3" }, "PCIE_TOP.PCIE_IMUX7_R_4->PCIE_TOP_TRNTD27": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD27", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX7_R_4" }, "PCIE_TOP.PCIE_IMUX8_L_0->PCIE_TOP_CFGDSN57": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDSN57", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX8_L_0" }, "PCIE_TOP.PCIE_IMUX8_L_1->PCIE_TOP_CFGDSN61": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDSN61", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX8_L_1" }, "PCIE_TOP.PCIE_IMUX8_L_2->PCIE_TOP_CFGDEVID1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX8_L_2" }, "PCIE_TOP.PCIE_IMUX8_L_3->PCIE_TOP_CFGDEVID5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX8_L_3" }, "PCIE_TOP.PCIE_IMUX8_L_4->PCIE_TOP_CFGDEVID9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX8_L_4" }, "PCIE_TOP.PCIE_IMUX8_R_0->PCIE_TOP_TRNTD8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX8_R_0" }, "PCIE_TOP.PCIE_IMUX8_R_1->PCIE_TOP_TRNTD12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX8_R_1" }, "PCIE_TOP.PCIE_IMUX8_R_2->PCIE_TOP_TRNTD16": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD16", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX8_R_2" }, "PCIE_TOP.PCIE_IMUX8_R_3->PCIE_TOP_TRNTD20": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD20", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX8_R_3" }, "PCIE_TOP.PCIE_IMUX8_R_4->PCIE_TOP_PL2DIRECTEDLSTATE1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX8_R_4" }, "PCIE_TOP.PCIE_IMUX9_L_0->PCIE_TOP_CFGDSN58": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDSN58", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX9_L_0" }, "PCIE_TOP.PCIE_IMUX9_L_1->PCIE_TOP_CFGDSN62": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDSN62", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX9_L_1" }, "PCIE_TOP.PCIE_IMUX9_L_2->PCIE_TOP_CFGDEVID2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX9_L_2" }, "PCIE_TOP.PCIE_IMUX9_L_3->PCIE_TOP_CFGDEVID6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX9_L_3" }, "PCIE_TOP.PCIE_IMUX9_L_4->PCIE_TOP_CFGDEVID10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX9_L_4" }, "PCIE_TOP.PCIE_IMUX9_R_0->PCIE_TOP_TRNTD9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX9_R_0" }, "PCIE_TOP.PCIE_IMUX9_R_1->PCIE_TOP_TRNTD13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX9_R_1" }, "PCIE_TOP.PCIE_IMUX9_R_2->PCIE_TOP_TRNTD17": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD17", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX9_R_2" }, "PCIE_TOP.PCIE_IMUX9_R_3->PCIE_TOP_TRNTD21": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD21", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX9_R_3" }, "PCIE_TOP.PCIE_IMUX9_R_4->PCIE_TOP_PL2DIRECTEDLSTATE2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX9_R_4" }, "PCIE_TOP.PCIE_IMUX10_L_0->PCIE_TOP_CFGDSN59": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDSN59", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX10_L_0" }, "PCIE_TOP.PCIE_IMUX10_L_1->PCIE_TOP_CFGDSN63": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDSN63", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX10_L_1" }, "PCIE_TOP.PCIE_IMUX10_L_2->PCIE_TOP_CFGDEVID3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX10_L_2" }, "PCIE_TOP.PCIE_IMUX10_L_3->PCIE_TOP_CFGDEVID7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX10_L_3" }, "PCIE_TOP.PCIE_IMUX10_L_4->PCIE_TOP_CFGDEVID11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX10_L_4" }, "PCIE_TOP.PCIE_IMUX10_R_0->PCIE_TOP_TRNTD10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX10_R_0" }, "PCIE_TOP.PCIE_IMUX10_R_1->PCIE_TOP_TRNTD14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX10_R_1" }, "PCIE_TOP.PCIE_IMUX10_R_2->PCIE_TOP_TRNTD18": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD18", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX10_R_2" }, "PCIE_TOP.PCIE_IMUX10_R_3->PCIE_TOP_TRNTD22": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD22", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX10_R_3" }, "PCIE_TOP.PCIE_IMUX10_R_4->PCIE_TOP_PL2DIRECTEDLSTATE3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX10_R_4" }, "PCIE_TOP.PCIE_IMUX11_L_0->PCIE_TOP_CFGDSN60": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDSN60", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX11_L_0" }, "PCIE_TOP.PCIE_IMUX11_L_1->PCIE_TOP_CFGDEVID0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX11_L_1" }, "PCIE_TOP.PCIE_IMUX11_L_2->PCIE_TOP_CFGDEVID4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX11_L_2" }, "PCIE_TOP.PCIE_IMUX11_L_3->PCIE_TOP_CFGDEVID8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX11_L_3" }, "PCIE_TOP.PCIE_IMUX11_L_4->PCIE_TOP_CFGDEVID12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX11_L_4" }, "PCIE_TOP.PCIE_IMUX11_R_0->PCIE_TOP_TRNTD11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX11_R_0" }, "PCIE_TOP.PCIE_IMUX11_R_1->PCIE_TOP_TRNTD15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX11_R_1" }, "PCIE_TOP.PCIE_IMUX11_R_2->PCIE_TOP_TRNTD19": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD19", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX11_R_2" }, "PCIE_TOP.PCIE_IMUX11_R_3->PCIE_TOP_TRNTD23": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD23", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX11_R_3" }, "PCIE_TOP.PCIE_IMUX11_R_4->PCIE_TOP_PL2DIRECTEDLSTATE4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX11_R_4" }, "PCIE_TOP.PCIE_IMUX12_L_0->PCIE_TOP_DRPADDR7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPADDR7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX12_L_0" }, "PCIE_TOP.PCIE_IMUX12_L_1->PCIE_TOP_DRPDI0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX12_L_1" }, "PCIE_TOP.PCIE_IMUX12_L_2->PCIE_TOP_DRPDI4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX12_L_2" }, "PCIE_TOP.PCIE_IMUX12_L_3->PCIE_TOP_DRPDI8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX12_L_3" }, "PCIE_TOP.PCIE_IMUX12_L_4->PCIE_TOP_DRPDI12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX12_L_4" }, "PCIE_TOP.PCIE_IMUX12_R_0->PCIE_TOP_TRNTD40": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD40", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX12_R_0" }, "PCIE_TOP.PCIE_IMUX12_R_1->PCIE_TOP_TRNTD36": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD36", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX12_R_1" }, "PCIE_TOP.PCIE_IMUX12_R_2->PCIE_TOP_TRNTD32": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD32", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX12_R_2" }, "PCIE_TOP.PCIE_IMUX12_R_3->PCIE_TOP_TRNTD28": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD28", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX12_R_3" }, "PCIE_TOP.PCIE_IMUX13_L_0->PCIE_TOP_DRPADDR8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPADDR8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX13_L_0" }, "PCIE_TOP.PCIE_IMUX13_L_1->PCIE_TOP_DRPDI1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX13_L_1" }, "PCIE_TOP.PCIE_IMUX13_L_2->PCIE_TOP_DRPDI5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX13_L_2" }, "PCIE_TOP.PCIE_IMUX13_L_3->PCIE_TOP_DRPDI9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX13_L_3" }, "PCIE_TOP.PCIE_IMUX13_L_4->PCIE_TOP_DRPDI13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX13_L_4" }, "PCIE_TOP.PCIE_IMUX13_R_0->PCIE_TOP_TRNTD41": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD41", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX13_R_0" }, "PCIE_TOP.PCIE_IMUX13_R_1->PCIE_TOP_TRNTD37": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD37", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX13_R_1" }, "PCIE_TOP.PCIE_IMUX13_R_2->PCIE_TOP_TRNTD33": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD33", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX13_R_2" }, "PCIE_TOP.PCIE_IMUX13_R_3->PCIE_TOP_TRNTD29": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD29", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX13_R_3" }, "PCIE_TOP.PCIE_IMUX13_R_4->PCIE_TOP_CFGERRAERHEADERLOG6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX13_R_4" }, "PCIE_TOP.PCIE_IMUX14_L_1->PCIE_TOP_DRPDI2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX14_L_1" }, "PCIE_TOP.PCIE_IMUX14_L_2->PCIE_TOP_DRPDI6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX14_L_2" }, "PCIE_TOP.PCIE_IMUX14_L_3->PCIE_TOP_DRPDI10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX14_L_3" }, "PCIE_TOP.PCIE_IMUX14_L_4->PCIE_TOP_DRPDI14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX14_L_4" }, "PCIE_TOP.PCIE_IMUX14_R_1->PCIE_TOP_TRNTD38": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD38", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX14_R_1" }, "PCIE_TOP.PCIE_IMUX14_R_2->PCIE_TOP_TRNTD34": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD34", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX14_R_2" }, "PCIE_TOP.PCIE_IMUX14_R_3->PCIE_TOP_TRNTD30": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD30", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX14_R_3" }, "PCIE_TOP.PCIE_IMUX14_R_4->PCIE_TOP_CFGERRAERHEADERLOG7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX14_R_4" }, "PCIE_TOP.PCIE_IMUX15_L_1->PCIE_TOP_DRPDI3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX15_L_1" }, "PCIE_TOP.PCIE_IMUX15_L_2->PCIE_TOP_DRPDI7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX15_L_2" }, "PCIE_TOP.PCIE_IMUX15_L_3->PCIE_TOP_DRPDI11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX15_L_3" }, "PCIE_TOP.PCIE_IMUX15_L_4->PCIE_TOP_DRPDI15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DRPDI15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX15_L_4" }, "PCIE_TOP.PCIE_IMUX15_R_1->PCIE_TOP_TRNTD39": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD39", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX15_R_1" }, "PCIE_TOP.PCIE_IMUX15_R_2->PCIE_TOP_TRNTD35": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD35", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX15_R_2" }, "PCIE_TOP.PCIE_IMUX15_R_3->PCIE_TOP_TRNTD31": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TRNTD31", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX15_R_3" }, "PCIE_TOP.PCIE_IMUX15_R_4->PCIE_TOP_CFGERRAERHEADERLOG8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX15_R_4" }, "PCIE_TOP.PCIE_IMUX16_L_1->PCIE_TOP_PIPERX0CHARISK0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX0CHARISK0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX16_L_1" }, "PCIE_TOP.PCIE_IMUX16_R_1->PCIE_TOP_PIPERX4CHARISK0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX4CHARISK0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX16_R_1" }, "PCIE_TOP.PCIE_IMUX16_R_3->PCIE_TOP_LL2SUSPENDNOW": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_LL2SUSPENDNOW", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX16_R_3" }, "PCIE_TOP.PCIE_IMUX16_R_4->PCIE_TOP_CFGERRAERHEADERLOG9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX16_R_4" }, "PCIE_TOP.PCIE_IMUX17_R_2->PCIE_TOP_CFGERRLOCKEDN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRLOCKEDN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX17_R_2" }, "PCIE_TOP.PCIE_IMUX17_R_3->PCIE_TOP_TL2PPMSUSPENDREQ": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TL2PPMSUSPENDREQ", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX17_R_3" }, "PCIE_TOP.PCIE_IMUX17_R_4->PCIE_TOP_CFGERRTLPCPLHEADER46": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER46", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX17_R_4" }, "PCIE_TOP.PCIE_IMUX18_R_2->PCIE_TOP_CFGERRNORECOVERYN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRNORECOVERYN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX18_R_2" }, "PCIE_TOP.PCIE_IMUX18_R_3->PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX18_R_3" }, "PCIE_TOP.PCIE_IMUX18_R_4->PCIE_TOP_CFGERRTLPCPLHEADER47": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER47", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX18_R_4" }, "PCIE_TOP.PCIE_IMUX19_R_2->PCIE_TOP_CFGERRAERHEADERLOG0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX19_R_2" }, "PCIE_TOP.PCIE_IMUX19_R_4->PCIE_TOP_CFGINTERRUPTN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGINTERRUPTN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX19_R_4" }, "PCIE_TOP.PCIE_IMUX20_R_2->PCIE_TOP_CFGERRAERHEADERLOG1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX20_R_2" }, "PCIE_TOP.PCIE_IMUX20_R_3->PCIE_TOP_CFGERRAERHEADERLOG2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX20_R_3" }, "PCIE_TOP.PCIE_IMUX20_R_4->PCIE_TOP_CFGINTERRUPTDI0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGINTERRUPTDI0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX20_R_4" }, "PCIE_TOP.PCIE_IMUX21_R_2->PCIE_TOP_CFGERRAERHEADERLOG11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX21_R_2" }, "PCIE_TOP.PCIE_IMUX21_R_3->PCIE_TOP_CFGERRAERHEADERLOG3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX21_R_3" }, "PCIE_TOP.PCIE_IMUX21_R_4->PCIE_TOP_CFGDEVID13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX21_R_4" }, "PCIE_TOP.PCIE_IMUX22_R_3->PCIE_TOP_CFGERRAERHEADERLOG4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX22_R_3" }, "PCIE_TOP.PCIE_IMUX22_R_4->PCIE_TOP_CFGDEVID14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX22_R_4" }, "PCIE_TOP.PCIE_IMUX23_R_3->PCIE_TOP_CFGERRAERHEADERLOG5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX23_R_3" }, "PCIE_TOP.PCIE_IMUX23_R_4->PCIE_TOP_CFGDEVID15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGDEVID15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX23_R_4" }, "PCIE_TOP.PCIE_IMUX24_R_3->PCIE_TOP_CFGERRAERHEADERLOG10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX24_R_3" }, "PCIE_TOP.PCIE_IMUX24_R_4->PCIE_TOP_CFGVENDID0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_CFGVENDID0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX24_R_4" }, "PCIE_TOP.PCIE_IMUX25_R_4->PCIE_TOP_DBGMODE0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_DBGMODE0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX25_R_4" }, "PCIE_TOP.PCIE_IMUX32_L_1->PCIE_TOP_PIPERX0DATA3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX0DATA3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX32_L_1" }, "PCIE_TOP.PCIE_IMUX32_R_1->PCIE_TOP_PIPERX4DATA3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX4DATA3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX32_R_1" }, "PCIE_TOP.PCIE_IMUX33_L_0->PCIE_TOP_PIPERX0CHANISALIGNED": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX0CHANISALIGNED", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX33_L_0" }, "PCIE_TOP.PCIE_IMUX33_L_1->PCIE_TOP_PIPERX0DATA2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX0DATA2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX33_L_1" }, "PCIE_TOP.PCIE_IMUX33_R_0->PCIE_TOP_PIPERX4CHANISALIGNED": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX4CHANISALIGNED", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX33_R_0" }, "PCIE_TOP.PCIE_IMUX33_R_1->PCIE_TOP_PIPERX4DATA2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX4DATA2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX33_R_1" }, "PCIE_TOP.PCIE_IMUX34_L_0->PCIE_TOP_PIPERX0DATA7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX0DATA7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX34_L_0" }, "PCIE_TOP.PCIE_IMUX34_R_0->PCIE_TOP_PIPERX4DATA7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX4DATA7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX34_R_0" }, "PCIE_TOP.PCIE_IMUX35_L_0->PCIE_TOP_PIPERX0DATA6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX0DATA6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX35_L_0" }, "PCIE_TOP.PCIE_IMUX35_R_0->PCIE_TOP_PIPERX4DATA6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX4DATA6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX35_R_0" }, "PCIE_TOP.PCIE_IMUX36_L_0->PCIE_TOP_PIPERX0VALID": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX0VALID", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX36_L_0" }, "PCIE_TOP.PCIE_IMUX36_L_1->PCIE_TOP_PIPERX0DATA1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX0DATA1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX36_L_1" }, "PCIE_TOP.PCIE_IMUX36_R_0->PCIE_TOP_PIPERX4VALID": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX4VALID", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX36_R_0" }, "PCIE_TOP.PCIE_IMUX36_R_1->PCIE_TOP_PIPERX4DATA1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX4DATA1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX36_R_1" }, "PCIE_TOP.PCIE_IMUX37_L_0->PCIE_TOP_PIPERX0PHYSTATUS": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX0PHYSTATUS", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX37_L_0" }, "PCIE_TOP.PCIE_IMUX37_L_1->PCIE_TOP_PIPERX0DATA0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX0DATA0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX37_L_1" }, "PCIE_TOP.PCIE_IMUX37_R_0->PCIE_TOP_PIPERX4PHYSTATUS": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX4PHYSTATUS", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX37_R_0" }, "PCIE_TOP.PCIE_IMUX37_R_1->PCIE_TOP_PIPERX4DATA0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX4DATA0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX37_R_1" }, "PCIE_TOP.PCIE_IMUX38_L_0->PCIE_TOP_PIPERX0DATA5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX0DATA5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX38_L_0" }, "PCIE_TOP.PCIE_IMUX38_R_0->PCIE_TOP_PIPERX4DATA5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX4DATA5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX38_R_0" }, "PCIE_TOP.PCIE_IMUX39_L_0->PCIE_TOP_PIPERX0DATA4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX0DATA4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX39_L_0" }, "PCIE_TOP.PCIE_IMUX39_R_0->PCIE_TOP_PIPERX4DATA4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_TOP_PIPERX4DATA4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_IMUX39_R_0" }, "PCIE_TOP.PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED->PCIE_LOGIC_OUTS_B21_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED" }, "PCIE_TOP.PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED->PCIE_LOGIC_OUTS_B16_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED" }, "PCIE_TOP.PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN" }, "PCIE_TOP.PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED->PCIE_LOGIC_OUTS_B22_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B22_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED" }, "PCIE_TOP.PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B19_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN" }, "PCIE_TOP.PCIE_TOP_CFGCOMMANDBUSMASTERENABLE->PCIE_LOGIC_OUTS_B20_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B20_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGCOMMANDBUSMASTERENABLE" }, "PCIE_TOP.PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE->PCIE_LOGIC_OUTS_B21_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B21_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE" }, "PCIE_TOP.PCIE_TOP_CFGCOMMANDIOENABLE->PCIE_LOGIC_OUTS_B11_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B11_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGCOMMANDIOENABLE" }, "PCIE_TOP.PCIE_TOP_CFGCOMMANDMEMENABLE->PCIE_LOGIC_OUTS_B17_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B17_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGCOMMANDMEMENABLE" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN->PCIE_LOGIC_OUTS_B15_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK->PCIE_LOGIC_OUTS_B13_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B13_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN->PCIE_LOGIC_OUTS_B12_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS->PCIE_LOGIC_OUTS_B14_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0->PCIE_LOGIC_OUTS_B14_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1->PCIE_LOGIC_OUTS_B15_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2->PCIE_LOGIC_OUTS_B12_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3->PCIE_LOGIC_OUTS_B13_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B13_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2IDOCPLEN->PCIE_LOGIC_OUTS_B15_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2IDOCPLEN" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2IDOREQEN->PCIE_LOGIC_OUTS_B14_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2IDOREQEN" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2LTREN->PCIE_LOGIC_OUTS_B23_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B23_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2LTREN" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLASPMCONTROL1->PCIE_LOGIC_OUTS_B13_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B13_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGLINKCONTROLASPMCONTROL1" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN->PCIE_LOGIC_OUTS_B13_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B13_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN->PCIE_LOGIC_OUTS_B12_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLCLOCKPMEN->PCIE_LOGIC_OUTS_B14_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGLINKCONTROLCLOCKPMEN" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK->PCIE_LOGIC_OUTS_B12_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC->PCIE_LOGIC_OUTS_B13_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B13_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS->PCIE_LOGIC_OUTS_B15_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLLINKDISABLE->PCIE_LOGIC_OUTS_B15_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGLINKCONTROLLINKDISABLE" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLRCB->PCIE_LOGIC_OUTS_B14_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGLINKCONTROLRCB" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLRETRAINLINK->PCIE_LOGIC_OUTS_B17_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGLINKCONTROLRETRAINLINK" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO16->PCIE_LOGIC_OUTS_B21_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B21_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO16" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO17->PCIE_LOGIC_OUTS_B16_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B16_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO17" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO18->PCIE_LOGIC_OUTS_B17_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B17_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO18" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO19->PCIE_LOGIC_OUTS_B19_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B19_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO19" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO20->PCIE_LOGIC_OUTS_B11_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B11_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO20" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO21->PCIE_LOGIC_OUTS_B12_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B12_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO21" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO22->PCIE_LOGIC_OUTS_B13_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B13_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO22" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO23->PCIE_LOGIC_OUTS_B15_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B15_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO23" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO24->PCIE_LOGIC_OUTS_B13_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B13_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO24" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO25->PCIE_LOGIC_OUTS_B14_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B14_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO25" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO26->PCIE_LOGIC_OUTS_B15_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B15_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO26" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO27->PCIE_LOGIC_OUTS_B16_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B16_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO27" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO28->PCIE_LOGIC_OUTS_B16_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B16_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO28" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO29->PCIE_LOGIC_OUTS_B17_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B17_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO29" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO30->PCIE_LOGIC_OUTS_B18_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B18_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGMGMTDO30" }, "PCIE_TOP.PCIE_TOP_CFGPCIELINKSTATE1->PCIE_LOGIC_OUTS_B9_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B9_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGPCIELINKSTATE1" }, "PCIE_TOP.PCIE_TOP_CFGPCIELINKSTATE2->PCIE_LOGIC_OUTS_B10_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B10_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGPCIELINKSTATE2" }, "PCIE_TOP.PCIE_TOP_CFGPMCSRPMEEN->PCIE_LOGIC_OUTS_B8_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B8_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGPMCSRPMEEN" }, "PCIE_TOP.PCIE_TOP_CFGPMCSRPMESTATUS->PCIE_LOGIC_OUTS_B9_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B9_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGPMCSRPMESTATUS" }, "PCIE_TOP.PCIE_TOP_CFGPMCSRPOWERSTATE0->PCIE_LOGIC_OUTS_B10_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B10_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGPMCSRPOWERSTATE0" }, "PCIE_TOP.PCIE_TOP_CFGPMCSRPOWERSTATE1->PCIE_LOGIC_OUTS_B11_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B11_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGPMCSRPOWERSTATE1" }, "PCIE_TOP.PCIE_TOP_CFGPMRCVASREQL1N->PCIE_LOGIC_OUTS_B11_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B11_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGPMRCVASREQL1N" }, "PCIE_TOP.PCIE_TOP_CFGPMRCVENTERL1N->PCIE_LOGIC_OUTS_B12_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGPMRCVENTERL1N" }, "PCIE_TOP.PCIE_TOP_CFGPMRCVENTERL23N->PCIE_LOGIC_OUTS_B8_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B8_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGPMRCVENTERL23N" }, "PCIE_TOP.PCIE_TOP_CFGPMRCVREQACKN->PCIE_LOGIC_OUTS_B9_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B9_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGPMRCVREQACKN" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTION->PCIE_LOGIC_OUTS_B10_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B10_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGTRANSACTION" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR0->PCIE_LOGIC_OUTS_B8_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B8_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR0" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR1->PCIE_LOGIC_OUTS_B9_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B9_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR1" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR2->PCIE_LOGIC_OUTS_B10_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B10_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR2" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR3->PCIE_LOGIC_OUTS_B11_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B11_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR3" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR4->PCIE_LOGIC_OUTS_B8_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B8_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR4" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR5->PCIE_LOGIC_OUTS_B9_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B9_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR5" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR6->PCIE_LOGIC_OUTS_B10_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B10_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR6" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONTYPE->PCIE_LOGIC_OUTS_B11_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B11_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGTRANSACTIONTYPE" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP0->PCIE_LOGIC_OUTS_B17_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP0" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP1->PCIE_LOGIC_OUTS_B18_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP1" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP2->PCIE_LOGIC_OUTS_B19_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP2" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP3->PCIE_LOGIC_OUTS_B16_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP3" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP4->PCIE_LOGIC_OUTS_B17_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP4" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP5->PCIE_LOGIC_OUTS_B18_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP5" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP6->PCIE_LOGIC_OUTS_B19_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP6" }, "PCIE_TOP.PCIE_TOP_DBGVECA0->PCIE_LOGIC_OUTS_B21_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA0" }, "PCIE_TOP.PCIE_TOP_DBGVECA1->PCIE_LOGIC_OUTS_B22_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B22_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA1" }, "PCIE_TOP.PCIE_TOP_DBGVECA2->PCIE_LOGIC_OUTS_B23_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B23_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA2" }, "PCIE_TOP.PCIE_TOP_DBGVECA3->PCIE_LOGIC_OUTS_B20_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA3" }, "PCIE_TOP.PCIE_TOP_DBGVECA4->PCIE_LOGIC_OUTS_B21_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA4" }, "PCIE_TOP.PCIE_TOP_DBGVECA5->PCIE_LOGIC_OUTS_B22_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B22_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA5" }, "PCIE_TOP.PCIE_TOP_DBGVECA6->PCIE_LOGIC_OUTS_B23_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B23_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA6" }, "PCIE_TOP.PCIE_TOP_DBGVECA7->PCIE_LOGIC_OUTS_B20_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA7" }, "PCIE_TOP.PCIE_TOP_DBGVECA8->PCIE_LOGIC_OUTS_B21_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA8" }, "PCIE_TOP.PCIE_TOP_DBGVECA9->PCIE_LOGIC_OUTS_B22_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B22_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA9" }, "PCIE_TOP.PCIE_TOP_DBGVECA10->PCIE_LOGIC_OUTS_B23_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B23_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA10" }, "PCIE_TOP.PCIE_TOP_DBGVECA11->PCIE_LOGIC_OUTS_B22_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B22_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA11" }, "PCIE_TOP.PCIE_TOP_DBGVECA12->PCIE_LOGIC_OUTS_B20_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B20_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA12" }, "PCIE_TOP.PCIE_TOP_DBGVECA13->PCIE_LOGIC_OUTS_B21_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B21_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA13" }, "PCIE_TOP.PCIE_TOP_DBGVECA14->PCIE_LOGIC_OUTS_B20_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B20_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA14" }, "PCIE_TOP.PCIE_TOP_DBGVECA15->PCIE_LOGIC_OUTS_B23_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B23_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA15" }, "PCIE_TOP.PCIE_TOP_DBGVECA16->PCIE_LOGIC_OUTS_B22_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B22_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA16" }, "PCIE_TOP.PCIE_TOP_DBGVECA17->PCIE_LOGIC_OUTS_B23_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B23_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA17" }, "PCIE_TOP.PCIE_TOP_DBGVECA18->PCIE_LOGIC_OUTS_B14_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B14_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA18" }, "PCIE_TOP.PCIE_TOP_DBGVECA19->PCIE_LOGIC_OUTS_B19_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B19_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA19" }, "PCIE_TOP.PCIE_TOP_DBGVECA20->PCIE_LOGIC_OUTS_B20_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B20_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA20" }, "PCIE_TOP.PCIE_TOP_DBGVECA21->PCIE_LOGIC_OUTS_B21_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B21_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECA21" }, "PCIE_TOP.PCIE_TOP_DBGVECB10->PCIE_LOGIC_OUTS_B22_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B22_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DBGVECB10" }, "PCIE_TOP.PCIE_TOP_DRPDO0->PCIE_LOGIC_OUTS_B17_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPDO0" }, "PCIE_TOP.PCIE_TOP_DRPDO1->PCIE_LOGIC_OUTS_B18_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPDO1" }, "PCIE_TOP.PCIE_TOP_DRPDO2->PCIE_LOGIC_OUTS_B19_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPDO2" }, "PCIE_TOP.PCIE_TOP_DRPDO3->PCIE_LOGIC_OUTS_B16_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPDO3" }, "PCIE_TOP.PCIE_TOP_DRPDO4->PCIE_LOGIC_OUTS_B17_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPDO4" }, "PCIE_TOP.PCIE_TOP_DRPDO5->PCIE_LOGIC_OUTS_B18_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPDO5" }, "PCIE_TOP.PCIE_TOP_DRPDO6->PCIE_LOGIC_OUTS_B19_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPDO6" }, "PCIE_TOP.PCIE_TOP_DRPDO11->PCIE_LOGIC_OUTS_B20_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPDO11" }, "PCIE_TOP.PCIE_TOP_DRPDO12->PCIE_LOGIC_OUTS_B21_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPDO12" }, "PCIE_TOP.PCIE_TOP_DRPDO13->PCIE_LOGIC_OUTS_B22_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B22_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPDO13" }, "PCIE_TOP.PCIE_TOP_DRPDO14->PCIE_LOGIC_OUTS_B23_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B23_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPDO14" }, "PCIE_TOP.PCIE_TOP_DRPDO15->PCIE_LOGIC_OUTS_B20_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPDO15" }, "PCIE_TOP.PCIE_TOP_DRPRDY->PCIE_LOGIC_OUTS_B16_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_DRPRDY" }, "PCIE_TOP.PCIE_TOP_LL2TFCINIT1SEQ->PCIE_LOGIC_OUTS_B16_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B16_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_LL2TFCINIT1SEQ" }, "PCIE_TOP.PCIE_TOP_LL2TFCINIT2SEQ->PCIE_LOGIC_OUTS_B20_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B20_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_LL2TFCINIT2SEQ" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR0->PCIE_LOGIC_OUTS_B13_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B13_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXRADDR0" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR1->PCIE_LOGIC_OUTS_B11_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B11_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXRADDR1" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR2->PCIE_LOGIC_OUTS_B12_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B12_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXRADDR2" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR4->PCIE_LOGIC_OUTS_B5_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B5_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXRADDR4" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR8->PCIE_LOGIC_OUTS_B17_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B17_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXRADDR8" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR9->PCIE_LOGIC_OUTS_B8_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B8_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXRADDR9" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR10->PCIE_LOGIC_OUTS_B3_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B3_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXRADDR10" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR11->PCIE_LOGIC_OUTS_B10_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B10_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXRADDR11" }, "PCIE_TOP.PCIE_TOP_MIMRXREN->PCIE_LOGIC_OUTS_B12_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B12_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXREN" }, "PCIE_TOP.PCIE_TOP_MIMRXWADDR1->PCIE_LOGIC_OUTS_B15_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B15_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWADDR1" }, "PCIE_TOP.PCIE_TOP_MIMRXWADDR2->PCIE_LOGIC_OUTS_B0_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B0_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWADDR2" }, "PCIE_TOP.PCIE_TOP_MIMRXWADDR5->PCIE_LOGIC_OUTS_B9_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B9_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWADDR5" }, "PCIE_TOP.PCIE_TOP_MIMRXWADDR12->PCIE_LOGIC_OUTS_B1_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B1_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWADDR12" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA0->PCIE_LOGIC_OUTS_B11_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B11_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA0" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA1->PCIE_LOGIC_OUTS_B13_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B13_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA1" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA2->PCIE_LOGIC_OUTS_B18_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B18_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA2" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA3->PCIE_LOGIC_OUTS_B15_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B15_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA3" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA4->PCIE_LOGIC_OUTS_B9_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B9_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA4" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA5->PCIE_LOGIC_OUTS_B22_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B22_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA5" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA6->PCIE_LOGIC_OUTS_B16_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B16_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA6" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA7->PCIE_LOGIC_OUTS_B23_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B23_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA7" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA8->PCIE_LOGIC_OUTS_B8_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B8_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA8" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA9->PCIE_LOGIC_OUTS_B3_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B3_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA9" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA10->PCIE_LOGIC_OUTS_B19_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B19_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA10" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA11->PCIE_LOGIC_OUTS_B18_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B18_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA11" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA12->PCIE_LOGIC_OUTS_B2_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B2_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA12" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA13->PCIE_LOGIC_OUTS_B9_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B9_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA13" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA15->PCIE_LOGIC_OUTS_B10_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B10_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA15" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA17->PCIE_LOGIC_OUTS_B9_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B9_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA17" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA19->PCIE_LOGIC_OUTS_B8_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B8_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA19" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA20->PCIE_LOGIC_OUTS_B0_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B0_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA20" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA21->PCIE_LOGIC_OUTS_B19_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B19_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA21" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA22->PCIE_LOGIC_OUTS_B15_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B15_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA22" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA23->PCIE_LOGIC_OUTS_B14_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B14_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA23" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA24->PCIE_LOGIC_OUTS_B0_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B0_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA24" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA25->PCIE_LOGIC_OUTS_B10_R_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B10_R_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA25" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA26->PCIE_LOGIC_OUTS_B13_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B13_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA26" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA27->PCIE_LOGIC_OUTS_B19_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B19_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA27" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA28->PCIE_LOGIC_OUTS_B14_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B14_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA28" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA29->PCIE_LOGIC_OUTS_B8_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B8_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA29" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA30->PCIE_LOGIC_OUTS_B18_R_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B18_R_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA30" }, 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null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA33" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA34->PCIE_LOGIC_OUTS_B17_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B17_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA34" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA35->PCIE_LOGIC_OUTS_B11_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B11_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA35" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA49->PCIE_LOGIC_OUTS_B5_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B5_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA49" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA51->PCIE_LOGIC_OUTS_B7_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B7_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWDATA51" }, "PCIE_TOP.PCIE_TOP_MIMRXWEN->PCIE_LOGIC_OUTS_B18_R_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B18_R_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_MIMRXWEN" }, "PCIE_TOP.PCIE_TOP_PIPETXMARGIN0->PCIE_LOGIC_OUTS_B18_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": 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{ "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B12_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_PL2RECOVERY" }, "PCIE_TOP.PCIE_TOP_PL2SUSPENDOK->PCIE_LOGIC_OUTS_B7_R_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B7_R_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_PL2SUSPENDOK" }, "PCIE_TOP.PCIE_TOP_PLDBGVEC8->PCIE_LOGIC_OUTS_B23_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B23_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_PLDBGVEC8" }, "PCIE_TOP.PCIE_TOP_TRNRD59->PCIE_LOGIC_OUTS_B0_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B0_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD59" }, "PCIE_TOP.PCIE_TOP_TRNRD60->PCIE_LOGIC_OUTS_B1_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B1_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD60" }, "PCIE_TOP.PCIE_TOP_TRNRD61->PCIE_LOGIC_OUTS_B2_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B2_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD61" }, "PCIE_TOP.PCIE_TOP_TRNRD62->PCIE_LOGIC_OUTS_B3_L_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B3_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD62" }, "PCIE_TOP.PCIE_TOP_TRNRD63->PCIE_LOGIC_OUTS_B0_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B0_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD63" }, "PCIE_TOP.PCIE_TOP_TRNRD64->PCIE_LOGIC_OUTS_B1_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B1_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD64" }, "PCIE_TOP.PCIE_TOP_TRNRD65->PCIE_LOGIC_OUTS_B2_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B2_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD65" }, "PCIE_TOP.PCIE_TOP_TRNRD66->PCIE_LOGIC_OUTS_B3_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B3_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD66" }, "PCIE_TOP.PCIE_TOP_TRNRD67->PCIE_LOGIC_OUTS_B0_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B0_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD67" }, "PCIE_TOP.PCIE_TOP_TRNRD68->PCIE_LOGIC_OUTS_B1_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B1_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD68" }, "PCIE_TOP.PCIE_TOP_TRNRD69->PCIE_LOGIC_OUTS_B2_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B2_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD69" }, "PCIE_TOP.PCIE_TOP_TRNRD70->PCIE_LOGIC_OUTS_B3_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B3_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD70" }, "PCIE_TOP.PCIE_TOP_TRNRD71->PCIE_LOGIC_OUTS_B0_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B0_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD71" }, "PCIE_TOP.PCIE_TOP_TRNRD72->PCIE_LOGIC_OUTS_B1_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B1_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD72" }, "PCIE_TOP.PCIE_TOP_TRNRD73->PCIE_LOGIC_OUTS_B2_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B2_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD73" }, "PCIE_TOP.PCIE_TOP_TRNRD74->PCIE_LOGIC_OUTS_B3_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B3_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD74" }, "PCIE_TOP.PCIE_TOP_TRNRD75->PCIE_LOGIC_OUTS_B0_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B0_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD75" }, "PCIE_TOP.PCIE_TOP_TRNRD76->PCIE_LOGIC_OUTS_B1_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B1_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD76" }, "PCIE_TOP.PCIE_TOP_TRNRD77->PCIE_LOGIC_OUTS_B2_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B2_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD77" }, "PCIE_TOP.PCIE_TOP_TRNRD78->PCIE_LOGIC_OUTS_B3_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B3_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD78" }, "PCIE_TOP.PCIE_TOP_TRNRD79->PCIE_LOGIC_OUTS_B0_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B0_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD79" }, "PCIE_TOP.PCIE_TOP_TRNRD80->PCIE_LOGIC_OUTS_B2_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B2_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD80" }, "PCIE_TOP.PCIE_TOP_TRNRD81->PCIE_LOGIC_OUTS_B3_R_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B3_R_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRD81" }, "PCIE_TOP.PCIE_TOP_TRNRD82->PCIE_LOGIC_OUTS_B4_R_4": { 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"dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B8_L_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRDLLPDATA35" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA36->PCIE_LOGIC_OUTS_B4_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B4_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRDLLPDATA36" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA37->PCIE_LOGIC_OUTS_B5_L_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B5_L_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRDLLPDATA37" }, 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"in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRDLLPDATA40" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA41->PCIE_LOGIC_OUTS_B5_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B5_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRDLLPDATA41" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA42->PCIE_LOGIC_OUTS_B6_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B6_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRDLLPDATA42" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA43->PCIE_LOGIC_OUTS_B7_L_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B7_L_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRDLLPDATA43" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA44->PCIE_LOGIC_OUTS_B4_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B4_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRDLLPDATA44" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA45->PCIE_LOGIC_OUTS_B5_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B5_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRDLLPDATA45" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA46->PCIE_LOGIC_OUTS_B6_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B6_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRDLLPDATA46" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA47->PCIE_LOGIC_OUTS_B7_L_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B7_L_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRDLLPDATA47" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA48->PCIE_LOGIC_OUTS_B4_L_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "PCIE_LOGIC_OUTS_B4_L_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "PCIE_TOP_TRNRDLLPDATA48" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA49->PCIE_LOGIC_OUTS_B5_L_4": { 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}, "PCIE_WW4B0_4": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B1_0": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B1_1": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B1_2": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B1_3": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B1_4": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B2_0": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B2_1": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B2_2": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B2_3": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B2_4": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B3_0": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B3_1": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B3_2": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B3_3": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4B3_4": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4C0_0": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4C0_1": { "cap": "60.227", "res": "487.600" }, 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"60.227", "res": "487.600" }, "PCIE_WW4END3_3": { "cap": "60.227", "res": "487.600" }, "PCIE_WW4END3_4": { "cap": "60.227", "res": "487.600" } } }