{ "pips": { "CMT_FIFO_L.CMT_FIFO_L_CLK0_6->CMT_OUT_FIFO_WRCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_WRCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_CLK0_6" }, "CMT_FIFO_L.CMT_FIFO_L_CLK0_7->CMT_OUT_FIFO_RDCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_RDCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_CLK0_7" }, "CMT_FIFO_L.CMT_FIFO_L_CLK1_6->CMT_IN_FIFO_WRCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_WRCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_CLK1_6" }, "CMT_FIFO_L.CMT_FIFO_L_CLK1_7->CMT_IN_FIFO_RDCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_RDCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_CLK1_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_0->CMT_OUT_FIFO_D05": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D05", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX5_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_1->CMT_OUT_FIFO_D15": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D15", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX5_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_2->CMT_OUT_FIFO_D25": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D25", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX5_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_3->CMT_OUT_FIFO_D35": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D35", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX5_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_4->CMT_OUT_FIFO_D45": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D45", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX5_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_5->CMT_OUT_FIFO_D55": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D55", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX5_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_6->CMT_OUT_FIFO_RESET": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_RESET", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX5_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_7->CMT_IN_FIFO_RESET": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_RESET", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX5_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_8->CMT_OUT_FIFO_D65": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D65", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX5_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_9->CMT_OUT_FIFO_D75": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D75", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX5_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_10->CMT_OUT_FIFO_D85": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D85", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX5_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_11->CMT_OUT_FIFO_D95": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D95", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX5_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_0->CMT_OUT_FIFO_D07": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D07", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX6_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_1->CMT_OUT_FIFO_D17": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D17", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX6_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_2->CMT_OUT_FIFO_D27": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D27", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX6_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_3->CMT_OUT_FIFO_D37": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D37", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX6_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_4->CMT_OUT_FIFO_D47": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D47", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX6_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_5->CMT_OUT_FIFO_D57": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D57", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX6_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_6->CMT_OUT_FIFO_WREN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_WREN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX6_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_7->CMT_OUT_FIFO_RDEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_RDEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX6_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_8->CMT_OUT_FIFO_D67": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D67", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX6_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_9->CMT_OUT_FIFO_D77": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D77", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX6_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_10->CMT_OUT_FIFO_D87": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D87", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX6_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_11->CMT_OUT_FIFO_D97": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D97", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX6_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_0->CMT_OUT_FIFO_D06": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D06", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX7_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_1->CMT_OUT_FIFO_D16": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D16", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX7_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_2->CMT_OUT_FIFO_D26": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D26", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX7_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_3->CMT_OUT_FIFO_D36": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D36", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX7_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_4->CMT_OUT_FIFO_D46": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D46", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX7_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_5->CMT_OUT_FIFO_D56": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D56", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX7_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_6->CMT_IN_FIFO_WREN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_WREN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX7_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_7->CMT_IN_FIFO_RDEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_RDEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX7_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_8->CMT_OUT_FIFO_D66": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D66", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX7_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_9->CMT_OUT_FIFO_D76": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D76", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX7_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_10->CMT_OUT_FIFO_D86": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D86", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX7_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_11->CMT_OUT_FIFO_D96": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D96", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX7_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_0->CMT_OUT_FIFO_D04": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D04", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX12_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_1->CMT_OUT_FIFO_D14": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D14", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX12_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_2->CMT_OUT_FIFO_D24": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D24", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX12_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_3->CMT_OUT_FIFO_D34": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D34", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX12_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_4->CMT_OUT_FIFO_D44": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D44", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX12_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_5->CMT_OUT_FIFO_D54": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D54", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX12_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_8->CMT_OUT_FIFO_D64": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D64", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX12_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_9->CMT_OUT_FIFO_D74": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D74", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX12_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_10->CMT_OUT_FIFO_D84": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D84", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX12_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_11->CMT_OUT_FIFO_D94": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D94", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX12_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_0->CMT_OUT_FIFO_D01": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D01", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX21_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_1->CMT_OUT_FIFO_D11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX21_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_2->CMT_OUT_FIFO_D21": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D21", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX21_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_3->CMT_OUT_FIFO_D31": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D31", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX21_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_4->CMT_OUT_FIFO_D41": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D41", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX21_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_5->CMT_OUT_FIFO_D51": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D51", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX21_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_8->CMT_OUT_FIFO_D61": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D61", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX21_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_9->CMT_OUT_FIFO_D71": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D71", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX21_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_10->CMT_OUT_FIFO_D81": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D81", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX21_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_11->CMT_OUT_FIFO_D91": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D91", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX21_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_0->CMT_IN_FIFO_D00": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D00", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX26_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_1->CMT_IN_FIFO_D10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX26_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_2->CMT_IN_FIFO_D20": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D20", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX26_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_3->CMT_IN_FIFO_D30": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D30", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX26_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_4->CMT_IN_FIFO_D40": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D40", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX26_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_5->CMT_IN_FIFO_D50": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D50", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX26_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_6->CMT_IN_FIFO_D54": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D54", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX26_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_7->CMT_IN_FIFO_D64": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D64", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX26_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_8->CMT_IN_FIFO_D60": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D60", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX26_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_9->CMT_IN_FIFO_D70": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D70", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX26_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_10->CMT_IN_FIFO_D80": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D80", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX26_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_11->CMT_IN_FIFO_D90": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D90", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX26_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_0->CMT_OUT_FIFO_D00": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D00", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX28_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_1->CMT_OUT_FIFO_D10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX28_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_2->CMT_OUT_FIFO_D20": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D20", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX28_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_3->CMT_OUT_FIFO_D30": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D30", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX28_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_4->CMT_OUT_FIFO_D40": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D40", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX28_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_5->CMT_OUT_FIFO_D50": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D50", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX28_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_8->CMT_OUT_FIFO_D60": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D60", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX28_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_9->CMT_OUT_FIFO_D70": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D70", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX28_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_10->CMT_OUT_FIFO_D80": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D80", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX28_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_11->CMT_OUT_FIFO_D90": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D90", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX28_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_0->CMT_IN_FIFO_D02": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D02", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX36_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_1->CMT_IN_FIFO_D12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX36_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_2->CMT_IN_FIFO_D22": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D22", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX36_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_3->CMT_IN_FIFO_D32": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D32", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX36_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_4->CMT_IN_FIFO_D42": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D42", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX36_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_5->CMT_IN_FIFO_D52": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D52", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX36_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_6->CMT_IN_FIFO_D56": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D56", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX36_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_7->CMT_IN_FIFO_D66": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D66", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX36_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_8->CMT_IN_FIFO_D62": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D62", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX36_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_9->CMT_IN_FIFO_D72": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D72", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX36_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_10->CMT_IN_FIFO_D82": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D82", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX36_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_11->CMT_IN_FIFO_D92": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D92", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX36_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_0->CMT_OUT_FIFO_D03": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D03", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX38_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_1->CMT_OUT_FIFO_D13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX38_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_2->CMT_OUT_FIFO_D23": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D23", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX38_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_3->CMT_OUT_FIFO_D33": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D33", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX38_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_4->CMT_OUT_FIFO_D43": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D43", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX38_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_5->CMT_OUT_FIFO_D53": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D53", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX38_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_8->CMT_OUT_FIFO_D63": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D63", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX38_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_9->CMT_OUT_FIFO_D73": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D73", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX38_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_10->CMT_OUT_FIFO_D83": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D83", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX38_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_11->CMT_OUT_FIFO_D93": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D93", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX38_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_0->CMT_OUT_FIFO_D02": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D02", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX39_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_1->CMT_OUT_FIFO_D12": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D12", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX39_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_2->CMT_OUT_FIFO_D22": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D22", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX39_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_3->CMT_OUT_FIFO_D32": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D32", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX39_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_4->CMT_OUT_FIFO_D42": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D42", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX39_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_5->CMT_OUT_FIFO_D52": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D52", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX39_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_8->CMT_OUT_FIFO_D62": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D62", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX39_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_9->CMT_OUT_FIFO_D72": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D72", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX39_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_10->CMT_OUT_FIFO_D82": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D82", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX39_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_11->CMT_OUT_FIFO_D92": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_D92", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX39_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_0->CMT_IN_FIFO_D01": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D01", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX40_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_1->CMT_IN_FIFO_D11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX40_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_2->CMT_IN_FIFO_D21": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D21", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX40_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_3->CMT_IN_FIFO_D31": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D31", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX40_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_4->CMT_IN_FIFO_D41": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D41", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX40_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_5->CMT_IN_FIFO_D51": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D51", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX40_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_6->CMT_IN_FIFO_D55": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D55", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX40_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_7->CMT_IN_FIFO_D65": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D65", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX40_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_8->CMT_IN_FIFO_D61": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D61", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX40_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_9->CMT_IN_FIFO_D71": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D71", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX40_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_10->CMT_IN_FIFO_D81": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D81", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX40_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_11->CMT_IN_FIFO_D91": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D91", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX40_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_0->CMT_IN_FIFO_D03": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D03", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX42_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_1->CMT_IN_FIFO_D13": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D13", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX42_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_2->CMT_IN_FIFO_D23": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D23", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX42_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_3->CMT_IN_FIFO_D33": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D33", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX42_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_4->CMT_IN_FIFO_D43": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D43", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX42_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_5->CMT_IN_FIFO_D53": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D53", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX42_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_6->CMT_IN_FIFO_D57": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D57", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX42_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_7->CMT_IN_FIFO_D67": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D67", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX42_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_8->CMT_IN_FIFO_D63": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D63", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX42_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_9->CMT_IN_FIFO_D73": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D73", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX42_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_10->CMT_IN_FIFO_D83": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D83", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX42_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_11->CMT_IN_FIFO_D93": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_D93", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_IMUX42_11" }, "CMT_FIFO_L.CMT_FIFO_L_PHASER_RDCLK->CMT_OUT_FIFO_RDCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_RDCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_PHASER_RDCLK" }, "CMT_FIFO_L.CMT_FIFO_L_PHASER_RDENABLE->CMT_OUT_FIFO_RDEN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_OUT_FIFO_RDEN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_PHASER_RDENABLE" }, "CMT_FIFO_L.CMT_FIFO_L_PHASER_WRCLK->CMT_IN_FIFO_WRCLK": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_WRCLK", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_PHASER_WRCLK" }, "CMT_FIFO_L.CMT_FIFO_L_PHASER_WRENABLE->CMT_IN_FIFO_WREN": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_IN_FIFO_WREN", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_FIFO_L_PHASER_WRENABLE" }, "CMT_FIFO_L.CMT_IN_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_ALMOSTEMPTY" }, "CMT_FIFO_L.CMT_IN_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_ALMOSTFULL" }, "CMT_FIFO_L.CMT_IN_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_EMPTY" }, "CMT_FIFO_L.CMT_IN_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_7": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_7", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_FULL" }, "CMT_FIFO_L.CMT_IN_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS0_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q00" }, "CMT_FIFO_L.CMT_IN_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS4_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q01" }, "CMT_FIFO_L.CMT_IN_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS5_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q02" }, "CMT_FIFO_L.CMT_IN_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS1_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q03" }, "CMT_FIFO_L.CMT_IN_FIFO_Q04->CMT_FIFO_L_LOGIC_OUTS12_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q04" }, "CMT_FIFO_L.CMT_IN_FIFO_Q05->CMT_FIFO_L_LOGIC_OUTS8_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q05" }, "CMT_FIFO_L.CMT_IN_FIFO_Q06->CMT_FIFO_L_LOGIC_OUTS9_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q06" }, "CMT_FIFO_L.CMT_IN_FIFO_Q07->CMT_FIFO_L_LOGIC_OUTS13_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q07" }, "CMT_FIFO_L.CMT_IN_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS0_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q10" }, "CMT_FIFO_L.CMT_IN_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS4_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q11" }, "CMT_FIFO_L.CMT_IN_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS5_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q12" }, "CMT_FIFO_L.CMT_IN_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS1_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q13" }, "CMT_FIFO_L.CMT_IN_FIFO_Q14->CMT_FIFO_L_LOGIC_OUTS12_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q14" }, "CMT_FIFO_L.CMT_IN_FIFO_Q15->CMT_FIFO_L_LOGIC_OUTS8_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q15" }, "CMT_FIFO_L.CMT_IN_FIFO_Q16->CMT_FIFO_L_LOGIC_OUTS9_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q16" }, "CMT_FIFO_L.CMT_IN_FIFO_Q17->CMT_FIFO_L_LOGIC_OUTS13_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q17" }, "CMT_FIFO_L.CMT_IN_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS0_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q20" }, "CMT_FIFO_L.CMT_IN_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS4_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q21" }, "CMT_FIFO_L.CMT_IN_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS5_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q22" }, "CMT_FIFO_L.CMT_IN_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS1_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q23" }, "CMT_FIFO_L.CMT_IN_FIFO_Q24->CMT_FIFO_L_LOGIC_OUTS12_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q24" }, "CMT_FIFO_L.CMT_IN_FIFO_Q25->CMT_FIFO_L_LOGIC_OUTS8_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q25" }, "CMT_FIFO_L.CMT_IN_FIFO_Q26->CMT_FIFO_L_LOGIC_OUTS9_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q26" }, "CMT_FIFO_L.CMT_IN_FIFO_Q27->CMT_FIFO_L_LOGIC_OUTS13_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q27" }, "CMT_FIFO_L.CMT_IN_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS0_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q30" }, "CMT_FIFO_L.CMT_IN_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS4_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q31" }, "CMT_FIFO_L.CMT_IN_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS5_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q32" }, "CMT_FIFO_L.CMT_IN_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS1_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q33" }, "CMT_FIFO_L.CMT_IN_FIFO_Q34->CMT_FIFO_L_LOGIC_OUTS12_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q34" }, "CMT_FIFO_L.CMT_IN_FIFO_Q35->CMT_FIFO_L_LOGIC_OUTS8_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q35" }, "CMT_FIFO_L.CMT_IN_FIFO_Q36->CMT_FIFO_L_LOGIC_OUTS9_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q36" }, "CMT_FIFO_L.CMT_IN_FIFO_Q37->CMT_FIFO_L_LOGIC_OUTS13_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q37" }, "CMT_FIFO_L.CMT_IN_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS0_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q40" }, "CMT_FIFO_L.CMT_IN_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS4_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q41" }, "CMT_FIFO_L.CMT_IN_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS5_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q42" }, "CMT_FIFO_L.CMT_IN_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS1_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q43" }, "CMT_FIFO_L.CMT_IN_FIFO_Q44->CMT_FIFO_L_LOGIC_OUTS12_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q44" }, "CMT_FIFO_L.CMT_IN_FIFO_Q45->CMT_FIFO_L_LOGIC_OUTS8_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q45" }, "CMT_FIFO_L.CMT_IN_FIFO_Q46->CMT_FIFO_L_LOGIC_OUTS9_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q46" }, "CMT_FIFO_L.CMT_IN_FIFO_Q47->CMT_FIFO_L_LOGIC_OUTS13_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q47" }, "CMT_FIFO_L.CMT_IN_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS0_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q50" }, "CMT_FIFO_L.CMT_IN_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS4_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q51" }, "CMT_FIFO_L.CMT_IN_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS5_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q52" }, "CMT_FIFO_L.CMT_IN_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS1_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q53" }, "CMT_FIFO_L.CMT_IN_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS12_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q54" }, "CMT_FIFO_L.CMT_IN_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS8_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q55" }, "CMT_FIFO_L.CMT_IN_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS9_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q56" }, "CMT_FIFO_L.CMT_IN_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS13_5": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_5", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q57" }, "CMT_FIFO_L.CMT_IN_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS0_8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q60" }, "CMT_FIFO_L.CMT_IN_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS4_8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q61" }, "CMT_FIFO_L.CMT_IN_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS5_8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q62" }, "CMT_FIFO_L.CMT_IN_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS1_8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q63" }, "CMT_FIFO_L.CMT_IN_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS12_8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q64" }, "CMT_FIFO_L.CMT_IN_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS8_8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q65" }, "CMT_FIFO_L.CMT_IN_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS9_8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q66" }, "CMT_FIFO_L.CMT_IN_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS13_8": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_8", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q67" }, "CMT_FIFO_L.CMT_IN_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS0_9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q70" }, "CMT_FIFO_L.CMT_IN_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS4_9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q71" }, "CMT_FIFO_L.CMT_IN_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS5_9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q72" }, "CMT_FIFO_L.CMT_IN_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS1_9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q73" }, "CMT_FIFO_L.CMT_IN_FIFO_Q74->CMT_FIFO_L_LOGIC_OUTS12_9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q74" }, "CMT_FIFO_L.CMT_IN_FIFO_Q75->CMT_FIFO_L_LOGIC_OUTS8_9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q75" }, "CMT_FIFO_L.CMT_IN_FIFO_Q76->CMT_FIFO_L_LOGIC_OUTS9_9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q76" }, "CMT_FIFO_L.CMT_IN_FIFO_Q77->CMT_FIFO_L_LOGIC_OUTS13_9": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q77" }, "CMT_FIFO_L.CMT_IN_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS0_10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q80" }, "CMT_FIFO_L.CMT_IN_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS4_10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q81" }, "CMT_FIFO_L.CMT_IN_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS5_10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q82" }, "CMT_FIFO_L.CMT_IN_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS1_10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q83" }, "CMT_FIFO_L.CMT_IN_FIFO_Q84->CMT_FIFO_L_LOGIC_OUTS12_10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q84" }, "CMT_FIFO_L.CMT_IN_FIFO_Q85->CMT_FIFO_L_LOGIC_OUTS8_10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q85" }, "CMT_FIFO_L.CMT_IN_FIFO_Q86->CMT_FIFO_L_LOGIC_OUTS9_10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q86" }, "CMT_FIFO_L.CMT_IN_FIFO_Q87->CMT_FIFO_L_LOGIC_OUTS13_10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q87" }, "CMT_FIFO_L.CMT_IN_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS0_11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q90" }, "CMT_FIFO_L.CMT_IN_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS4_11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q91" }, "CMT_FIFO_L.CMT_IN_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS5_11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q92" }, "CMT_FIFO_L.CMT_IN_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS1_11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q93" }, "CMT_FIFO_L.CMT_IN_FIFO_Q94->CMT_FIFO_L_LOGIC_OUTS12_11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q94" }, "CMT_FIFO_L.CMT_IN_FIFO_Q95->CMT_FIFO_L_LOGIC_OUTS8_11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q95" }, "CMT_FIFO_L.CMT_IN_FIFO_Q96->CMT_FIFO_L_LOGIC_OUTS9_11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q96" }, "CMT_FIFO_L.CMT_IN_FIFO_Q97->CMT_FIFO_L_LOGIC_OUTS13_11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_IN_FIFO_Q97" }, "CMT_FIFO_L.CMT_OUT_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_ALMOSTEMPTY" }, "CMT_FIFO_L.CMT_OUT_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_ALMOSTFULL" }, "CMT_FIFO_L.CMT_OUT_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_EMPTY" }, "CMT_FIFO_L.CMT_OUT_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_6": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_6", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_FULL" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS22_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q00" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS19_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q01" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS11_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q02" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS20_0": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_0", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q03" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS22_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q10" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS19_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q11" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS11_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q12" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS20_1": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_1", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q13" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS22_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q20" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS19_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q21" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS11_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q22" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS20_2": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_2", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q23" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS22_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q30" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS19_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q31" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS11_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q32" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS20_3": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_3", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q33" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS22_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q40" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS19_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q41" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS11_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_4", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q42" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS20_4": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": 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"dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_9", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q73" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS22_10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q80" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS19_10": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_10", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q81" }, 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null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q90" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS19_11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q91" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS11_11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q92" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS20_11": { "can_invert": "0", "dst_to_src": { "delay": null, "in_cap": null, "res": "0.000" }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_11", "is_directional": "1", "is_pass_transistor": 1, "is_pseudo": "0", "src_to_dst": { "delay": null, "in_cap": null, "res": "0.000" }, "src_wire": "CMT_OUT_FIFO_Q93" } }, "sites": [ { "name": "X0Y0", "prefix": "IN_FIFO", "site_pins": { "ALMOSTEMPTY": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "CMT_IN_FIFO_ALMOSTEMPTY" }, "ALMOSTFULL": { "delay": [ "0.000", "0.000", "0.000", "0.000" ], "res": "0.0", "wire": "CMT_IN_FIFO_ALMOSTFULL" }, "D00": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "CMT_IN_FIFO_D00" }, "D01": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "CMT_IN_FIFO_D01" }, "D02": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "CMT_IN_FIFO_D02" }, "D03": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "CMT_IN_FIFO_D03" }, "D10": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", "0.000" ], "wire": "CMT_IN_FIFO_D10" }, "D11": { "cap": "0.000", "delay": [ "0.000", "0.000", "0.000", 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